2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org>
6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer
14 * in this position and unchanged.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #ifndef WITHOUT_CAPSICUM
37 #include <sys/capsicum.h>
39 #include <sys/limits.h>
40 #include <sys/ioctl.h>
42 #include <net/ethernet.h>
43 #include <netinet/in.h>
44 #include <netinet/tcp.h>
46 #ifndef WITHOUT_CAPSICUM
47 #include <capsicum_helpers.h>
60 #include <pthread_np.h>
62 #include "e1000_regs.h"
63 #include "e1000_defines.h"
74 #include "net_utils.h"
75 #include "net_backends.h"
77 /* Hardware/register definitions XXX: move some to common code. */
78 #define E82545_VENDOR_ID_INTEL 0x8086
79 #define E82545_DEV_ID_82545EM_COPPER 0x100F
80 #define E82545_SUBDEV_ID 0x1008
82 #define E82545_REVISION_4 4
84 #define E82545_MDIC_DATA_MASK 0x0000FFFF
85 #define E82545_MDIC_OP_MASK 0x0c000000
86 #define E82545_MDIC_IE 0x20000000
88 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */
89 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */
90 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */
92 #define E82545_BAR_REGISTER 0
93 #define E82545_BAR_REGISTER_LEN (128*1024)
94 #define E82545_BAR_FLASH 1
95 #define E82545_BAR_FLASH_LEN (64*1024)
96 #define E82545_BAR_IO 2
97 #define E82545_BAR_IO_LEN 8
99 #define E82545_IOADDR 0x00000000
100 #define E82545_IODATA 0x00000004
101 #define E82545_IO_REGISTER_MAX 0x0001FFFF
102 #define E82545_IO_FLASH_BASE 0x00080000
103 #define E82545_IO_FLASH_MAX 0x000FFFFF
105 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2))
106 #define E82545_RAR_MAX 15
107 #define E82545_MTA_MAX 127
108 #define E82545_VFTA_MAX 127
110 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits,
111 * followed by 6 address bits.
112 * TODO: make opcode bits and addr bits configurable?
113 * NVM Commands - Microwire */
114 #define E82545_NVM_OPCODE_BITS 3
115 #define E82545_NVM_ADDR_BITS 6
116 #define E82545_NVM_DATA_BITS 16
117 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS)
118 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1)
119 #define E82545_NVM_OPCODE_MASK \
120 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS)
121 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */
122 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */
123 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */
124 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */
126 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */
128 #define E1000_ICR_SRPD 0x00010000
130 /* This is an arbitrary number. There is no hard limit on the chip. */
131 #define I82545_MAX_TXSEGS 64
133 /* Legacy receive descriptor */
134 struct e1000_rx_desc {
135 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
136 uint16_t length; /* Length of data DMAed into data buffer */
137 uint16_t csum; /* Packet checksum */
138 uint8_t status; /* Descriptor status */
139 uint8_t errors; /* Descriptor Errors */
143 /* Transmit descriptor types */
144 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000)
145 #define E1000_TXD_TYP_L (0)
146 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C)
147 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)
149 /* Legacy transmit descriptor */
150 struct e1000_tx_desc {
151 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
155 uint16_t length; /* Data buffer length */
156 uint8_t cso; /* Checksum offset */
157 uint8_t cmd; /* Descriptor control */
163 uint8_t status; /* Descriptor status */
164 uint8_t css; /* Checksum start */
170 /* Context descriptor */
171 struct e1000_context_desc {
175 uint8_t ipcss; /* IP checksum start */
176 uint8_t ipcso; /* IP checksum offset */
177 uint16_t ipcse; /* IP checksum end */
183 uint8_t tucss; /* TCP checksum start */
184 uint8_t tucso; /* TCP checksum offset */
185 uint16_t tucse; /* TCP checksum end */
188 uint32_t cmd_and_length;
192 uint8_t status; /* Descriptor status */
193 uint8_t hdr_len; /* Header length */
194 uint16_t mss; /* Maximum segment size */
199 /* Data descriptor */
200 struct e1000_data_desc {
201 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
205 uint16_t length; /* Data buffer length */
213 uint8_t status; /* Descriptor status */
214 uint8_t popts; /* Packet Options */
220 union e1000_tx_udesc {
221 struct e1000_tx_desc td;
222 struct e1000_context_desc cd;
223 struct e1000_data_desc dd;
226 /* Tx checksum info for a packet. */
228 int ck_valid; /* ck_info is valid */
229 uint8_t ck_start; /* start byte of cksum calcuation */
230 uint8_t ck_off; /* offset of cksum insertion */
231 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */
237 static int e82545_debug = 0;
238 #define WPRINTF(msg,params...) PRINTLN("e82545: " msg, ##params)
239 #define DPRINTF(msg,params...) if (e82545_debug) WPRINTF(msg, params)
241 #define MIN(a,b) (((a)<(b))?(a):(b))
242 #define MAX(a,b) (((a)>(b))?(a):(b))
244 /* s/w representation of the RAL/RAH regs */
248 struct ether_addr eu_eth;
252 struct e82545_softc {
253 struct pci_devinst *esc_pi;
254 struct vmctx *esc_ctx;
255 struct mevent *esc_mevpitr;
256 pthread_mutex_t esc_mtx;
257 struct ether_addr esc_mac;
258 net_backend_t *esc_be;
261 uint32_t esc_CTRL; /* x0000 device ctl */
262 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */
263 uint32_t esc_FCAH; /* x002C flow ctl addr hi */
264 uint32_t esc_FCT; /* x0030 flow ctl type */
265 uint32_t esc_VET; /* x0038 VLAN eth type */
266 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */
267 uint32_t esc_LEDCTL; /* x0E00 LED control */
268 uint32_t esc_PBA; /* x1000 pkt buffer allocation */
270 /* Interrupt control */
271 int esc_irq_asserted;
272 uint32_t esc_ICR; /* x00C0 cause read/clear */
273 uint32_t esc_ITR; /* x00C4 intr throttling */
274 uint32_t esc_ICS; /* x00C8 cause set */
275 uint32_t esc_IMS; /* x00D0 mask set/read */
276 uint32_t esc_IMC; /* x00D8 mask clear */
279 union e1000_tx_udesc *esc_txdesc;
280 struct e1000_context_desc esc_txctx;
281 pthread_t esc_tx_tid;
282 pthread_cond_t esc_tx_cond;
285 uint32_t esc_TXCW; /* x0178 transmit config */
286 uint32_t esc_TCTL; /* x0400 transmit ctl */
287 uint32_t esc_TIPG; /* x0410 inter-packet gap */
288 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */
289 uint64_t esc_tdba; /* verified 64-bit desc table addr */
290 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */
291 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */
292 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */
293 uint16_t esc_TDH; /* x3810 desc table head idx */
294 uint16_t esc_TDHr; /* internal read version of TDH */
295 uint16_t esc_TDT; /* x3818 desc table tail idx */
296 uint32_t esc_TIDV; /* x3820 intr delay */
297 uint32_t esc_TXDCTL; /* x3828 desc control */
298 uint32_t esc_TADV; /* x382C intr absolute delay */
300 /* L2 frame acceptance */
301 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */
302 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */
303 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */
306 struct e1000_rx_desc *esc_rxdesc;
307 pthread_cond_t esc_rx_cond;
311 uint32_t esc_RCTL; /* x0100 receive ctl */
312 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */
313 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */
314 uint64_t esc_rdba; /* verified 64-bit desc table addr */
315 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */
316 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/
317 uint32_t esc_RDLEN; /* x2808 #descriptors */
318 uint16_t esc_RDH; /* x2810 desc table head idx */
319 uint16_t esc_RDT; /* x2818 desc table tail idx */
320 uint32_t esc_RDTR; /* x2820 intr delay */
321 uint32_t esc_RXDCTL; /* x2828 desc control */
322 uint32_t esc_RADV; /* x282C intr absolute delay */
323 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */
324 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */
326 /* IO Port register access */
329 /* Shadow copy of MDIC */
330 uint32_t mdi_control;
331 /* Shadow copy of EECD */
332 uint32_t eeprom_control;
333 /* Latest NVM in/out */
337 uint32_t missed_pkt_count; /* dropped for no room in rx queue */
338 uint32_t pkt_rx_by_size[6];
339 uint32_t pkt_tx_by_size[6];
340 uint32_t good_pkt_rx_count;
341 uint32_t bcast_pkt_rx_count;
342 uint32_t mcast_pkt_rx_count;
343 uint32_t good_pkt_tx_count;
344 uint32_t bcast_pkt_tx_count;
345 uint32_t mcast_pkt_tx_count;
346 uint32_t oversize_rx_count;
347 uint32_t tso_tx_count;
348 uint64_t good_octets_rx;
349 uint64_t good_octets_tx;
350 uint64_t missed_octets; /* counts missed and oversized */
352 uint8_t nvm_bits:6; /* number of bits remaining in/out */
354 #define E82545_NVM_MODE_OPADDR 0x0
355 #define E82545_NVM_MODE_DATAIN 0x1
356 #define E82545_NVM_MODE_DATAOUT 0x2
358 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
361 static void e82545_reset(struct e82545_softc *sc, int dev);
362 static void e82545_rx_enable(struct e82545_softc *sc);
363 static void e82545_rx_disable(struct e82545_softc *sc);
364 static void e82545_rx_callback(int fd, enum ev_type type, void *param);
365 static void e82545_tx_start(struct e82545_softc *sc);
366 static void e82545_tx_enable(struct e82545_softc *sc);
367 static void e82545_tx_disable(struct e82545_softc *sc);
369 static inline int __unused
370 e82545_size_stat_index(uint32_t size)
374 } else if (size >= 1024) {
378 return (ffs(size) - 6);
383 e82545_init_eeprom(struct e82545_softc *sc)
385 uint16_t checksum, i;
388 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) |
389 (((uint16_t)sc->esc_mac.octet[1]) << 8);
390 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) |
391 (((uint16_t)sc->esc_mac.octet[3]) << 8);
392 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) |
393 (((uint16_t)sc->esc_mac.octet[5]) << 8);
396 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID;
397 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL;
398 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER;
399 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL;
401 /* fill in the checksum */
403 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
404 checksum += sc->eeprom_data[i];
406 checksum = NVM_SUM - checksum;
407 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum;
408 DPRINTF("eeprom checksum: 0x%x", checksum);
412 e82545_write_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr,
413 uint8_t phy_addr, uint32_t data)
415 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data);
419 e82545_read_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr,
422 //DPRINTF("Read mdi reg:0x%x phy:0x%x", reg_addr, phy_addr);
425 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS |
426 MII_SR_AUTONEG_COMPLETE);
427 case PHY_AUTONEG_ADV:
428 return NWAY_AR_SELECTOR_FIELD;
431 case PHY_1000T_STATUS:
432 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS |
433 SR_1000T_LOCAL_RX_STATUS);
435 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF;
437 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF;
439 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr);
446 e82545_eecd_strobe(struct e82545_softc *sc)
448 /* Microwire state machine */
450 DPRINTF("eeprom state machine srtobe "
451 "0x%x 0x%x 0x%x 0x%x",
452 sc->nvm_mode, sc->nvm_bits,
453 sc->nvm_opaddr, sc->nvm_data);*/
455 if (sc->nvm_bits == 0) {
456 DPRINTF("eeprom state machine not expecting data! "
457 "0x%x 0x%x 0x%x 0x%x",
458 sc->nvm_mode, sc->nvm_bits,
459 sc->nvm_opaddr, sc->nvm_data);
463 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) {
465 if (sc->nvm_data & 0x8000) {
466 sc->eeprom_control |= E1000_EECD_DO;
468 sc->eeprom_control &= ~E1000_EECD_DO;
471 if (sc->nvm_bits == 0) {
472 /* read done, back to opcode mode. */
474 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
475 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
477 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) {
480 if (sc->eeprom_control & E1000_EECD_DI) {
483 if (sc->nvm_bits == 0) {
485 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK;
486 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK;
487 if (op != E82545_NVM_OPCODE_WRITE) {
488 DPRINTF("Illegal eeprom write op 0x%x",
490 } else if (addr >= E82545_NVM_EEPROM_SIZE) {
491 DPRINTF("Illegal eeprom write addr 0x%x",
494 DPRINTF("eeprom write eeprom[0x%x] = 0x%x",
496 sc->eeprom_data[addr] = sc->nvm_data;
498 /* back to opcode mode */
500 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
501 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
503 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) {
504 sc->nvm_opaddr <<= 1;
505 if (sc->eeprom_control & E1000_EECD_DI) {
508 if (sc->nvm_bits == 0) {
509 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK;
511 case E82545_NVM_OPCODE_EWEN:
512 DPRINTF("eeprom write enable: 0x%x",
514 /* back to opcode mode */
516 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
517 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
519 case E82545_NVM_OPCODE_READ:
521 uint16_t addr = sc->nvm_opaddr &
522 E82545_NVM_ADDR_MASK;
523 sc->nvm_mode = E82545_NVM_MODE_DATAOUT;
524 sc->nvm_bits = E82545_NVM_DATA_BITS;
525 if (addr < E82545_NVM_EEPROM_SIZE) {
526 sc->nvm_data = sc->eeprom_data[addr];
527 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x",
530 DPRINTF("eeprom illegal read: 0x%x",
536 case E82545_NVM_OPCODE_WRITE:
537 sc->nvm_mode = E82545_NVM_MODE_DATAIN;
538 sc->nvm_bits = E82545_NVM_DATA_BITS;
542 DPRINTF("eeprom unknown op: 0x%x",
544 /* back to opcode mode */
546 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
547 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
551 DPRINTF("eeprom state machine wrong state! "
552 "0x%x 0x%x 0x%x 0x%x",
553 sc->nvm_mode, sc->nvm_bits,
554 sc->nvm_opaddr, sc->nvm_data);
559 e82545_itr_callback(int fd __unused, enum ev_type type __unused, void *param)
562 struct e82545_softc *sc = param;
564 pthread_mutex_lock(&sc->esc_mtx);
565 new = sc->esc_ICR & sc->esc_IMS;
566 if (new && !sc->esc_irq_asserted) {
567 DPRINTF("itr callback: lintr assert %x", new);
568 sc->esc_irq_asserted = 1;
569 pci_lintr_assert(sc->esc_pi);
571 mevent_delete(sc->esc_mevpitr);
572 sc->esc_mevpitr = NULL;
574 pthread_mutex_unlock(&sc->esc_mtx);
578 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits)
582 DPRINTF("icr assert: 0x%x", bits);
585 * An interrupt is only generated if bits are set that
586 * aren't already in the ICR, these bits are unmasked,
587 * and there isn't an interrupt already pending.
589 new = bits & ~sc->esc_ICR & sc->esc_IMS;
593 DPRINTF("icr assert: masked %x, ims %x", new, sc->esc_IMS);
594 } else if (sc->esc_mevpitr != NULL) {
595 DPRINTF("icr assert: throttled %x, ims %x", new, sc->esc_IMS);
596 } else if (!sc->esc_irq_asserted) {
597 DPRINTF("icr assert: lintr assert %x", new);
598 sc->esc_irq_asserted = 1;
599 pci_lintr_assert(sc->esc_pi);
600 if (sc->esc_ITR != 0) {
601 sc->esc_mevpitr = mevent_add(
602 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */
603 EVF_TIMER, e82545_itr_callback, sc);
609 e82545_ims_change(struct e82545_softc *sc, uint32_t bits)
614 * Changing the mask may allow previously asserted
615 * but masked interrupt requests to generate an interrupt.
617 new = bits & sc->esc_ICR & ~sc->esc_IMS;
621 DPRINTF("ims change: masked %x, ims %x", new, sc->esc_IMS);
622 } else if (sc->esc_mevpitr != NULL) {
623 DPRINTF("ims change: throttled %x, ims %x", new, sc->esc_IMS);
624 } else if (!sc->esc_irq_asserted) {
625 DPRINTF("ims change: lintr assert %x", new);
626 sc->esc_irq_asserted = 1;
627 pci_lintr_assert(sc->esc_pi);
628 if (sc->esc_ITR != 0) {
629 sc->esc_mevpitr = mevent_add(
630 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */
631 EVF_TIMER, e82545_itr_callback, sc);
637 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits)
640 DPRINTF("icr deassert: 0x%x", bits);
641 sc->esc_ICR &= ~bits;
644 * If there are no longer any interrupt sources and there
645 * was an asserted interrupt, clear it
647 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) {
648 DPRINTF("icr deassert: lintr deassert %x", bits);
649 pci_lintr_deassert(sc->esc_pi);
650 sc->esc_irq_asserted = 0;
655 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value)
658 DPRINTF("intr_write: off %x, val %x", offset, value);
662 e82545_icr_deassert(sc, value);
668 sc->esc_ICS = value; /* not used: store for debug */
669 e82545_icr_assert(sc, value);
672 e82545_ims_change(sc, value);
675 sc->esc_IMC = value; /* for debug */
676 sc->esc_IMS &= ~value;
677 // XXX clear interrupts if all ICR bits now masked
678 // and interrupt was pending ?
686 e82545_intr_read(struct e82545_softc *sc, uint32_t offset)
692 DPRINTF("intr_read: off %x", offset);
696 retval = sc->esc_ICR;
698 e82545_icr_deassert(sc, ~0);
701 retval = sc->esc_ITR;
704 /* write-only register */
707 retval = sc->esc_IMS;
710 /* write-only register */
720 e82545_devctl(struct e82545_softc *sc, uint32_t val)
723 sc->esc_CTRL = val & ~E1000_CTRL_RST;
725 if (val & E1000_CTRL_RST) {
726 DPRINTF("e1k: s/w reset, ctl %x", val);
729 /* XXX check for phy reset ? */
733 e82545_rx_update_rdba(struct e82545_softc *sc)
736 /* XXX verify desc base/len within phys mem range */
737 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 |
740 /* Cache host mapping of guest descriptor array */
741 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx,
742 sc->esc_rdba, sc->esc_RDLEN);
746 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val)
750 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN);
752 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */
753 sc->esc_RCTL = val & ~0xF9204c01;
755 DPRINTF("rx_ctl - %s RCTL %x, val %x",
756 on ? "on" : "off", sc->esc_RCTL, val);
758 /* state change requested */
759 if (on != sc->esc_rx_enabled) {
761 /* Catch disallowed/unimplemented settings */
762 //assert(!(val & E1000_RCTL_LBM_TCVR));
764 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) {
765 sc->esc_rx_loopback = 1;
767 sc->esc_rx_loopback = 0;
770 e82545_rx_update_rdba(sc);
771 e82545_rx_enable(sc);
773 e82545_rx_disable(sc);
774 sc->esc_rx_loopback = 0;
776 sc->esc_rxdesc = NULL;
782 e82545_tx_update_tdba(struct e82545_softc *sc)
785 /* XXX verify desc base/len within phys mem range */
786 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL;
788 /* Cache host mapping of guest descriptor array */
789 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba,
794 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val)
798 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN);
800 /* ignore TCTL_EN settings that don't change state */
801 if (on == sc->esc_tx_enabled)
805 e82545_tx_update_tdba(sc);
806 e82545_tx_enable(sc);
808 e82545_tx_disable(sc);
810 sc->esc_txdesc = NULL;
813 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */
814 sc->esc_TCTL = val & ~0xFE800005;
818 e82545_bufsz(uint32_t rctl)
821 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) {
822 case (E1000_RCTL_SZ_2048): return (2048);
823 case (E1000_RCTL_SZ_1024): return (1024);
824 case (E1000_RCTL_SZ_512): return (512);
825 case (E1000_RCTL_SZ_256): return (256);
826 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384);
827 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192);
828 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096);
830 return (256); /* Forbidden value. */
833 /* XXX one packet at a time until this is debugged */
835 e82545_rx_callback(int fd __unused, enum ev_type type __unused, void *param)
837 struct e82545_softc *sc = param;
838 struct e1000_rx_desc *rxd;
839 struct iovec vec[64];
841 int left, lim, maxpktsz, maxpktdesc, bufsz, i, n, size;
843 uint16_t *tp, tag, head;
845 pthread_mutex_lock(&sc->esc_mtx);
846 DPRINTF("rx_run: head %x, tail %x", sc->esc_RDH, sc->esc_RDT);
848 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) {
849 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped",
850 sc->esc_rx_enabled, sc->esc_rx_loopback);
851 while (netbe_rx_discard(sc->esc_be) > 0) {
855 bufsz = e82545_bufsz(sc->esc_RCTL);
856 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522;
857 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz;
858 size = sc->esc_RDLEN / 16;
860 left = (size + sc->esc_RDT - head) % size;
861 if (left < maxpktdesc) {
862 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped",
864 while (netbe_rx_discard(sc->esc_be) > 0) {
869 sc->esc_rx_active = 1;
870 pthread_mutex_unlock(&sc->esc_mtx);
872 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) {
874 /* Grab rx descriptor pointed to by the head pointer */
875 for (i = 0; i < maxpktdesc; i++) {
876 rxd = &sc->esc_rxdesc[(head + i) % size];
877 vec[i].iov_base = paddr_guest2host(sc->esc_ctx,
878 rxd->buffer_addr, bufsz);
879 vec[i].iov_len = bufsz;
881 len = netbe_recv(sc->esc_be, vec, maxpktdesc);
883 DPRINTF("netbe_recv() returned %zd", len);
888 * Adjust the packet length based on whether the CRC needs
889 * to be stripped or if the packet is less than the minimum
892 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
893 len = ETHER_MIN_LEN - ETHER_CRC_LEN;
894 if (!(sc->esc_RCTL & E1000_RCTL_SECRC))
895 len += ETHER_CRC_LEN;
896 n = (len + bufsz - 1) / bufsz;
898 DPRINTF("packet read %zd bytes, %d segs, head %d",
901 /* Apply VLAN filter. */
902 tp = (uint16_t *)vec[0].iov_base + 6;
903 if ((sc->esc_RCTL & E1000_RCTL_VFE) &&
904 (ntohs(tp[0]) == sc->esc_VET)) {
905 tag = ntohs(tp[1]) & 0x0fff;
906 if ((sc->esc_fvlan[tag >> 5] &
907 (1 << (tag & 0x1f))) != 0) {
908 DPRINTF("known VLAN %d", tag);
910 DPRINTF("unknown VLAN %d", tag);
916 /* Update all consumed descriptors. */
917 for (i = 0; i < n - 1; i++) {
918 rxd = &sc->esc_rxdesc[(head + i) % size];
923 rxd->status = E1000_RXD_STAT_DD;
925 rxd = &sc->esc_rxdesc[(head + i) % size];
926 rxd->length = len % bufsz;
930 /* XXX signal no checksum for now */
931 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM |
932 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD;
934 /* Schedule receive interrupts. */
935 if ((uint32_t)len <= sc->esc_RSRPD) {
936 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0;
938 /* XXX: RDRT and RADV timers should be here. */
939 cause |= E1000_ICR_RXT0;
942 head = (head + n) % size;
947 pthread_mutex_lock(&sc->esc_mtx);
948 sc->esc_rx_active = 0;
949 if (sc->esc_rx_enabled == 0)
950 pthread_cond_signal(&sc->esc_rx_cond);
953 /* Respect E1000_RCTL_RDMTS */
954 left = (size + sc->esc_RDT - head) % size;
955 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1)))
956 cause |= E1000_ICR_RXDMT0;
957 /* Assert all accumulated interrupts. */
959 e82545_icr_assert(sc, cause);
961 DPRINTF("rx_run done: head %x, tail %x", sc->esc_RDH, sc->esc_RDT);
962 pthread_mutex_unlock(&sc->esc_mtx);
966 e82545_carry(uint32_t sum)
969 sum = (sum & 0xFFFF) + (sum >> 16);
976 e82545_buf_checksum(uint8_t *buf, int len)
981 /* Checksum all the pairs of bytes first... */
982 for (i = 0; i < (len & ~1); i += 2)
983 sum += *((u_int16_t *)(buf + i));
986 * If there's a single byte left over, checksum it, too.
987 * Network byte order is big-endian, so the remaining byte is
991 sum += htons(buf[i] << 8);
993 return (e82545_carry(sum));
997 e82545_iov_checksum(struct iovec *iov, int iovcnt, unsigned int off,
1000 unsigned int now, odd;
1001 uint32_t sum = 0, s;
1003 /* Skip completely unneeded vectors. */
1004 while (iovcnt > 0 && iov->iov_len <= off && off > 0) {
1005 off -= iov->iov_len;
1010 /* Calculate checksum of requested range. */
1012 while (len > 0 && iovcnt > 0) {
1013 now = MIN(len, iov->iov_len - off);
1014 s = e82545_buf_checksum((uint8_t *)iov->iov_base + off, now);
1015 sum += odd ? (s << 8) : s;
1023 return (e82545_carry(sum));
1027 * Return the transmit descriptor type.
1030 e82545_txdesc_type(uint32_t lower)
1036 if (lower & E1000_TXD_CMD_DEXT)
1037 type = lower & E1000_TXD_MASK;
1043 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck)
1048 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d",
1049 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len);
1050 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1U : UINT_MAX;
1051 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen);
1052 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum;
1056 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt)
1059 if (sc->esc_be == NULL)
1062 (void) netbe_send(sc->esc_be, iov, iovcnt);
1066 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail,
1067 uint16_t dsize, int *tdwb)
1069 union e1000_tx_udesc *dsc;
1071 for ( ; head != tail; head = (head + 1) % dsize) {
1072 dsc = &sc->esc_txdesc[head];
1073 if (dsc->td.lower.data & E1000_TXD_CMD_RS) {
1074 dsc->td.upper.data |= E1000_TXD_STAT_DD;
1081 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail,
1082 uint16_t dsize, uint16_t *rhead, int *tdwb)
1084 uint8_t *hdr, *hdrp;
1085 struct iovec iovb[I82545_MAX_TXSEGS + 2];
1086 struct iovec tiov[I82545_MAX_TXSEGS + 2];
1087 struct e1000_context_desc *cd;
1088 struct ck_info ckinfo[2];
1090 union e1000_tx_udesc *dsc;
1091 int desc, dtype, ntype, iovcnt, tcp, tso, paylen, seg, tiovcnt, pv;
1092 unsigned hdrlen, vlen, pktlen, len, left, mss, now, nnow, nleft, pvoff;
1093 uint32_t tcpsum, tcpseq;
1094 uint16_t ipcs, tcpcs, ipid, ohead;
1097 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0;
1105 /* iovb[0/1] may be used for writable copy of headers. */
1108 for (desc = 0; ; desc++, head = (head + 1) % dsize) {
1113 dsc = &sc->esc_txdesc[head];
1114 dtype = e82545_txdesc_type(dsc->td.lower.data);
1118 case E1000_TXD_TYP_C:
1119 DPRINTF("tx ctxt desc idx %d: %016jx "
1121 head, dsc->td.buffer_addr,
1122 dsc->td.upper.data, dsc->td.lower.data);
1123 /* Save context and return */
1124 sc->esc_txctx = dsc->cd;
1126 case E1000_TXD_TYP_L:
1127 DPRINTF("tx legacy desc idx %d: %08x%08x",
1128 head, dsc->td.upper.data, dsc->td.lower.data);
1130 * legacy cksum start valid in first descriptor
1133 ckinfo[0].ck_start = dsc->td.upper.fields.css;
1135 case E1000_TXD_TYP_D:
1136 DPRINTF("tx data desc idx %d: %08x%08x",
1137 head, dsc->td.upper.data, dsc->td.lower.data);
1144 /* Descriptor type must be consistent */
1145 assert(dtype == ntype);
1146 DPRINTF("tx next desc idx %d: %08x%08x",
1147 head, dsc->td.upper.data, dsc->td.lower.data);
1150 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length :
1151 dsc->dd.lower.data & 0xFFFFF;
1153 /* Strip checksum supplied by guest. */
1154 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 &&
1155 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) {
1157 WPRINTF("final descriptor too short (%d) -- dropped",
1164 if (len > 0 && iovcnt < I82545_MAX_TXSEGS) {
1165 iov[iovcnt].iov_base = paddr_guest2host(sc->esc_ctx,
1166 dsc->td.buffer_addr, len);
1167 iov[iovcnt].iov_len = len;
1173 * Pull out info that is valid in the final descriptor
1174 * and exit descriptor loop.
1176 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) {
1177 if (dtype == E1000_TXD_TYP_L) {
1178 if (dsc->td.lower.data & E1000_TXD_CMD_IC) {
1179 ckinfo[0].ck_valid = 1;
1181 dsc->td.lower.flags.cso;
1182 ckinfo[0].ck_len = 0;
1185 cd = &sc->esc_txctx;
1186 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE)
1188 if (dsc->dd.upper.fields.popts &
1189 E1000_TXD_POPTS_IXSM)
1190 ckinfo[0].ck_valid = 1;
1191 if (dsc->dd.upper.fields.popts &
1192 E1000_TXD_POPTS_IXSM || tso) {
1193 ckinfo[0].ck_start =
1194 cd->lower_setup.ip_fields.ipcss;
1196 cd->lower_setup.ip_fields.ipcso;
1198 cd->lower_setup.ip_fields.ipcse;
1200 if (dsc->dd.upper.fields.popts &
1201 E1000_TXD_POPTS_TXSM)
1202 ckinfo[1].ck_valid = 1;
1203 if (dsc->dd.upper.fields.popts &
1204 E1000_TXD_POPTS_TXSM || tso) {
1205 ckinfo[1].ck_start =
1206 cd->upper_setup.tcp_fields.tucss;
1208 cd->upper_setup.tcp_fields.tucso;
1210 cd->upper_setup.tcp_fields.tucse;
1220 if (iovcnt > I82545_MAX_TXSEGS) {
1221 WPRINTF("tx too many descriptors (%d > %d) -- dropped",
1222 iovcnt, I82545_MAX_TXSEGS);
1227 /* Estimate writable space for VLAN header insertion. */
1228 if ((sc->esc_CTRL & E1000_CTRL_VME) &&
1229 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) {
1230 hdrlen = ETHER_ADDR_LEN*2;
1231 vlen = ETHER_VLAN_ENCAP_LEN;
1234 /* Estimate required writable space for checksums. */
1235 if (ckinfo[0].ck_valid)
1236 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2U);
1237 if (ckinfo[1].ck_valid)
1238 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2U);
1239 /* Round up writable space to the first vector. */
1240 if (hdrlen != 0 && iov[0].iov_len > hdrlen &&
1241 iov[0].iov_len < hdrlen + 100)
1242 hdrlen = iov[0].iov_len;
1244 /* In case of TSO header length provided by software. */
1245 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len;
1248 * Cap the header length at 240 based on 7.2.4.5 of
1249 * the Intel 82576EB (Rev 2.63) datasheet.
1252 WPRINTF("TSO hdrlen too large: %d", hdrlen);
1257 * If VLAN insertion is requested, ensure the header
1258 * at least holds the amount of data copied during
1259 * VLAN insertion below.
1261 * XXX: Realistic packets will include a full Ethernet
1262 * header before the IP header at ckinfo[0].ck_start,
1263 * but this check is sufficient to prevent
1264 * out-of-bounds access below.
1266 if (vlen != 0 && hdrlen < ETHER_ADDR_LEN*2) {
1267 WPRINTF("TSO hdrlen too small for vlan insertion "
1268 "(%d vs %d) -- dropped", hdrlen,
1274 * Ensure that the header length covers the used fields
1275 * in the IP and TCP headers as well as the IP and TCP
1276 * checksums. The following fields are accessed below:
1278 * Header | Field | Offset | Length
1279 * -------+-------+--------+-------
1280 * IPv4 | len | 2 | 2
1282 * IPv6 | len | 4 | 2
1283 * TCP | seq # | 4 | 4
1284 * TCP | flags | 13 | 1
1287 if (hdrlen < ckinfo[0].ck_start + 6U ||
1288 hdrlen < ckinfo[0].ck_off + 2U) {
1289 WPRINTF("TSO hdrlen too small for IP fields (%d) "
1290 "-- dropped", hdrlen);
1293 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) {
1294 if (hdrlen < ckinfo[1].ck_start + 14U) {
1295 WPRINTF("TSO hdrlen too small for TCP fields "
1296 "(%d) -- dropped", hdrlen);
1300 if (hdrlen < ckinfo[1].ck_start + 8U) {
1301 WPRINTF("TSO hdrlen too small for UDP fields "
1302 "(%d) -- dropped", hdrlen);
1306 if (ckinfo[1].ck_valid && hdrlen < ckinfo[1].ck_off + 2U) {
1307 WPRINTF("TSO hdrlen too small for TCP/UDP fields "
1308 "(%d) -- dropped", hdrlen);
1313 if (pktlen < hdrlen + vlen) {
1314 WPRINTF("packet too small for writable header");
1318 /* Allocate, fill and prepend writable header vector. */
1319 if (hdrlen + vlen != 0) {
1320 hdr = __builtin_alloca(hdrlen + vlen);
1322 for (left = hdrlen, hdrp = hdr; left > 0;
1323 left -= now, hdrp += now) {
1324 now = MIN(left, iov->iov_len);
1325 memcpy(hdrp, iov->iov_base, now);
1326 iov->iov_base = (uint8_t *)iov->iov_base + now;
1327 iov->iov_len -= now;
1328 if (iov->iov_len == 0) {
1335 iov->iov_base = hdr;
1336 iov->iov_len = hdrlen;
1340 /* Insert VLAN tag. */
1342 hdr -= ETHER_VLAN_ENCAP_LEN;
1343 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2);
1344 hdrlen += ETHER_VLAN_ENCAP_LEN;
1345 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8;
1346 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff;
1347 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8;
1348 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff;
1349 iov->iov_base = hdr;
1350 iov->iov_len += ETHER_VLAN_ENCAP_LEN;
1351 /* Correct checksum offsets after VLAN tag insertion. */
1352 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN;
1353 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN;
1354 if (ckinfo[0].ck_len != 0)
1355 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN;
1356 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN;
1357 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN;
1358 if (ckinfo[1].ck_len != 0)
1359 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN;
1362 /* Simple non-TSO case. */
1364 /* Calculate checksums and transmit. */
1365 if (ckinfo[0].ck_valid)
1366 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]);
1367 if (ckinfo[1].ck_valid)
1368 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]);
1369 e82545_transmit_backend(sc, iov, iovcnt);
1374 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0;
1375 mss = sc->esc_txctx.tcp_seg_setup.fields.mss;
1376 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff);
1377 DPRINTF("tx %s segmentation offload %d+%d/%u bytes %d iovs",
1378 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt);
1379 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]);
1382 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]);
1383 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off];
1385 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */
1386 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off];
1389 for (seg = 0, left = paylen; left > 0; seg++, left -= now) {
1390 now = MIN(left, mss);
1392 /* Construct IOVs for the segment. */
1393 /* Include whole original header. */
1394 tiov[0].iov_base = hdr;
1395 tiov[0].iov_len = hdrlen;
1397 /* Include respective part of payload IOV. */
1398 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) {
1399 nnow = MIN(nleft, iov[pv].iov_len - pvoff);
1400 tiov[tiovcnt].iov_base = (uint8_t *)iov[pv].iov_base +
1402 tiov[tiovcnt++].iov_len = nnow;
1403 if (pvoff + nnow == iov[pv].iov_len) {
1409 DPRINTF("tx segment %d %d+%d bytes %d iovs",
1410 seg, hdrlen, now, tiovcnt);
1412 /* Update IP header. */
1413 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) {
1414 /* IPv4 -- set length and ID */
1415 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] =
1416 htons(hdrlen - ckinfo[0].ck_start + now);
1417 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] =
1420 /* IPv6 -- set length */
1421 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] =
1422 htons(hdrlen - ckinfo[0].ck_start - 40 +
1426 /* Update pseudo-header checksum. */
1428 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now);
1430 /* Update TCP/UDP headers. */
1432 /* Update sequence number and FIN/PUSH flags. */
1433 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] =
1434 htonl(tcpseq + paylen - left);
1436 hdr[ckinfo[1].ck_start + 13] &=
1437 ~(TH_FIN | TH_PUSH);
1440 /* Update payload length. */
1441 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] =
1442 hdrlen - ckinfo[1].ck_start + now;
1445 /* Calculate checksums and transmit. */
1446 if (ckinfo[0].ck_valid) {
1447 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs;
1448 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]);
1450 if (ckinfo[1].ck_valid) {
1451 *(uint16_t *)&hdr[ckinfo[1].ck_off] =
1452 e82545_carry(tcpsum);
1453 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]);
1455 e82545_transmit_backend(sc, tiov, tiovcnt);
1459 head = (head + 1) % dsize;
1460 e82545_transmit_done(sc, ohead, head, dsize, tdwb);
1467 e82545_tx_run(struct e82545_softc *sc)
1470 uint16_t head, rhead, tail, size;
1471 int lim, tdwb, sent;
1473 size = sc->esc_TDLEN / 16;
1477 head = sc->esc_TDH % size;
1478 tail = sc->esc_TDT % size;
1479 DPRINTF("tx_run: head %x, rhead %x, tail %x",
1480 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT);
1482 pthread_mutex_unlock(&sc->esc_mtx);
1485 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) {
1486 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb);
1491 pthread_mutex_lock(&sc->esc_mtx);
1494 sc->esc_TDHr = rhead;
1497 cause |= E1000_ICR_TXDW;
1498 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT)
1499 cause |= E1000_ICR_TXQE;
1501 e82545_icr_assert(sc, cause);
1503 DPRINTF("tx_run done: head %x, rhead %x, tail %x",
1504 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT);
1507 static _Noreturn void *
1508 e82545_tx_thread(void *param)
1510 struct e82545_softc *sc = param;
1512 pthread_mutex_lock(&sc->esc_mtx);
1514 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) {
1515 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT)
1517 sc->esc_tx_active = 0;
1518 if (sc->esc_tx_enabled == 0)
1519 pthread_cond_signal(&sc->esc_tx_cond);
1520 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx);
1522 sc->esc_tx_active = 1;
1524 /* Process some tx descriptors. Lock dropped inside. */
1530 e82545_tx_start(struct e82545_softc *sc)
1533 if (sc->esc_tx_active == 0)
1534 pthread_cond_signal(&sc->esc_tx_cond);
1538 e82545_tx_enable(struct e82545_softc *sc)
1541 sc->esc_tx_enabled = 1;
1545 e82545_tx_disable(struct e82545_softc *sc)
1548 sc->esc_tx_enabled = 0;
1549 while (sc->esc_tx_active)
1550 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx);
1554 e82545_rx_enable(struct e82545_softc *sc)
1557 sc->esc_rx_enabled = 1;
1561 e82545_rx_disable(struct e82545_softc *sc)
1564 sc->esc_rx_enabled = 0;
1565 while (sc->esc_rx_active)
1566 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx);
1570 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
1578 eu = &sc->esc_uni[idx];
1582 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV);
1583 eu->eu_addrsel = (wval >> 16) & 0x3;
1584 eu->eu_eth.octet[5] = wval >> 8;
1585 eu->eu_eth.octet[4] = wval;
1588 eu->eu_eth.octet[3] = wval >> 24;
1589 eu->eu_eth.octet[2] = wval >> 16;
1590 eu->eu_eth.octet[1] = wval >> 8;
1591 eu->eu_eth.octet[0] = wval;
1596 e82545_read_ra(struct e82545_softc *sc, int reg)
1605 eu = &sc->esc_uni[idx];
1609 retval = (eu->eu_valid << 31) |
1610 (eu->eu_addrsel << 16) |
1611 (eu->eu_eth.octet[5] << 8) |
1612 eu->eu_eth.octet[4];
1615 retval = (eu->eu_eth.octet[3] << 24) |
1616 (eu->eu_eth.octet[2] << 16) |
1617 (eu->eu_eth.octet[1] << 8) |
1618 eu->eu_eth.octet[0];
1625 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value)
1630 DPRINTF("Unaligned register write offset:0x%x value:0x%x", offset, value);
1633 DPRINTF("Register write: 0x%x value: 0x%x", offset, value);
1637 case E1000_CTRL_DUP:
1638 e82545_devctl(sc, value);
1641 sc->esc_FCAL = value;
1644 sc->esc_FCAH = value & ~0xFFFF0000;
1647 sc->esc_FCT = value & ~0xFFFF0000;
1650 sc->esc_VET = value & ~0xFFFF0000;
1653 sc->esc_FCTTV = value & ~0xFFFF0000;
1656 sc->esc_LEDCTL = value & ~0x30303000;
1659 sc->esc_PBA = value & 0x0000FF80;
1666 e82545_intr_write(sc, offset, value);
1669 e82545_rx_ctl(sc, value);
1672 sc->esc_FCRTL = value & ~0xFFFF0007;
1675 sc->esc_FCRTH = value & ~0xFFFF0007;
1677 case E1000_RDBAL(0):
1678 sc->esc_RDBAL = value & ~0xF;
1679 if (sc->esc_rx_enabled) {
1680 /* Apparently legal: update cached address */
1681 e82545_rx_update_rdba(sc);
1684 case E1000_RDBAH(0):
1685 assert(!sc->esc_rx_enabled);
1686 sc->esc_RDBAH = value;
1688 case E1000_RDLEN(0):
1689 assert(!sc->esc_rx_enabled);
1690 sc->esc_RDLEN = value & ~0xFFF0007F;
1693 /* XXX should only ever be zero ? Range check ? */
1694 sc->esc_RDH = value;
1697 /* XXX if this opens up the rx ring, do something ? */
1698 sc->esc_RDT = value;
1701 /* ignore FPD bit 31 */
1702 sc->esc_RDTR = value & ~0xFFFF0000;
1704 case E1000_RXDCTL(0):
1705 sc->esc_RXDCTL = value & ~0xFEC0C0C0;
1708 sc->esc_RADV = value & ~0xFFFF0000;
1711 sc->esc_RSRPD = value & ~0xFFFFF000;
1714 sc->esc_RXCSUM = value & ~0xFFFFF800;
1717 sc->esc_TXCW = value & ~0x3FFF0000;
1720 e82545_tx_ctl(sc, value);
1723 sc->esc_TIPG = value;
1726 sc->esc_AIT = value;
1728 case E1000_TDBAL(0):
1729 sc->esc_TDBAL = value & ~0xF;
1730 if (sc->esc_tx_enabled)
1731 e82545_tx_update_tdba(sc);
1733 case E1000_TDBAH(0):
1734 sc->esc_TDBAH = value;
1735 if (sc->esc_tx_enabled)
1736 e82545_tx_update_tdba(sc);
1738 case E1000_TDLEN(0):
1739 sc->esc_TDLEN = value & ~0xFFF0007F;
1740 if (sc->esc_tx_enabled)
1741 e82545_tx_update_tdba(sc);
1744 if (sc->esc_tx_enabled) {
1745 WPRINTF("ignoring write to TDH while transmit enabled");
1749 WPRINTF("ignoring non-zero value written to TDH");
1752 sc->esc_TDHr = sc->esc_TDH = value;
1755 sc->esc_TDT = value;
1756 if (sc->esc_tx_enabled)
1757 e82545_tx_start(sc);
1760 sc->esc_TIDV = value & ~0xFFFF0000;
1762 case E1000_TXDCTL(0):
1763 //assert(!sc->esc_tx_enabled);
1764 sc->esc_TXDCTL = value & ~0xC0C0C0;
1767 sc->esc_TADV = value & ~0xFFFF0000;
1769 case E1000_RAL(0) ... E1000_RAH(15):
1770 /* convert to u32 offset */
1771 ridx = (offset - E1000_RAL(0)) >> 2;
1772 e82545_write_ra(sc, ridx, value);
1774 case E1000_MTA ... (E1000_MTA + (127*4)):
1775 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value;
1777 case E1000_VFTA ... (E1000_VFTA + (127*4)):
1778 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value;
1782 //DPRINTF("EECD write 0x%x -> 0x%x", sc->eeprom_control, value);
1783 /* edge triggered low->high */
1784 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ?
1785 0 : (value & E1000_EECD_SK));
1786 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS|
1787 E1000_EECD_DI|E1000_EECD_REQ);
1788 sc->eeprom_control &= ~eecd_mask;
1789 sc->eeprom_control |= (value & eecd_mask);
1790 /* grant/revoke immediately */
1791 if (value & E1000_EECD_REQ) {
1792 sc->eeprom_control |= E1000_EECD_GNT;
1794 sc->eeprom_control &= ~E1000_EECD_GNT;
1796 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) {
1797 e82545_eecd_strobe(sc);
1803 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >>
1804 E1000_MDIC_REG_SHIFT);
1805 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >>
1806 E1000_MDIC_PHY_SHIFT);
1808 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST));
1809 if ((value & E1000_MDIC_READY) != 0) {
1810 DPRINTF("Incorrect MDIC ready bit: 0x%x", value);
1813 switch (value & E82545_MDIC_OP_MASK) {
1814 case E1000_MDIC_OP_READ:
1815 sc->mdi_control &= ~E82545_MDIC_DATA_MASK;
1816 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr);
1818 case E1000_MDIC_OP_WRITE:
1819 e82545_write_mdi(sc, reg_addr, phy_addr,
1820 value & E82545_MDIC_DATA_MASK);
1823 DPRINTF("Unknown MDIC op: 0x%x", value);
1826 /* TODO: barrier? */
1827 sc->mdi_control |= E1000_MDIC_READY;
1828 if (value & E82545_MDIC_IE) {
1829 // TODO: generate interrupt
1837 DPRINTF("Unknown write register: 0x%x value:%x", offset, value);
1843 e82545_read_register(struct e82545_softc *sc, uint32_t offset)
1849 DPRINTF("Unaligned register read offset:0x%x", offset);
1853 DPRINTF("Register read: 0x%x", offset);
1857 retval = sc->esc_CTRL;
1860 retval = E1000_STATUS_FD | E1000_STATUS_LU |
1861 E1000_STATUS_SPEED_1000;
1864 retval = sc->esc_FCAL;
1867 retval = sc->esc_FCAH;
1870 retval = sc->esc_FCT;
1873 retval = sc->esc_VET;
1876 retval = sc->esc_FCTTV;
1879 retval = sc->esc_LEDCTL;
1882 retval = sc->esc_PBA;
1889 retval = e82545_intr_read(sc, offset);
1892 retval = sc->esc_RCTL;
1895 retval = sc->esc_FCRTL;
1898 retval = sc->esc_FCRTH;
1900 case E1000_RDBAL(0):
1901 retval = sc->esc_RDBAL;
1903 case E1000_RDBAH(0):
1904 retval = sc->esc_RDBAH;
1906 case E1000_RDLEN(0):
1907 retval = sc->esc_RDLEN;
1910 retval = sc->esc_RDH;
1913 retval = sc->esc_RDT;
1916 retval = sc->esc_RDTR;
1918 case E1000_RXDCTL(0):
1919 retval = sc->esc_RXDCTL;
1922 retval = sc->esc_RADV;
1925 retval = sc->esc_RSRPD;
1928 retval = sc->esc_RXCSUM;
1931 retval = sc->esc_TXCW;
1934 retval = sc->esc_TCTL;
1937 retval = sc->esc_TIPG;
1940 retval = sc->esc_AIT;
1942 case E1000_TDBAL(0):
1943 retval = sc->esc_TDBAL;
1945 case E1000_TDBAH(0):
1946 retval = sc->esc_TDBAH;
1948 case E1000_TDLEN(0):
1949 retval = sc->esc_TDLEN;
1952 retval = sc->esc_TDH;
1955 retval = sc->esc_TDT;
1958 retval = sc->esc_TIDV;
1960 case E1000_TXDCTL(0):
1961 retval = sc->esc_TXDCTL;
1964 retval = sc->esc_TADV;
1966 case E1000_RAL(0) ... E1000_RAH(15):
1967 /* convert to u32 offset */
1968 ridx = (offset - E1000_RAL(0)) >> 2;
1969 retval = e82545_read_ra(sc, ridx);
1971 case E1000_MTA ... (E1000_MTA + (127*4)):
1972 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2];
1974 case E1000_VFTA ... (E1000_VFTA + (127*4)):
1975 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2];
1978 //DPRINTF("EECD read %x", sc->eeprom_control);
1979 retval = sc->eeprom_control;
1982 retval = sc->mdi_control;
1987 /* stats that we emulate. */
1989 retval = sc->missed_pkt_count;
1992 retval = sc->pkt_rx_by_size[0];
1995 retval = sc->pkt_rx_by_size[1];
1998 retval = sc->pkt_rx_by_size[2];
2001 retval = sc->pkt_rx_by_size[3];
2004 retval = sc->pkt_rx_by_size[4];
2007 retval = sc->pkt_rx_by_size[5];
2010 retval = sc->good_pkt_rx_count;
2013 retval = sc->bcast_pkt_rx_count;
2016 retval = sc->mcast_pkt_rx_count;
2020 retval = sc->good_pkt_tx_count;
2023 retval = (uint32_t)sc->good_octets_rx;
2026 retval = (uint32_t)(sc->good_octets_rx >> 32);
2030 retval = (uint32_t)sc->good_octets_tx;
2034 retval = (uint32_t)(sc->good_octets_tx >> 32);
2037 retval = sc->oversize_rx_count;
2040 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets);
2043 retval = (uint32_t)((sc->good_octets_rx +
2044 sc->missed_octets) >> 32);
2047 retval = sc->good_pkt_rx_count + sc->missed_pkt_count +
2048 sc->oversize_rx_count;
2051 retval = sc->pkt_tx_by_size[0];
2054 retval = sc->pkt_tx_by_size[1];
2057 retval = sc->pkt_tx_by_size[2];
2060 retval = sc->pkt_tx_by_size[3];
2063 retval = sc->pkt_tx_by_size[4];
2066 retval = sc->pkt_tx_by_size[5];
2069 retval = sc->mcast_pkt_tx_count;
2072 retval = sc->bcast_pkt_tx_count;
2075 retval = sc->tso_tx_count;
2077 /* stats that are always 0. */
2079 case E1000_ALGNERRC:
2108 DPRINTF("Unknown read register: 0x%x", offset);
2117 e82545_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2120 struct e82545_softc *sc;
2122 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d", baridx, offset, value, size);
2126 pthread_mutex_lock(&sc->esc_mtx);
2133 DPRINTF("Wrong io addr write sz:%d value:0x%lx", size, value);
2135 sc->io_addr = (uint32_t)value;
2139 DPRINTF("Wrong io data write size:%d value:0x%lx", size, value);
2140 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) {
2141 DPRINTF("Non-register io write addr:0x%x value:0x%lx", sc->io_addr, value);
2143 e82545_write_register(sc, sc->io_addr,
2147 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d", offset, value, size);
2151 case E82545_BAR_REGISTER:
2153 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx", size, offset, value);
2155 e82545_write_register(sc, (uint32_t)offset,
2159 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d",
2160 baridx, offset, value, size);
2163 pthread_mutex_unlock(&sc->esc_mtx);
2167 e82545_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
2169 struct e82545_softc *sc;
2172 //DPRINTF("Read bar:%d offset:0x%lx size:%d", baridx, offset, size);
2176 pthread_mutex_lock(&sc->esc_mtx);
2183 DPRINTF("Wrong io addr read sz:%d", size);
2185 retval = sc->io_addr;
2189 DPRINTF("Wrong io data read sz:%d", size);
2191 if (sc->io_addr > E82545_IO_REGISTER_MAX) {
2192 DPRINTF("Non-register io read addr:0x%x",
2195 retval = e82545_read_register(sc, sc->io_addr);
2198 DPRINTF("Unknown io bar read offset:0x%lx size:%d",
2203 case E82545_BAR_REGISTER:
2205 DPRINTF("Wrong register read size:%d offset:0x%lx",
2208 retval = e82545_read_register(sc, (uint32_t)offset);
2211 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d",
2212 baridx, offset, size);
2216 pthread_mutex_unlock(&sc->esc_mtx);
2222 e82545_reset(struct e82545_softc *sc, int drvr)
2226 e82545_rx_disable(sc);
2227 e82545_tx_disable(sc);
2229 /* clear outstanding interrupts */
2230 if (sc->esc_irq_asserted)
2231 pci_lintr_deassert(sc->esc_pi);
2241 sc->esc_LEDCTL = 0x07061302;
2242 sc->esc_PBA = 0x00100030;
2244 /* start nvm in opcode mode. */
2246 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
2247 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
2248 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN;
2249 e82545_init_eeprom(sc);
2260 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan));
2261 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast));
2262 memset(sc->esc_uni, 0, sizeof(sc->esc_uni));
2264 /* XXX not necessary on 82545 ?? */
2265 sc->esc_uni[0].eu_valid = 1;
2266 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet,
2269 /* Clear RAH valid bits */
2270 for (i = 0; i < 16; i++)
2271 sc->esc_uni[i].eu_valid = 0;
2286 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */
2300 sc->esc_txdesc = NULL;
2305 sc->esc_TDHr = sc->esc_TDH = 0;
2310 e82545_init(struct pci_devinst *pi, nvlist_t *nvl)
2313 struct e82545_softc *sc;
2317 /* Setup our softc */
2318 sc = calloc(1, sizeof(*sc));
2322 sc->esc_ctx = pi->pi_vmctx;
2324 pthread_mutex_init(&sc->esc_mtx, NULL);
2325 pthread_cond_init(&sc->esc_rx_cond, NULL);
2326 pthread_cond_init(&sc->esc_tx_cond, NULL);
2327 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc);
2328 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot,
2330 pthread_set_name_np(sc->esc_tx_tid, nstr);
2332 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER);
2333 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL);
2334 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK);
2335 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET);
2336 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID);
2337 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL);
2339 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL);
2340 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1);
2342 /* TODO: this card also supports msi, but the freebsd driver for it
2343 * does not, so I have not implemented it. */
2344 pci_lintr_request(pi);
2346 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32,
2347 E82545_BAR_REGISTER_LEN);
2348 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32,
2349 E82545_BAR_FLASH_LEN);
2350 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO,
2353 mac = get_config_value_node(nvl, "mac");
2355 err = net_parsemac(mac, sc->esc_mac.octet);
2361 net_genmac(pi, sc->esc_mac.octet);
2363 err = netbe_init(&sc->esc_be, nvl, e82545_rx_callback, sc);
2369 netbe_rx_enable(sc->esc_be);
2371 /* H/w initiated reset */
2372 e82545_reset(sc, 0);
2377 #ifdef BHYVE_SNAPSHOT
2379 e82545_snapshot(struct vm_snapshot_meta *meta)
2383 struct e82545_softc *sc;
2384 struct pci_devinst *pi;
2385 uint64_t bitmap_value;
2387 pi = meta->dev_data;
2390 /* esc_mevp and esc_mevpitr should be reinitiated at init. */
2391 SNAPSHOT_VAR_OR_LEAVE(sc->esc_mac, meta, ret, done);
2394 SNAPSHOT_VAR_OR_LEAVE(sc->esc_CTRL, meta, ret, done);
2395 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCAL, meta, ret, done);
2396 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCAH, meta, ret, done);
2397 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCT, meta, ret, done);
2398 SNAPSHOT_VAR_OR_LEAVE(sc->esc_VET, meta, ret, done);
2399 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCTTV, meta, ret, done);
2400 SNAPSHOT_VAR_OR_LEAVE(sc->esc_LEDCTL, meta, ret, done);
2401 SNAPSHOT_VAR_OR_LEAVE(sc->esc_PBA, meta, ret, done);
2403 /* Interrupt control */
2404 SNAPSHOT_VAR_OR_LEAVE(sc->esc_irq_asserted, meta, ret, done);
2405 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ICR, meta, ret, done);
2406 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ITR, meta, ret, done);
2407 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ICS, meta, ret, done);
2408 SNAPSHOT_VAR_OR_LEAVE(sc->esc_IMS, meta, ret, done);
2409 SNAPSHOT_VAR_OR_LEAVE(sc->esc_IMC, meta, ret, done);
2414 * The fields in the unions are in superposition to access certain
2415 * bytes in the larger uint variables.
2416 * e.g., ip_config = [ipcss|ipcso|ipcse0|ipcse1]
2418 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.lower_setup.ip_config, meta, ret, done);
2419 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.upper_setup.tcp_config, meta, ret, done);
2420 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.cmd_and_length, meta, ret, done);
2421 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.tcp_seg_setup.data, meta, ret, done);
2423 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tx_enabled, meta, ret, done);
2424 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tx_active, meta, ret, done);
2425 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TXCW, meta, ret, done);
2426 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TCTL, meta, ret, done);
2427 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TIPG, meta, ret, done);
2428 SNAPSHOT_VAR_OR_LEAVE(sc->esc_AIT, meta, ret, done);
2429 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tdba, meta, ret, done);
2430 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDBAL, meta, ret, done);
2431 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDBAH, meta, ret, done);
2432 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDLEN, meta, ret, done);
2433 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDH, meta, ret, done);
2434 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDHr, meta, ret, done);
2435 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDT, meta, ret, done);
2436 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TIDV, meta, ret, done);
2437 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TXDCTL, meta, ret, done);
2438 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TADV, meta, ret, done);
2440 /* Has dependency on esc_TDLEN; reoreder of fields from struct. */
2441 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, sc->esc_txdesc,
2442 sc->esc_TDLEN, true, meta, ret, done);
2444 /* L2 frame acceptance */
2445 for (i = 0; i < (int)nitems(sc->esc_uni); i++) {
2446 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_valid, meta, ret, done);
2447 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_addrsel, meta, ret, done);
2448 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_eth, meta, ret, done);
2451 SNAPSHOT_BUF_OR_LEAVE(sc->esc_fmcast, sizeof(sc->esc_fmcast),
2453 SNAPSHOT_BUF_OR_LEAVE(sc->esc_fvlan, sizeof(sc->esc_fvlan),
2457 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_enabled, meta, ret, done);
2458 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_active, meta, ret, done);
2459 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_loopback, meta, ret, done);
2460 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RCTL, meta, ret, done);
2461 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCRTL, meta, ret, done);
2462 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCRTH, meta, ret, done);
2463 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rdba, meta, ret, done);
2464 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDBAL, meta, ret, done);
2465 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDBAH, meta, ret, done);
2466 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDLEN, meta, ret, done);
2467 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDH, meta, ret, done);
2468 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDT, meta, ret, done);
2469 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDTR, meta, ret, done);
2470 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RXDCTL, meta, ret, done);
2471 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RADV, meta, ret, done);
2472 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RSRPD, meta, ret, done);
2473 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RXCSUM, meta, ret, done);
2475 /* Has dependency on esc_RDLEN; reoreder of fields from struct. */
2476 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, sc->esc_rxdesc,
2477 sc->esc_TDLEN, true, meta, ret, done);
2479 /* IO Port register access */
2480 SNAPSHOT_VAR_OR_LEAVE(sc->io_addr, meta, ret, done);
2482 /* Shadow copy of MDIC */
2483 SNAPSHOT_VAR_OR_LEAVE(sc->mdi_control, meta, ret, done);
2485 /* Shadow copy of EECD */
2486 SNAPSHOT_VAR_OR_LEAVE(sc->eeprom_control, meta, ret, done);
2488 /* Latest NVM in/out */
2489 SNAPSHOT_VAR_OR_LEAVE(sc->nvm_data, meta, ret, done);
2490 SNAPSHOT_VAR_OR_LEAVE(sc->nvm_opaddr, meta, ret, done);
2493 SNAPSHOT_VAR_OR_LEAVE(sc->missed_pkt_count, meta, ret, done);
2494 SNAPSHOT_BUF_OR_LEAVE(sc->pkt_rx_by_size, sizeof(sc->pkt_rx_by_size),
2496 SNAPSHOT_BUF_OR_LEAVE(sc->pkt_tx_by_size, sizeof(sc->pkt_tx_by_size),
2498 SNAPSHOT_VAR_OR_LEAVE(sc->good_pkt_rx_count, meta, ret, done);
2499 SNAPSHOT_VAR_OR_LEAVE(sc->bcast_pkt_rx_count, meta, ret, done);
2500 SNAPSHOT_VAR_OR_LEAVE(sc->mcast_pkt_rx_count, meta, ret, done);
2501 SNAPSHOT_VAR_OR_LEAVE(sc->good_pkt_tx_count, meta, ret, done);
2502 SNAPSHOT_VAR_OR_LEAVE(sc->bcast_pkt_tx_count, meta, ret, done);
2503 SNAPSHOT_VAR_OR_LEAVE(sc->mcast_pkt_tx_count, meta, ret, done);
2504 SNAPSHOT_VAR_OR_LEAVE(sc->oversize_rx_count, meta, ret, done);
2505 SNAPSHOT_VAR_OR_LEAVE(sc->tso_tx_count, meta, ret, done);
2506 SNAPSHOT_VAR_OR_LEAVE(sc->good_octets_rx, meta, ret, done);
2507 SNAPSHOT_VAR_OR_LEAVE(sc->good_octets_tx, meta, ret, done);
2508 SNAPSHOT_VAR_OR_LEAVE(sc->missed_octets, meta, ret, done);
2510 if (meta->op == VM_SNAPSHOT_SAVE)
2511 bitmap_value = sc->nvm_bits;
2512 SNAPSHOT_VAR_OR_LEAVE(bitmap_value, meta, ret, done);
2513 if (meta->op == VM_SNAPSHOT_RESTORE)
2514 sc->nvm_bits = bitmap_value;
2516 if (meta->op == VM_SNAPSHOT_SAVE)
2517 bitmap_value = sc->nvm_bits;
2518 SNAPSHOT_VAR_OR_LEAVE(bitmap_value, meta, ret, done);
2519 if (meta->op == VM_SNAPSHOT_RESTORE)
2520 sc->nvm_bits = bitmap_value;
2523 SNAPSHOT_BUF_OR_LEAVE(sc->eeprom_data, sizeof(sc->eeprom_data),
2531 static const struct pci_devemu pci_de_e82545 = {
2533 .pe_init = e82545_init,
2534 .pe_legacy_config = netbe_legacy_config,
2535 .pe_barwrite = e82545_write,
2536 .pe_barread = e82545_read,
2537 #ifdef BHYVE_SNAPSHOT
2538 .pe_snapshot = e82545_snapshot,
2541 PCI_EMUL_SET(pci_de_e82545);