2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org>
6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer
14 * in this position and unchanged.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #ifndef WITHOUT_CAPSICUM
37 #include <sys/capsicum.h>
39 #include <sys/limits.h>
40 #include <sys/ioctl.h>
42 #include <net/ethernet.h>
43 #include <netinet/in.h>
44 #include <netinet/tcp.h>
46 #ifndef WITHOUT_CAPSICUM
47 #include <capsicum_helpers.h>
49 #include <machine/vmm_snapshot.h>
61 #include <pthread_np.h>
63 #include "e1000_regs.h"
64 #include "e1000_defines.h"
72 #include "net_utils.h"
73 #include "net_backends.h"
75 /* Hardware/register definitions XXX: move some to common code. */
76 #define E82545_VENDOR_ID_INTEL 0x8086
77 #define E82545_DEV_ID_82545EM_COPPER 0x100F
78 #define E82545_SUBDEV_ID 0x1008
80 #define E82545_REVISION_4 4
82 #define E82545_MDIC_DATA_MASK 0x0000FFFF
83 #define E82545_MDIC_OP_MASK 0x0c000000
84 #define E82545_MDIC_IE 0x20000000
86 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */
87 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */
88 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */
90 #define E82545_BAR_REGISTER 0
91 #define E82545_BAR_REGISTER_LEN (128*1024)
92 #define E82545_BAR_FLASH 1
93 #define E82545_BAR_FLASH_LEN (64*1024)
94 #define E82545_BAR_IO 2
95 #define E82545_BAR_IO_LEN 8
97 #define E82545_IOADDR 0x00000000
98 #define E82545_IODATA 0x00000004
99 #define E82545_IO_REGISTER_MAX 0x0001FFFF
100 #define E82545_IO_FLASH_BASE 0x00080000
101 #define E82545_IO_FLASH_MAX 0x000FFFFF
103 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2))
104 #define E82545_RAR_MAX 15
105 #define E82545_MTA_MAX 127
106 #define E82545_VFTA_MAX 127
108 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits,
109 * followed by 6 address bits.
110 * TODO: make opcode bits and addr bits configurable?
111 * NVM Commands - Microwire */
112 #define E82545_NVM_OPCODE_BITS 3
113 #define E82545_NVM_ADDR_BITS 6
114 #define E82545_NVM_DATA_BITS 16
115 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS)
116 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1)
117 #define E82545_NVM_OPCODE_MASK \
118 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS)
119 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */
120 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */
121 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */
122 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */
124 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */
126 #define E1000_ICR_SRPD 0x00010000
128 /* This is an arbitrary number. There is no hard limit on the chip. */
129 #define I82545_MAX_TXSEGS 64
131 /* Legacy receive descriptor */
132 struct e1000_rx_desc {
133 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
134 uint16_t length; /* Length of data DMAed into data buffer */
135 uint16_t csum; /* Packet checksum */
136 uint8_t status; /* Descriptor status */
137 uint8_t errors; /* Descriptor Errors */
141 /* Transmit descriptor types */
142 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000)
143 #define E1000_TXD_TYP_L (0)
144 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C)
145 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)
147 /* Legacy transmit descriptor */
148 struct e1000_tx_desc {
149 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
153 uint16_t length; /* Data buffer length */
154 uint8_t cso; /* Checksum offset */
155 uint8_t cmd; /* Descriptor control */
161 uint8_t status; /* Descriptor status */
162 uint8_t css; /* Checksum start */
168 /* Context descriptor */
169 struct e1000_context_desc {
173 uint8_t ipcss; /* IP checksum start */
174 uint8_t ipcso; /* IP checksum offset */
175 uint16_t ipcse; /* IP checksum end */
181 uint8_t tucss; /* TCP checksum start */
182 uint8_t tucso; /* TCP checksum offset */
183 uint16_t tucse; /* TCP checksum end */
186 uint32_t cmd_and_length;
190 uint8_t status; /* Descriptor status */
191 uint8_t hdr_len; /* Header length */
192 uint16_t mss; /* Maximum segment size */
197 /* Data descriptor */
198 struct e1000_data_desc {
199 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
203 uint16_t length; /* Data buffer length */
211 uint8_t status; /* Descriptor status */
212 uint8_t popts; /* Packet Options */
218 union e1000_tx_udesc {
219 struct e1000_tx_desc td;
220 struct e1000_context_desc cd;
221 struct e1000_data_desc dd;
224 /* Tx checksum info for a packet. */
226 int ck_valid; /* ck_info is valid */
227 uint8_t ck_start; /* start byte of cksum calcuation */
228 uint8_t ck_off; /* offset of cksum insertion */
229 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */
235 static int e82545_debug = 0;
236 #define WPRINTF(msg,params...) PRINTLN("e82545: " msg, ##params)
237 #define DPRINTF(msg,params...) if (e82545_debug) WPRINTF(msg, params)
239 #define MIN(a,b) (((a)<(b))?(a):(b))
240 #define MAX(a,b) (((a)>(b))?(a):(b))
242 /* s/w representation of the RAL/RAH regs */
246 struct ether_addr eu_eth;
250 struct e82545_softc {
251 struct pci_devinst *esc_pi;
252 struct vmctx *esc_ctx;
253 struct mevent *esc_mevpitr;
254 pthread_mutex_t esc_mtx;
255 struct ether_addr esc_mac;
256 net_backend_t *esc_be;
259 uint32_t esc_CTRL; /* x0000 device ctl */
260 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */
261 uint32_t esc_FCAH; /* x002C flow ctl addr hi */
262 uint32_t esc_FCT; /* x0030 flow ctl type */
263 uint32_t esc_VET; /* x0038 VLAN eth type */
264 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */
265 uint32_t esc_LEDCTL; /* x0E00 LED control */
266 uint32_t esc_PBA; /* x1000 pkt buffer allocation */
268 /* Interrupt control */
269 int esc_irq_asserted;
270 uint32_t esc_ICR; /* x00C0 cause read/clear */
271 uint32_t esc_ITR; /* x00C4 intr throttling */
272 uint32_t esc_ICS; /* x00C8 cause set */
273 uint32_t esc_IMS; /* x00D0 mask set/read */
274 uint32_t esc_IMC; /* x00D8 mask clear */
277 union e1000_tx_udesc *esc_txdesc;
278 struct e1000_context_desc esc_txctx;
279 pthread_t esc_tx_tid;
280 pthread_cond_t esc_tx_cond;
283 uint32_t esc_TXCW; /* x0178 transmit config */
284 uint32_t esc_TCTL; /* x0400 transmit ctl */
285 uint32_t esc_TIPG; /* x0410 inter-packet gap */
286 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */
287 uint64_t esc_tdba; /* verified 64-bit desc table addr */
288 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */
289 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */
290 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */
291 uint16_t esc_TDH; /* x3810 desc table head idx */
292 uint16_t esc_TDHr; /* internal read version of TDH */
293 uint16_t esc_TDT; /* x3818 desc table tail idx */
294 uint32_t esc_TIDV; /* x3820 intr delay */
295 uint32_t esc_TXDCTL; /* x3828 desc control */
296 uint32_t esc_TADV; /* x382C intr absolute delay */
298 /* L2 frame acceptance */
299 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */
300 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */
301 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */
304 struct e1000_rx_desc *esc_rxdesc;
305 pthread_cond_t esc_rx_cond;
309 uint32_t esc_RCTL; /* x0100 receive ctl */
310 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */
311 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */
312 uint64_t esc_rdba; /* verified 64-bit desc table addr */
313 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */
314 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/
315 uint32_t esc_RDLEN; /* x2808 #descriptors */
316 uint16_t esc_RDH; /* x2810 desc table head idx */
317 uint16_t esc_RDT; /* x2818 desc table tail idx */
318 uint32_t esc_RDTR; /* x2820 intr delay */
319 uint32_t esc_RXDCTL; /* x2828 desc control */
320 uint32_t esc_RADV; /* x282C intr absolute delay */
321 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */
322 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */
324 /* IO Port register access */
327 /* Shadow copy of MDIC */
328 uint32_t mdi_control;
329 /* Shadow copy of EECD */
330 uint32_t eeprom_control;
331 /* Latest NVM in/out */
335 uint32_t missed_pkt_count; /* dropped for no room in rx queue */
336 uint32_t pkt_rx_by_size[6];
337 uint32_t pkt_tx_by_size[6];
338 uint32_t good_pkt_rx_count;
339 uint32_t bcast_pkt_rx_count;
340 uint32_t mcast_pkt_rx_count;
341 uint32_t good_pkt_tx_count;
342 uint32_t bcast_pkt_tx_count;
343 uint32_t mcast_pkt_tx_count;
344 uint32_t oversize_rx_count;
345 uint32_t tso_tx_count;
346 uint64_t good_octets_rx;
347 uint64_t good_octets_tx;
348 uint64_t missed_octets; /* counts missed and oversized */
350 uint8_t nvm_bits:6; /* number of bits remaining in/out */
352 #define E82545_NVM_MODE_OPADDR 0x0
353 #define E82545_NVM_MODE_DATAIN 0x1
354 #define E82545_NVM_MODE_DATAOUT 0x2
356 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
359 static void e82545_reset(struct e82545_softc *sc, int dev);
360 static void e82545_rx_enable(struct e82545_softc *sc);
361 static void e82545_rx_disable(struct e82545_softc *sc);
362 static void e82545_rx_callback(int fd, enum ev_type type, void *param);
363 static void e82545_tx_start(struct e82545_softc *sc);
364 static void e82545_tx_enable(struct e82545_softc *sc);
365 static void e82545_tx_disable(struct e82545_softc *sc);
367 static inline int __unused
368 e82545_size_stat_index(uint32_t size)
372 } else if (size >= 1024) {
376 return (ffs(size) - 6);
381 e82545_init_eeprom(struct e82545_softc *sc)
383 uint16_t checksum, i;
386 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) |
387 (((uint16_t)sc->esc_mac.octet[1]) << 8);
388 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) |
389 (((uint16_t)sc->esc_mac.octet[3]) << 8);
390 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) |
391 (((uint16_t)sc->esc_mac.octet[5]) << 8);
394 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID;
395 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL;
396 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER;
397 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL;
399 /* fill in the checksum */
401 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
402 checksum += sc->eeprom_data[i];
404 checksum = NVM_SUM - checksum;
405 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum;
406 DPRINTF("eeprom checksum: 0x%x", checksum);
410 e82545_write_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr,
411 uint8_t phy_addr, uint32_t data)
413 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data);
417 e82545_read_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr,
420 //DPRINTF("Read mdi reg:0x%x phy:0x%x", reg_addr, phy_addr);
423 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS |
424 MII_SR_AUTONEG_COMPLETE);
425 case PHY_AUTONEG_ADV:
426 return NWAY_AR_SELECTOR_FIELD;
429 case PHY_1000T_STATUS:
430 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS |
431 SR_1000T_LOCAL_RX_STATUS);
433 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF;
435 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF;
437 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr);
444 e82545_eecd_strobe(struct e82545_softc *sc)
446 /* Microwire state machine */
448 DPRINTF("eeprom state machine srtobe "
449 "0x%x 0x%x 0x%x 0x%x",
450 sc->nvm_mode, sc->nvm_bits,
451 sc->nvm_opaddr, sc->nvm_data);*/
453 if (sc->nvm_bits == 0) {
454 DPRINTF("eeprom state machine not expecting data! "
455 "0x%x 0x%x 0x%x 0x%x",
456 sc->nvm_mode, sc->nvm_bits,
457 sc->nvm_opaddr, sc->nvm_data);
461 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) {
463 if (sc->nvm_data & 0x8000) {
464 sc->eeprom_control |= E1000_EECD_DO;
466 sc->eeprom_control &= ~E1000_EECD_DO;
469 if (sc->nvm_bits == 0) {
470 /* read done, back to opcode mode. */
472 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
473 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
475 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) {
478 if (sc->eeprom_control & E1000_EECD_DI) {
481 if (sc->nvm_bits == 0) {
483 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK;
484 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK;
485 if (op != E82545_NVM_OPCODE_WRITE) {
486 DPRINTF("Illegal eeprom write op 0x%x",
488 } else if (addr >= E82545_NVM_EEPROM_SIZE) {
489 DPRINTF("Illegal eeprom write addr 0x%x",
492 DPRINTF("eeprom write eeprom[0x%x] = 0x%x",
494 sc->eeprom_data[addr] = sc->nvm_data;
496 /* back to opcode mode */
498 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
499 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
501 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) {
502 sc->nvm_opaddr <<= 1;
503 if (sc->eeprom_control & E1000_EECD_DI) {
506 if (sc->nvm_bits == 0) {
507 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK;
509 case E82545_NVM_OPCODE_EWEN:
510 DPRINTF("eeprom write enable: 0x%x",
512 /* back to opcode mode */
514 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
515 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
517 case E82545_NVM_OPCODE_READ:
519 uint16_t addr = sc->nvm_opaddr &
520 E82545_NVM_ADDR_MASK;
521 sc->nvm_mode = E82545_NVM_MODE_DATAOUT;
522 sc->nvm_bits = E82545_NVM_DATA_BITS;
523 if (addr < E82545_NVM_EEPROM_SIZE) {
524 sc->nvm_data = sc->eeprom_data[addr];
525 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x",
528 DPRINTF("eeprom illegal read: 0x%x",
534 case E82545_NVM_OPCODE_WRITE:
535 sc->nvm_mode = E82545_NVM_MODE_DATAIN;
536 sc->nvm_bits = E82545_NVM_DATA_BITS;
540 DPRINTF("eeprom unknown op: 0x%x",
542 /* back to opcode mode */
544 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
545 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
549 DPRINTF("eeprom state machine wrong state! "
550 "0x%x 0x%x 0x%x 0x%x",
551 sc->nvm_mode, sc->nvm_bits,
552 sc->nvm_opaddr, sc->nvm_data);
557 e82545_itr_callback(int fd __unused, enum ev_type type __unused, void *param)
560 struct e82545_softc *sc = param;
562 pthread_mutex_lock(&sc->esc_mtx);
563 new = sc->esc_ICR & sc->esc_IMS;
564 if (new && !sc->esc_irq_asserted) {
565 DPRINTF("itr callback: lintr assert %x", new);
566 sc->esc_irq_asserted = 1;
567 pci_lintr_assert(sc->esc_pi);
569 mevent_delete(sc->esc_mevpitr);
570 sc->esc_mevpitr = NULL;
572 pthread_mutex_unlock(&sc->esc_mtx);
576 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits)
580 DPRINTF("icr assert: 0x%x", bits);
583 * An interrupt is only generated if bits are set that
584 * aren't already in the ICR, these bits are unmasked,
585 * and there isn't an interrupt already pending.
587 new = bits & ~sc->esc_ICR & sc->esc_IMS;
591 DPRINTF("icr assert: masked %x, ims %x", new, sc->esc_IMS);
592 } else if (sc->esc_mevpitr != NULL) {
593 DPRINTF("icr assert: throttled %x, ims %x", new, sc->esc_IMS);
594 } else if (!sc->esc_irq_asserted) {
595 DPRINTF("icr assert: lintr assert %x", new);
596 sc->esc_irq_asserted = 1;
597 pci_lintr_assert(sc->esc_pi);
598 if (sc->esc_ITR != 0) {
599 sc->esc_mevpitr = mevent_add(
600 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */
601 EVF_TIMER, e82545_itr_callback, sc);
607 e82545_ims_change(struct e82545_softc *sc, uint32_t bits)
612 * Changing the mask may allow previously asserted
613 * but masked interrupt requests to generate an interrupt.
615 new = bits & sc->esc_ICR & ~sc->esc_IMS;
619 DPRINTF("ims change: masked %x, ims %x", new, sc->esc_IMS);
620 } else if (sc->esc_mevpitr != NULL) {
621 DPRINTF("ims change: throttled %x, ims %x", new, sc->esc_IMS);
622 } else if (!sc->esc_irq_asserted) {
623 DPRINTF("ims change: lintr assert %x", new);
624 sc->esc_irq_asserted = 1;
625 pci_lintr_assert(sc->esc_pi);
626 if (sc->esc_ITR != 0) {
627 sc->esc_mevpitr = mevent_add(
628 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */
629 EVF_TIMER, e82545_itr_callback, sc);
635 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits)
638 DPRINTF("icr deassert: 0x%x", bits);
639 sc->esc_ICR &= ~bits;
642 * If there are no longer any interrupt sources and there
643 * was an asserted interrupt, clear it
645 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) {
646 DPRINTF("icr deassert: lintr deassert %x", bits);
647 pci_lintr_deassert(sc->esc_pi);
648 sc->esc_irq_asserted = 0;
653 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value)
656 DPRINTF("intr_write: off %x, val %x", offset, value);
660 e82545_icr_deassert(sc, value);
666 sc->esc_ICS = value; /* not used: store for debug */
667 e82545_icr_assert(sc, value);
670 e82545_ims_change(sc, value);
673 sc->esc_IMC = value; /* for debug */
674 sc->esc_IMS &= ~value;
675 // XXX clear interrupts if all ICR bits now masked
676 // and interrupt was pending ?
684 e82545_intr_read(struct e82545_softc *sc, uint32_t offset)
690 DPRINTF("intr_read: off %x", offset);
694 retval = sc->esc_ICR;
696 e82545_icr_deassert(sc, ~0);
699 retval = sc->esc_ITR;
702 /* write-only register */
705 retval = sc->esc_IMS;
708 /* write-only register */
718 e82545_devctl(struct e82545_softc *sc, uint32_t val)
721 sc->esc_CTRL = val & ~E1000_CTRL_RST;
723 if (val & E1000_CTRL_RST) {
724 DPRINTF("e1k: s/w reset, ctl %x", val);
727 /* XXX check for phy reset ? */
731 e82545_rx_update_rdba(struct e82545_softc *sc)
734 /* XXX verify desc base/len within phys mem range */
735 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 |
738 /* Cache host mapping of guest descriptor array */
739 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx,
740 sc->esc_rdba, sc->esc_RDLEN);
744 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val)
748 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN);
750 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */
751 sc->esc_RCTL = val & ~0xF9204c01;
753 DPRINTF("rx_ctl - %s RCTL %x, val %x",
754 on ? "on" : "off", sc->esc_RCTL, val);
756 /* state change requested */
757 if (on != sc->esc_rx_enabled) {
759 /* Catch disallowed/unimplemented settings */
760 //assert(!(val & E1000_RCTL_LBM_TCVR));
762 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) {
763 sc->esc_rx_loopback = 1;
765 sc->esc_rx_loopback = 0;
768 e82545_rx_update_rdba(sc);
769 e82545_rx_enable(sc);
771 e82545_rx_disable(sc);
772 sc->esc_rx_loopback = 0;
774 sc->esc_rxdesc = NULL;
780 e82545_tx_update_tdba(struct e82545_softc *sc)
783 /* XXX verify desc base/len within phys mem range */
784 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL;
786 /* Cache host mapping of guest descriptor array */
787 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba,
792 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val)
796 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN);
798 /* ignore TCTL_EN settings that don't change state */
799 if (on == sc->esc_tx_enabled)
803 e82545_tx_update_tdba(sc);
804 e82545_tx_enable(sc);
806 e82545_tx_disable(sc);
808 sc->esc_txdesc = NULL;
811 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */
812 sc->esc_TCTL = val & ~0xFE800005;
816 e82545_bufsz(uint32_t rctl)
819 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) {
820 case (E1000_RCTL_SZ_2048): return (2048);
821 case (E1000_RCTL_SZ_1024): return (1024);
822 case (E1000_RCTL_SZ_512): return (512);
823 case (E1000_RCTL_SZ_256): return (256);
824 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384);
825 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192);
826 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096);
828 return (256); /* Forbidden value. */
831 /* XXX one packet at a time until this is debugged */
833 e82545_rx_callback(int fd __unused, enum ev_type type __unused, void *param)
835 struct e82545_softc *sc = param;
836 struct e1000_rx_desc *rxd;
837 struct iovec vec[64];
839 int left, lim, maxpktsz, maxpktdesc, bufsz, i, n, size;
841 uint16_t *tp, tag, head;
843 pthread_mutex_lock(&sc->esc_mtx);
844 DPRINTF("rx_run: head %x, tail %x", sc->esc_RDH, sc->esc_RDT);
846 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) {
847 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped",
848 sc->esc_rx_enabled, sc->esc_rx_loopback);
849 while (netbe_rx_discard(sc->esc_be) > 0) {
853 bufsz = e82545_bufsz(sc->esc_RCTL);
854 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522;
855 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz;
856 size = sc->esc_RDLEN / 16;
858 left = (size + sc->esc_RDT - head) % size;
859 if (left < maxpktdesc) {
860 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped",
862 while (netbe_rx_discard(sc->esc_be) > 0) {
867 sc->esc_rx_active = 1;
868 pthread_mutex_unlock(&sc->esc_mtx);
870 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) {
872 /* Grab rx descriptor pointed to by the head pointer */
873 for (i = 0; i < maxpktdesc; i++) {
874 rxd = &sc->esc_rxdesc[(head + i) % size];
875 vec[i].iov_base = paddr_guest2host(sc->esc_ctx,
876 rxd->buffer_addr, bufsz);
877 vec[i].iov_len = bufsz;
879 len = netbe_recv(sc->esc_be, vec, maxpktdesc);
881 DPRINTF("netbe_recv() returned %zd", len);
886 * Adjust the packet length based on whether the CRC needs
887 * to be stripped or if the packet is less than the minimum
890 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
891 len = ETHER_MIN_LEN - ETHER_CRC_LEN;
892 if (!(sc->esc_RCTL & E1000_RCTL_SECRC))
893 len += ETHER_CRC_LEN;
894 n = (len + bufsz - 1) / bufsz;
896 DPRINTF("packet read %zd bytes, %d segs, head %d",
899 /* Apply VLAN filter. */
900 tp = (uint16_t *)vec[0].iov_base + 6;
901 if ((sc->esc_RCTL & E1000_RCTL_VFE) &&
902 (ntohs(tp[0]) == sc->esc_VET)) {
903 tag = ntohs(tp[1]) & 0x0fff;
904 if ((sc->esc_fvlan[tag >> 5] &
905 (1 << (tag & 0x1f))) != 0) {
906 DPRINTF("known VLAN %d", tag);
908 DPRINTF("unknown VLAN %d", tag);
914 /* Update all consumed descriptors. */
915 for (i = 0; i < n - 1; i++) {
916 rxd = &sc->esc_rxdesc[(head + i) % size];
921 rxd->status = E1000_RXD_STAT_DD;
923 rxd = &sc->esc_rxdesc[(head + i) % size];
924 rxd->length = len % bufsz;
928 /* XXX signal no checksum for now */
929 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM |
930 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD;
932 /* Schedule receive interrupts. */
933 if ((uint32_t)len <= sc->esc_RSRPD) {
934 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0;
936 /* XXX: RDRT and RADV timers should be here. */
937 cause |= E1000_ICR_RXT0;
940 head = (head + n) % size;
945 pthread_mutex_lock(&sc->esc_mtx);
946 sc->esc_rx_active = 0;
947 if (sc->esc_rx_enabled == 0)
948 pthread_cond_signal(&sc->esc_rx_cond);
951 /* Respect E1000_RCTL_RDMTS */
952 left = (size + sc->esc_RDT - head) % size;
953 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1)))
954 cause |= E1000_ICR_RXDMT0;
955 /* Assert all accumulated interrupts. */
957 e82545_icr_assert(sc, cause);
959 DPRINTF("rx_run done: head %x, tail %x", sc->esc_RDH, sc->esc_RDT);
960 pthread_mutex_unlock(&sc->esc_mtx);
964 e82545_carry(uint32_t sum)
967 sum = (sum & 0xFFFF) + (sum >> 16);
974 e82545_buf_checksum(uint8_t *buf, int len)
979 /* Checksum all the pairs of bytes first... */
980 for (i = 0; i < (len & ~1); i += 2)
981 sum += *((u_int16_t *)(buf + i));
984 * If there's a single byte left over, checksum it, too.
985 * Network byte order is big-endian, so the remaining byte is
989 sum += htons(buf[i] << 8);
991 return (e82545_carry(sum));
995 e82545_iov_checksum(struct iovec *iov, int iovcnt, unsigned int off,
998 unsigned int now, odd;
1001 /* Skip completely unneeded vectors. */
1002 while (iovcnt > 0 && iov->iov_len <= off && off > 0) {
1003 off -= iov->iov_len;
1008 /* Calculate checksum of requested range. */
1010 while (len > 0 && iovcnt > 0) {
1011 now = MIN(len, iov->iov_len - off);
1012 s = e82545_buf_checksum((uint8_t *)iov->iov_base + off, now);
1013 sum += odd ? (s << 8) : s;
1021 return (e82545_carry(sum));
1025 * Return the transmit descriptor type.
1028 e82545_txdesc_type(uint32_t lower)
1034 if (lower & E1000_TXD_CMD_DEXT)
1035 type = lower & E1000_TXD_MASK;
1041 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck)
1046 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d",
1047 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len);
1048 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1U : UINT_MAX;
1049 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen);
1050 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum;
1054 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt)
1057 if (sc->esc_be == NULL)
1060 (void) netbe_send(sc->esc_be, iov, iovcnt);
1064 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail,
1065 uint16_t dsize, int *tdwb)
1067 union e1000_tx_udesc *dsc;
1069 for ( ; head != tail; head = (head + 1) % dsize) {
1070 dsc = &sc->esc_txdesc[head];
1071 if (dsc->td.lower.data & E1000_TXD_CMD_RS) {
1072 dsc->td.upper.data |= E1000_TXD_STAT_DD;
1079 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail,
1080 uint16_t dsize, uint16_t *rhead, int *tdwb)
1082 uint8_t *hdr, *hdrp;
1083 struct iovec iovb[I82545_MAX_TXSEGS + 2];
1084 struct iovec tiov[I82545_MAX_TXSEGS + 2];
1085 struct e1000_context_desc *cd;
1086 struct ck_info ckinfo[2];
1088 union e1000_tx_udesc *dsc;
1089 int desc, dtype, ntype, iovcnt, tcp, tso, paylen, seg, tiovcnt, pv;
1090 unsigned hdrlen, vlen, pktlen, len, left, mss, now, nnow, nleft, pvoff;
1091 uint32_t tcpsum, tcpseq;
1092 uint16_t ipcs, tcpcs, ipid, ohead;
1095 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0;
1103 /* iovb[0/1] may be used for writable copy of headers. */
1106 for (desc = 0; ; desc++, head = (head + 1) % dsize) {
1111 dsc = &sc->esc_txdesc[head];
1112 dtype = e82545_txdesc_type(dsc->td.lower.data);
1116 case E1000_TXD_TYP_C:
1117 DPRINTF("tx ctxt desc idx %d: %016jx "
1119 head, dsc->td.buffer_addr,
1120 dsc->td.upper.data, dsc->td.lower.data);
1121 /* Save context and return */
1122 sc->esc_txctx = dsc->cd;
1124 case E1000_TXD_TYP_L:
1125 DPRINTF("tx legacy desc idx %d: %08x%08x",
1126 head, dsc->td.upper.data, dsc->td.lower.data);
1128 * legacy cksum start valid in first descriptor
1131 ckinfo[0].ck_start = dsc->td.upper.fields.css;
1133 case E1000_TXD_TYP_D:
1134 DPRINTF("tx data desc idx %d: %08x%08x",
1135 head, dsc->td.upper.data, dsc->td.lower.data);
1142 /* Descriptor type must be consistent */
1143 assert(dtype == ntype);
1144 DPRINTF("tx next desc idx %d: %08x%08x",
1145 head, dsc->td.upper.data, dsc->td.lower.data);
1148 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length :
1149 dsc->dd.lower.data & 0xFFFFF;
1151 /* Strip checksum supplied by guest. */
1152 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 &&
1153 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) {
1155 WPRINTF("final descriptor too short (%d) -- dropped",
1162 if (len > 0 && iovcnt < I82545_MAX_TXSEGS) {
1163 iov[iovcnt].iov_base = paddr_guest2host(sc->esc_ctx,
1164 dsc->td.buffer_addr, len);
1165 iov[iovcnt].iov_len = len;
1171 * Pull out info that is valid in the final descriptor
1172 * and exit descriptor loop.
1174 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) {
1175 if (dtype == E1000_TXD_TYP_L) {
1176 if (dsc->td.lower.data & E1000_TXD_CMD_IC) {
1177 ckinfo[0].ck_valid = 1;
1179 dsc->td.lower.flags.cso;
1180 ckinfo[0].ck_len = 0;
1183 cd = &sc->esc_txctx;
1184 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE)
1186 if (dsc->dd.upper.fields.popts &
1187 E1000_TXD_POPTS_IXSM)
1188 ckinfo[0].ck_valid = 1;
1189 if (dsc->dd.upper.fields.popts &
1190 E1000_TXD_POPTS_IXSM || tso) {
1191 ckinfo[0].ck_start =
1192 cd->lower_setup.ip_fields.ipcss;
1194 cd->lower_setup.ip_fields.ipcso;
1196 cd->lower_setup.ip_fields.ipcse;
1198 if (dsc->dd.upper.fields.popts &
1199 E1000_TXD_POPTS_TXSM)
1200 ckinfo[1].ck_valid = 1;
1201 if (dsc->dd.upper.fields.popts &
1202 E1000_TXD_POPTS_TXSM || tso) {
1203 ckinfo[1].ck_start =
1204 cd->upper_setup.tcp_fields.tucss;
1206 cd->upper_setup.tcp_fields.tucso;
1208 cd->upper_setup.tcp_fields.tucse;
1218 if (iovcnt > I82545_MAX_TXSEGS) {
1219 WPRINTF("tx too many descriptors (%d > %d) -- dropped",
1220 iovcnt, I82545_MAX_TXSEGS);
1225 /* Estimate writable space for VLAN header insertion. */
1226 if ((sc->esc_CTRL & E1000_CTRL_VME) &&
1227 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) {
1228 hdrlen = ETHER_ADDR_LEN*2;
1229 vlen = ETHER_VLAN_ENCAP_LEN;
1232 /* Estimate required writable space for checksums. */
1233 if (ckinfo[0].ck_valid)
1234 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2U);
1235 if (ckinfo[1].ck_valid)
1236 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2U);
1237 /* Round up writable space to the first vector. */
1238 if (hdrlen != 0 && iov[0].iov_len > hdrlen &&
1239 iov[0].iov_len < hdrlen + 100)
1240 hdrlen = iov[0].iov_len;
1242 /* In case of TSO header length provided by software. */
1243 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len;
1246 * Cap the header length at 240 based on 7.2.4.5 of
1247 * the Intel 82576EB (Rev 2.63) datasheet.
1250 WPRINTF("TSO hdrlen too large: %d", hdrlen);
1255 * If VLAN insertion is requested, ensure the header
1256 * at least holds the amount of data copied during
1257 * VLAN insertion below.
1259 * XXX: Realistic packets will include a full Ethernet
1260 * header before the IP header at ckinfo[0].ck_start,
1261 * but this check is sufficient to prevent
1262 * out-of-bounds access below.
1264 if (vlen != 0 && hdrlen < ETHER_ADDR_LEN*2) {
1265 WPRINTF("TSO hdrlen too small for vlan insertion "
1266 "(%d vs %d) -- dropped", hdrlen,
1272 * Ensure that the header length covers the used fields
1273 * in the IP and TCP headers as well as the IP and TCP
1274 * checksums. The following fields are accessed below:
1276 * Header | Field | Offset | Length
1277 * -------+-------+--------+-------
1278 * IPv4 | len | 2 | 2
1280 * IPv6 | len | 4 | 2
1281 * TCP | seq # | 4 | 4
1282 * TCP | flags | 13 | 1
1285 if (hdrlen < ckinfo[0].ck_start + 6U ||
1286 hdrlen < ckinfo[0].ck_off + 2U) {
1287 WPRINTF("TSO hdrlen too small for IP fields (%d) "
1288 "-- dropped", hdrlen);
1291 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) {
1292 if (hdrlen < ckinfo[1].ck_start + 14U) {
1293 WPRINTF("TSO hdrlen too small for TCP fields "
1294 "(%d) -- dropped", hdrlen);
1298 if (hdrlen < ckinfo[1].ck_start + 8U) {
1299 WPRINTF("TSO hdrlen too small for UDP fields "
1300 "(%d) -- dropped", hdrlen);
1304 if (ckinfo[1].ck_valid && hdrlen < ckinfo[1].ck_off + 2U) {
1305 WPRINTF("TSO hdrlen too small for TCP/UDP fields "
1306 "(%d) -- dropped", hdrlen);
1311 if (pktlen < hdrlen + vlen) {
1312 WPRINTF("packet too small for writable header");
1316 /* Allocate, fill and prepend writable header vector. */
1317 if (hdrlen + vlen != 0) {
1318 hdr = __builtin_alloca(hdrlen + vlen);
1320 for (left = hdrlen, hdrp = hdr; left > 0;
1321 left -= now, hdrp += now) {
1322 now = MIN(left, iov->iov_len);
1323 memcpy(hdrp, iov->iov_base, now);
1324 iov->iov_base = (uint8_t *)iov->iov_base + now;
1325 iov->iov_len -= now;
1326 if (iov->iov_len == 0) {
1333 iov->iov_base = hdr;
1334 iov->iov_len = hdrlen;
1338 /* Insert VLAN tag. */
1340 hdr -= ETHER_VLAN_ENCAP_LEN;
1341 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2);
1342 hdrlen += ETHER_VLAN_ENCAP_LEN;
1343 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8;
1344 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff;
1345 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8;
1346 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff;
1347 iov->iov_base = hdr;
1348 iov->iov_len += ETHER_VLAN_ENCAP_LEN;
1349 /* Correct checksum offsets after VLAN tag insertion. */
1350 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN;
1351 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN;
1352 if (ckinfo[0].ck_len != 0)
1353 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN;
1354 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN;
1355 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN;
1356 if (ckinfo[1].ck_len != 0)
1357 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN;
1360 /* Simple non-TSO case. */
1362 /* Calculate checksums and transmit. */
1363 if (ckinfo[0].ck_valid)
1364 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]);
1365 if (ckinfo[1].ck_valid)
1366 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]);
1367 e82545_transmit_backend(sc, iov, iovcnt);
1372 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0;
1373 mss = sc->esc_txctx.tcp_seg_setup.fields.mss;
1374 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff);
1375 DPRINTF("tx %s segmentation offload %d+%d/%u bytes %d iovs",
1376 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt);
1377 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]);
1380 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]);
1381 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off];
1383 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */
1384 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off];
1387 for (seg = 0, left = paylen; left > 0; seg++, left -= now) {
1388 now = MIN(left, mss);
1390 /* Construct IOVs for the segment. */
1391 /* Include whole original header. */
1392 tiov[0].iov_base = hdr;
1393 tiov[0].iov_len = hdrlen;
1395 /* Include respective part of payload IOV. */
1396 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) {
1397 nnow = MIN(nleft, iov[pv].iov_len - pvoff);
1398 tiov[tiovcnt].iov_base = (uint8_t *)iov[pv].iov_base +
1400 tiov[tiovcnt++].iov_len = nnow;
1401 if (pvoff + nnow == iov[pv].iov_len) {
1407 DPRINTF("tx segment %d %d+%d bytes %d iovs",
1408 seg, hdrlen, now, tiovcnt);
1410 /* Update IP header. */
1411 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) {
1412 /* IPv4 -- set length and ID */
1413 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] =
1414 htons(hdrlen - ckinfo[0].ck_start + now);
1415 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] =
1418 /* IPv6 -- set length */
1419 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] =
1420 htons(hdrlen - ckinfo[0].ck_start - 40 +
1424 /* Update pseudo-header checksum. */
1426 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now);
1428 /* Update TCP/UDP headers. */
1430 /* Update sequence number and FIN/PUSH flags. */
1431 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] =
1432 htonl(tcpseq + paylen - left);
1434 hdr[ckinfo[1].ck_start + 13] &=
1435 ~(TH_FIN | TH_PUSH);
1438 /* Update payload length. */
1439 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] =
1440 hdrlen - ckinfo[1].ck_start + now;
1443 /* Calculate checksums and transmit. */
1444 if (ckinfo[0].ck_valid) {
1445 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs;
1446 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]);
1448 if (ckinfo[1].ck_valid) {
1449 *(uint16_t *)&hdr[ckinfo[1].ck_off] =
1450 e82545_carry(tcpsum);
1451 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]);
1453 e82545_transmit_backend(sc, tiov, tiovcnt);
1457 head = (head + 1) % dsize;
1458 e82545_transmit_done(sc, ohead, head, dsize, tdwb);
1465 e82545_tx_run(struct e82545_softc *sc)
1468 uint16_t head, rhead, tail, size;
1469 int lim, tdwb, sent;
1471 size = sc->esc_TDLEN / 16;
1475 head = sc->esc_TDH % size;
1476 tail = sc->esc_TDT % size;
1477 DPRINTF("tx_run: head %x, rhead %x, tail %x",
1478 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT);
1480 pthread_mutex_unlock(&sc->esc_mtx);
1483 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) {
1484 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb);
1489 pthread_mutex_lock(&sc->esc_mtx);
1492 sc->esc_TDHr = rhead;
1495 cause |= E1000_ICR_TXDW;
1496 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT)
1497 cause |= E1000_ICR_TXQE;
1499 e82545_icr_assert(sc, cause);
1501 DPRINTF("tx_run done: head %x, rhead %x, tail %x",
1502 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT);
1505 static _Noreturn void *
1506 e82545_tx_thread(void *param)
1508 struct e82545_softc *sc = param;
1510 pthread_mutex_lock(&sc->esc_mtx);
1512 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) {
1513 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT)
1515 sc->esc_tx_active = 0;
1516 if (sc->esc_tx_enabled == 0)
1517 pthread_cond_signal(&sc->esc_tx_cond);
1518 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx);
1520 sc->esc_tx_active = 1;
1522 /* Process some tx descriptors. Lock dropped inside. */
1528 e82545_tx_start(struct e82545_softc *sc)
1531 if (sc->esc_tx_active == 0)
1532 pthread_cond_signal(&sc->esc_tx_cond);
1536 e82545_tx_enable(struct e82545_softc *sc)
1539 sc->esc_tx_enabled = 1;
1543 e82545_tx_disable(struct e82545_softc *sc)
1546 sc->esc_tx_enabled = 0;
1547 while (sc->esc_tx_active)
1548 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx);
1552 e82545_rx_enable(struct e82545_softc *sc)
1555 sc->esc_rx_enabled = 1;
1559 e82545_rx_disable(struct e82545_softc *sc)
1562 sc->esc_rx_enabled = 0;
1563 while (sc->esc_rx_active)
1564 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx);
1568 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
1576 eu = &sc->esc_uni[idx];
1580 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV);
1581 eu->eu_addrsel = (wval >> 16) & 0x3;
1582 eu->eu_eth.octet[5] = wval >> 8;
1583 eu->eu_eth.octet[4] = wval;
1586 eu->eu_eth.octet[3] = wval >> 24;
1587 eu->eu_eth.octet[2] = wval >> 16;
1588 eu->eu_eth.octet[1] = wval >> 8;
1589 eu->eu_eth.octet[0] = wval;
1594 e82545_read_ra(struct e82545_softc *sc, int reg)
1603 eu = &sc->esc_uni[idx];
1607 retval = (eu->eu_valid << 31) |
1608 (eu->eu_addrsel << 16) |
1609 (eu->eu_eth.octet[5] << 8) |
1610 eu->eu_eth.octet[4];
1613 retval = (eu->eu_eth.octet[3] << 24) |
1614 (eu->eu_eth.octet[2] << 16) |
1615 (eu->eu_eth.octet[1] << 8) |
1616 eu->eu_eth.octet[0];
1623 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value)
1628 DPRINTF("Unaligned register write offset:0x%x value:0x%x", offset, value);
1631 DPRINTF("Register write: 0x%x value: 0x%x", offset, value);
1635 case E1000_CTRL_DUP:
1636 e82545_devctl(sc, value);
1639 sc->esc_FCAL = value;
1642 sc->esc_FCAH = value & ~0xFFFF0000;
1645 sc->esc_FCT = value & ~0xFFFF0000;
1648 sc->esc_VET = value & ~0xFFFF0000;
1651 sc->esc_FCTTV = value & ~0xFFFF0000;
1654 sc->esc_LEDCTL = value & ~0x30303000;
1657 sc->esc_PBA = value & 0x0000FF80;
1664 e82545_intr_write(sc, offset, value);
1667 e82545_rx_ctl(sc, value);
1670 sc->esc_FCRTL = value & ~0xFFFF0007;
1673 sc->esc_FCRTH = value & ~0xFFFF0007;
1675 case E1000_RDBAL(0):
1676 sc->esc_RDBAL = value & ~0xF;
1677 if (sc->esc_rx_enabled) {
1678 /* Apparently legal: update cached address */
1679 e82545_rx_update_rdba(sc);
1682 case E1000_RDBAH(0):
1683 assert(!sc->esc_rx_enabled);
1684 sc->esc_RDBAH = value;
1686 case E1000_RDLEN(0):
1687 assert(!sc->esc_rx_enabled);
1688 sc->esc_RDLEN = value & ~0xFFF0007F;
1691 /* XXX should only ever be zero ? Range check ? */
1692 sc->esc_RDH = value;
1695 /* XXX if this opens up the rx ring, do something ? */
1696 sc->esc_RDT = value;
1699 /* ignore FPD bit 31 */
1700 sc->esc_RDTR = value & ~0xFFFF0000;
1702 case E1000_RXDCTL(0):
1703 sc->esc_RXDCTL = value & ~0xFEC0C0C0;
1706 sc->esc_RADV = value & ~0xFFFF0000;
1709 sc->esc_RSRPD = value & ~0xFFFFF000;
1712 sc->esc_RXCSUM = value & ~0xFFFFF800;
1715 sc->esc_TXCW = value & ~0x3FFF0000;
1718 e82545_tx_ctl(sc, value);
1721 sc->esc_TIPG = value;
1724 sc->esc_AIT = value;
1726 case E1000_TDBAL(0):
1727 sc->esc_TDBAL = value & ~0xF;
1728 if (sc->esc_tx_enabled)
1729 e82545_tx_update_tdba(sc);
1731 case E1000_TDBAH(0):
1732 sc->esc_TDBAH = value;
1733 if (sc->esc_tx_enabled)
1734 e82545_tx_update_tdba(sc);
1736 case E1000_TDLEN(0):
1737 sc->esc_TDLEN = value & ~0xFFF0007F;
1738 if (sc->esc_tx_enabled)
1739 e82545_tx_update_tdba(sc);
1742 if (sc->esc_tx_enabled) {
1743 WPRINTF("ignoring write to TDH while transmit enabled");
1747 WPRINTF("ignoring non-zero value written to TDH");
1750 sc->esc_TDHr = sc->esc_TDH = value;
1753 sc->esc_TDT = value;
1754 if (sc->esc_tx_enabled)
1755 e82545_tx_start(sc);
1758 sc->esc_TIDV = value & ~0xFFFF0000;
1760 case E1000_TXDCTL(0):
1761 //assert(!sc->esc_tx_enabled);
1762 sc->esc_TXDCTL = value & ~0xC0C0C0;
1765 sc->esc_TADV = value & ~0xFFFF0000;
1767 case E1000_RAL(0) ... E1000_RAH(15):
1768 /* convert to u32 offset */
1769 ridx = (offset - E1000_RAL(0)) >> 2;
1770 e82545_write_ra(sc, ridx, value);
1772 case E1000_MTA ... (E1000_MTA + (127*4)):
1773 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value;
1775 case E1000_VFTA ... (E1000_VFTA + (127*4)):
1776 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value;
1780 //DPRINTF("EECD write 0x%x -> 0x%x", sc->eeprom_control, value);
1781 /* edge triggered low->high */
1782 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ?
1783 0 : (value & E1000_EECD_SK));
1784 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS|
1785 E1000_EECD_DI|E1000_EECD_REQ);
1786 sc->eeprom_control &= ~eecd_mask;
1787 sc->eeprom_control |= (value & eecd_mask);
1788 /* grant/revoke immediately */
1789 if (value & E1000_EECD_REQ) {
1790 sc->eeprom_control |= E1000_EECD_GNT;
1792 sc->eeprom_control &= ~E1000_EECD_GNT;
1794 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) {
1795 e82545_eecd_strobe(sc);
1801 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >>
1802 E1000_MDIC_REG_SHIFT);
1803 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >>
1804 E1000_MDIC_PHY_SHIFT);
1806 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST));
1807 if ((value & E1000_MDIC_READY) != 0) {
1808 DPRINTF("Incorrect MDIC ready bit: 0x%x", value);
1811 switch (value & E82545_MDIC_OP_MASK) {
1812 case E1000_MDIC_OP_READ:
1813 sc->mdi_control &= ~E82545_MDIC_DATA_MASK;
1814 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr);
1816 case E1000_MDIC_OP_WRITE:
1817 e82545_write_mdi(sc, reg_addr, phy_addr,
1818 value & E82545_MDIC_DATA_MASK);
1821 DPRINTF("Unknown MDIC op: 0x%x", value);
1824 /* TODO: barrier? */
1825 sc->mdi_control |= E1000_MDIC_READY;
1826 if (value & E82545_MDIC_IE) {
1827 // TODO: generate interrupt
1835 DPRINTF("Unknown write register: 0x%x value:%x", offset, value);
1841 e82545_read_register(struct e82545_softc *sc, uint32_t offset)
1847 DPRINTF("Unaligned register read offset:0x%x", offset);
1851 DPRINTF("Register read: 0x%x", offset);
1855 retval = sc->esc_CTRL;
1858 retval = E1000_STATUS_FD | E1000_STATUS_LU |
1859 E1000_STATUS_SPEED_1000;
1862 retval = sc->esc_FCAL;
1865 retval = sc->esc_FCAH;
1868 retval = sc->esc_FCT;
1871 retval = sc->esc_VET;
1874 retval = sc->esc_FCTTV;
1877 retval = sc->esc_LEDCTL;
1880 retval = sc->esc_PBA;
1887 retval = e82545_intr_read(sc, offset);
1890 retval = sc->esc_RCTL;
1893 retval = sc->esc_FCRTL;
1896 retval = sc->esc_FCRTH;
1898 case E1000_RDBAL(0):
1899 retval = sc->esc_RDBAL;
1901 case E1000_RDBAH(0):
1902 retval = sc->esc_RDBAH;
1904 case E1000_RDLEN(0):
1905 retval = sc->esc_RDLEN;
1908 retval = sc->esc_RDH;
1911 retval = sc->esc_RDT;
1914 retval = sc->esc_RDTR;
1916 case E1000_RXDCTL(0):
1917 retval = sc->esc_RXDCTL;
1920 retval = sc->esc_RADV;
1923 retval = sc->esc_RSRPD;
1926 retval = sc->esc_RXCSUM;
1929 retval = sc->esc_TXCW;
1932 retval = sc->esc_TCTL;
1935 retval = sc->esc_TIPG;
1938 retval = sc->esc_AIT;
1940 case E1000_TDBAL(0):
1941 retval = sc->esc_TDBAL;
1943 case E1000_TDBAH(0):
1944 retval = sc->esc_TDBAH;
1946 case E1000_TDLEN(0):
1947 retval = sc->esc_TDLEN;
1950 retval = sc->esc_TDH;
1953 retval = sc->esc_TDT;
1956 retval = sc->esc_TIDV;
1958 case E1000_TXDCTL(0):
1959 retval = sc->esc_TXDCTL;
1962 retval = sc->esc_TADV;
1964 case E1000_RAL(0) ... E1000_RAH(15):
1965 /* convert to u32 offset */
1966 ridx = (offset - E1000_RAL(0)) >> 2;
1967 retval = e82545_read_ra(sc, ridx);
1969 case E1000_MTA ... (E1000_MTA + (127*4)):
1970 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2];
1972 case E1000_VFTA ... (E1000_VFTA + (127*4)):
1973 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2];
1976 //DPRINTF("EECD read %x", sc->eeprom_control);
1977 retval = sc->eeprom_control;
1980 retval = sc->mdi_control;
1985 /* stats that we emulate. */
1987 retval = sc->missed_pkt_count;
1990 retval = sc->pkt_rx_by_size[0];
1993 retval = sc->pkt_rx_by_size[1];
1996 retval = sc->pkt_rx_by_size[2];
1999 retval = sc->pkt_rx_by_size[3];
2002 retval = sc->pkt_rx_by_size[4];
2005 retval = sc->pkt_rx_by_size[5];
2008 retval = sc->good_pkt_rx_count;
2011 retval = sc->bcast_pkt_rx_count;
2014 retval = sc->mcast_pkt_rx_count;
2018 retval = sc->good_pkt_tx_count;
2021 retval = (uint32_t)sc->good_octets_rx;
2024 retval = (uint32_t)(sc->good_octets_rx >> 32);
2028 retval = (uint32_t)sc->good_octets_tx;
2032 retval = (uint32_t)(sc->good_octets_tx >> 32);
2035 retval = sc->oversize_rx_count;
2038 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets);
2041 retval = (uint32_t)((sc->good_octets_rx +
2042 sc->missed_octets) >> 32);
2045 retval = sc->good_pkt_rx_count + sc->missed_pkt_count +
2046 sc->oversize_rx_count;
2049 retval = sc->pkt_tx_by_size[0];
2052 retval = sc->pkt_tx_by_size[1];
2055 retval = sc->pkt_tx_by_size[2];
2058 retval = sc->pkt_tx_by_size[3];
2061 retval = sc->pkt_tx_by_size[4];
2064 retval = sc->pkt_tx_by_size[5];
2067 retval = sc->mcast_pkt_tx_count;
2070 retval = sc->bcast_pkt_tx_count;
2073 retval = sc->tso_tx_count;
2075 /* stats that are always 0. */
2077 case E1000_ALGNERRC:
2106 DPRINTF("Unknown read register: 0x%x", offset);
2115 e82545_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2118 struct e82545_softc *sc;
2120 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d", baridx, offset, value, size);
2124 pthread_mutex_lock(&sc->esc_mtx);
2131 DPRINTF("Wrong io addr write sz:%d value:0x%lx", size, value);
2133 sc->io_addr = (uint32_t)value;
2137 DPRINTF("Wrong io data write size:%d value:0x%lx", size, value);
2138 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) {
2139 DPRINTF("Non-register io write addr:0x%x value:0x%lx", sc->io_addr, value);
2141 e82545_write_register(sc, sc->io_addr,
2145 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d", offset, value, size);
2149 case E82545_BAR_REGISTER:
2151 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx", size, offset, value);
2153 e82545_write_register(sc, (uint32_t)offset,
2157 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d",
2158 baridx, offset, value, size);
2161 pthread_mutex_unlock(&sc->esc_mtx);
2165 e82545_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
2167 struct e82545_softc *sc;
2170 //DPRINTF("Read bar:%d offset:0x%lx size:%d", baridx, offset, size);
2174 pthread_mutex_lock(&sc->esc_mtx);
2181 DPRINTF("Wrong io addr read sz:%d", size);
2183 retval = sc->io_addr;
2187 DPRINTF("Wrong io data read sz:%d", size);
2189 if (sc->io_addr > E82545_IO_REGISTER_MAX) {
2190 DPRINTF("Non-register io read addr:0x%x",
2193 retval = e82545_read_register(sc, sc->io_addr);
2196 DPRINTF("Unknown io bar read offset:0x%lx size:%d",
2201 case E82545_BAR_REGISTER:
2203 DPRINTF("Wrong register read size:%d offset:0x%lx",
2206 retval = e82545_read_register(sc, (uint32_t)offset);
2209 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d",
2210 baridx, offset, size);
2214 pthread_mutex_unlock(&sc->esc_mtx);
2220 e82545_reset(struct e82545_softc *sc, int drvr)
2224 e82545_rx_disable(sc);
2225 e82545_tx_disable(sc);
2227 /* clear outstanding interrupts */
2228 if (sc->esc_irq_asserted)
2229 pci_lintr_deassert(sc->esc_pi);
2239 sc->esc_LEDCTL = 0x07061302;
2240 sc->esc_PBA = 0x00100030;
2242 /* start nvm in opcode mode. */
2244 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
2245 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
2246 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN;
2247 e82545_init_eeprom(sc);
2258 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan));
2259 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast));
2260 memset(sc->esc_uni, 0, sizeof(sc->esc_uni));
2262 /* XXX not necessary on 82545 ?? */
2263 sc->esc_uni[0].eu_valid = 1;
2264 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet,
2267 /* Clear RAH valid bits */
2268 for (i = 0; i < 16; i++)
2269 sc->esc_uni[i].eu_valid = 0;
2284 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */
2298 sc->esc_txdesc = NULL;
2303 sc->esc_TDHr = sc->esc_TDH = 0;
2308 e82545_init(struct pci_devinst *pi, nvlist_t *nvl)
2311 struct e82545_softc *sc;
2315 /* Setup our softc */
2316 sc = calloc(1, sizeof(*sc));
2320 sc->esc_ctx = pi->pi_vmctx;
2322 pthread_mutex_init(&sc->esc_mtx, NULL);
2323 pthread_cond_init(&sc->esc_rx_cond, NULL);
2324 pthread_cond_init(&sc->esc_tx_cond, NULL);
2325 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc);
2326 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot,
2328 pthread_set_name_np(sc->esc_tx_tid, nstr);
2330 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER);
2331 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL);
2332 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK);
2333 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET);
2334 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID);
2335 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL);
2337 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL);
2338 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1);
2340 /* TODO: this card also supports msi, but the freebsd driver for it
2341 * does not, so I have not implemented it. */
2342 pci_lintr_request(pi);
2344 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32,
2345 E82545_BAR_REGISTER_LEN);
2346 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32,
2347 E82545_BAR_FLASH_LEN);
2348 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO,
2351 mac = get_config_value_node(nvl, "mac");
2353 err = net_parsemac(mac, sc->esc_mac.octet);
2359 net_genmac(pi, sc->esc_mac.octet);
2361 err = netbe_init(&sc->esc_be, nvl, e82545_rx_callback, sc);
2367 netbe_rx_enable(sc->esc_be);
2369 /* H/w initiated reset */
2370 e82545_reset(sc, 0);
2375 #ifdef BHYVE_SNAPSHOT
2377 e82545_snapshot(struct vm_snapshot_meta *meta)
2381 struct e82545_softc *sc;
2382 struct pci_devinst *pi;
2383 uint64_t bitmap_value;
2385 pi = meta->dev_data;
2388 /* esc_mevp and esc_mevpitr should be reinitiated at init. */
2389 SNAPSHOT_VAR_OR_LEAVE(sc->esc_mac, meta, ret, done);
2392 SNAPSHOT_VAR_OR_LEAVE(sc->esc_CTRL, meta, ret, done);
2393 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCAL, meta, ret, done);
2394 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCAH, meta, ret, done);
2395 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCT, meta, ret, done);
2396 SNAPSHOT_VAR_OR_LEAVE(sc->esc_VET, meta, ret, done);
2397 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCTTV, meta, ret, done);
2398 SNAPSHOT_VAR_OR_LEAVE(sc->esc_LEDCTL, meta, ret, done);
2399 SNAPSHOT_VAR_OR_LEAVE(sc->esc_PBA, meta, ret, done);
2401 /* Interrupt control */
2402 SNAPSHOT_VAR_OR_LEAVE(sc->esc_irq_asserted, meta, ret, done);
2403 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ICR, meta, ret, done);
2404 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ITR, meta, ret, done);
2405 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ICS, meta, ret, done);
2406 SNAPSHOT_VAR_OR_LEAVE(sc->esc_IMS, meta, ret, done);
2407 SNAPSHOT_VAR_OR_LEAVE(sc->esc_IMC, meta, ret, done);
2412 * The fields in the unions are in superposition to access certain
2413 * bytes in the larger uint variables.
2414 * e.g., ip_config = [ipcss|ipcso|ipcse0|ipcse1]
2416 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.lower_setup.ip_config, meta, ret, done);
2417 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.upper_setup.tcp_config, meta, ret, done);
2418 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.cmd_and_length, meta, ret, done);
2419 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.tcp_seg_setup.data, meta, ret, done);
2421 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tx_enabled, meta, ret, done);
2422 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tx_active, meta, ret, done);
2423 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TXCW, meta, ret, done);
2424 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TCTL, meta, ret, done);
2425 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TIPG, meta, ret, done);
2426 SNAPSHOT_VAR_OR_LEAVE(sc->esc_AIT, meta, ret, done);
2427 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tdba, meta, ret, done);
2428 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDBAL, meta, ret, done);
2429 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDBAH, meta, ret, done);
2430 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDLEN, meta, ret, done);
2431 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDH, meta, ret, done);
2432 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDHr, meta, ret, done);
2433 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDT, meta, ret, done);
2434 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TIDV, meta, ret, done);
2435 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TXDCTL, meta, ret, done);
2436 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TADV, meta, ret, done);
2438 /* Has dependency on esc_TDLEN; reoreder of fields from struct. */
2439 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->esc_txdesc, sc->esc_TDLEN,
2440 true, meta, ret, done);
2442 /* L2 frame acceptance */
2443 for (i = 0; i < (int)nitems(sc->esc_uni); i++) {
2444 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_valid, meta, ret, done);
2445 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_addrsel, meta, ret, done);
2446 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_eth, meta, ret, done);
2449 SNAPSHOT_BUF_OR_LEAVE(sc->esc_fmcast, sizeof(sc->esc_fmcast),
2451 SNAPSHOT_BUF_OR_LEAVE(sc->esc_fvlan, sizeof(sc->esc_fvlan),
2455 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_enabled, meta, ret, done);
2456 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_active, meta, ret, done);
2457 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_loopback, meta, ret, done);
2458 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RCTL, meta, ret, done);
2459 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCRTL, meta, ret, done);
2460 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCRTH, meta, ret, done);
2461 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rdba, meta, ret, done);
2462 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDBAL, meta, ret, done);
2463 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDBAH, meta, ret, done);
2464 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDLEN, meta, ret, done);
2465 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDH, meta, ret, done);
2466 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDT, meta, ret, done);
2467 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDTR, meta, ret, done);
2468 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RXDCTL, meta, ret, done);
2469 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RADV, meta, ret, done);
2470 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RSRPD, meta, ret, done);
2471 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RXCSUM, meta, ret, done);
2473 /* Has dependency on esc_RDLEN; reoreder of fields from struct. */
2474 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->esc_rxdesc, sc->esc_TDLEN,
2475 true, meta, ret, done);
2477 /* IO Port register access */
2478 SNAPSHOT_VAR_OR_LEAVE(sc->io_addr, meta, ret, done);
2480 /* Shadow copy of MDIC */
2481 SNAPSHOT_VAR_OR_LEAVE(sc->mdi_control, meta, ret, done);
2483 /* Shadow copy of EECD */
2484 SNAPSHOT_VAR_OR_LEAVE(sc->eeprom_control, meta, ret, done);
2486 /* Latest NVM in/out */
2487 SNAPSHOT_VAR_OR_LEAVE(sc->nvm_data, meta, ret, done);
2488 SNAPSHOT_VAR_OR_LEAVE(sc->nvm_opaddr, meta, ret, done);
2491 SNAPSHOT_VAR_OR_LEAVE(sc->missed_pkt_count, meta, ret, done);
2492 SNAPSHOT_BUF_OR_LEAVE(sc->pkt_rx_by_size, sizeof(sc->pkt_rx_by_size),
2494 SNAPSHOT_BUF_OR_LEAVE(sc->pkt_tx_by_size, sizeof(sc->pkt_tx_by_size),
2496 SNAPSHOT_VAR_OR_LEAVE(sc->good_pkt_rx_count, meta, ret, done);
2497 SNAPSHOT_VAR_OR_LEAVE(sc->bcast_pkt_rx_count, meta, ret, done);
2498 SNAPSHOT_VAR_OR_LEAVE(sc->mcast_pkt_rx_count, meta, ret, done);
2499 SNAPSHOT_VAR_OR_LEAVE(sc->good_pkt_tx_count, meta, ret, done);
2500 SNAPSHOT_VAR_OR_LEAVE(sc->bcast_pkt_tx_count, meta, ret, done);
2501 SNAPSHOT_VAR_OR_LEAVE(sc->mcast_pkt_tx_count, meta, ret, done);
2502 SNAPSHOT_VAR_OR_LEAVE(sc->oversize_rx_count, meta, ret, done);
2503 SNAPSHOT_VAR_OR_LEAVE(sc->tso_tx_count, meta, ret, done);
2504 SNAPSHOT_VAR_OR_LEAVE(sc->good_octets_rx, meta, ret, done);
2505 SNAPSHOT_VAR_OR_LEAVE(sc->good_octets_tx, meta, ret, done);
2506 SNAPSHOT_VAR_OR_LEAVE(sc->missed_octets, meta, ret, done);
2508 if (meta->op == VM_SNAPSHOT_SAVE)
2509 bitmap_value = sc->nvm_bits;
2510 SNAPSHOT_VAR_OR_LEAVE(bitmap_value, meta, ret, done);
2511 if (meta->op == VM_SNAPSHOT_RESTORE)
2512 sc->nvm_bits = bitmap_value;
2514 if (meta->op == VM_SNAPSHOT_SAVE)
2515 bitmap_value = sc->nvm_bits;
2516 SNAPSHOT_VAR_OR_LEAVE(bitmap_value, meta, ret, done);
2517 if (meta->op == VM_SNAPSHOT_RESTORE)
2518 sc->nvm_bits = bitmap_value;
2521 SNAPSHOT_BUF_OR_LEAVE(sc->eeprom_data, sizeof(sc->eeprom_data),
2529 static const struct pci_devemu pci_de_e82545 = {
2531 .pe_init = e82545_init,
2532 .pe_legacy_config = netbe_legacy_config,
2533 .pe_barwrite = e82545_write,
2534 .pe_barread = e82545_read,
2535 #ifdef BHYVE_SNAPSHOT
2536 .pe_snapshot = e82545_snapshot,
2539 PCI_EMUL_SET(pci_de_e82545);