2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/linker_set.h>
47 #include <machine/vmm.h>
60 #define CONF1_ADDR_PORT 0x0cf8
61 #define CONF1_DATA_PORT 0x0cfc
63 #define CONF1_ENABLE 0x80000000ul
65 #define MAXBUSES (PCI_BUSMAX + 1)
66 #define MAXSLOTS (PCI_SLOTMAX + 1)
67 #define MAXFUNCS (PCI_FUNCMAX + 1)
72 struct pci_devinst *fi_devi;
82 struct intxinfo si_intpins[4];
83 struct funcinfo si_funcs[MAXFUNCS];
87 uint16_t iobase, iolimit; /* I/O window */
88 uint32_t membase32, memlimit32; /* mmio window below 4GB */
89 uint64_t membase64, memlimit64; /* mmio window above 4GB */
90 struct slotinfo slotinfo[MAXSLOTS];
93 static struct businfo *pci_businfo[MAXBUSES];
95 SET_DECLARE(pci_devemu_set, struct pci_devemu);
97 static uint64_t pci_emul_iobase;
98 static uint64_t pci_emul_membase32;
99 static uint64_t pci_emul_membase64;
101 #define PCI_EMUL_IOBASE 0x2000
102 #define PCI_EMUL_IOLIMIT 0x10000
104 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
105 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
106 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
108 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
110 #define PCI_EMUL_MEMBASE64 0xD000000000UL
111 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
113 static struct pci_devemu *pci_emul_finddev(char *name);
114 static void pci_lintr_route(struct pci_devinst *pi);
115 static void pci_lintr_update(struct pci_devinst *pi);
116 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
117 int func, int coff, int bytes, uint32_t *val);
120 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
124 pci_set_cfgdata8(pi, coff, val);
126 pci_set_cfgdata16(pi, coff, val);
128 pci_set_cfgdata32(pi, coff, val);
131 static __inline uint32_t
132 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
136 return (pci_get_cfgdata8(pi, coff));
138 return (pci_get_cfgdata16(pi, coff));
140 return (pci_get_cfgdata32(pi, coff));
148 * Slot options are in the form:
150 * <bus>:<slot>:<func>,<emul>[,<config>]
151 * <slot>[:<func>],<emul>[,<config>]
155 * emul is a string describing the type of PCI device e.g. virtio-net
156 * config is an optional string, depending on the device, that can be
157 * used for configuration.
163 pci_parse_slot_usage(char *aopt)
166 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt);
170 pci_parse_slot(char *opt)
174 char *emul, *config, *str, *cp;
175 int error, bnum, snum, fnum;
180 emul = config = NULL;
181 if ((cp = strchr(str, ',')) != NULL) {
184 if ((cp = strchr(emul, ',')) != NULL) {
189 pci_parse_slot_usage(opt);
193 /* <bus>:<slot>:<func> */
194 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
197 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
200 if (sscanf(str, "%d", &snum) != 1) {
206 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
207 fnum < 0 || fnum >= MAXFUNCS) {
208 pci_parse_slot_usage(opt);
212 if (pci_businfo[bnum] == NULL)
213 pci_businfo[bnum] = calloc(1, sizeof(struct businfo));
215 bi = pci_businfo[bnum];
216 si = &bi->slotinfo[snum];
218 if (si->si_funcs[fnum].fi_name != NULL) {
219 EPRINTLN("pci slot %d:%d already occupied!",
224 if (pci_emul_finddev(emul) == NULL) {
225 EPRINTLN("pci slot %d:%d: unknown device \"%s\"",
231 si->si_funcs[fnum].fi_name = emul;
232 si->si_funcs[fnum].fi_param = config;
242 pci_print_supported_devices()
244 struct pci_devemu **pdpp, *pdp;
246 SET_FOREACH(pdpp, pci_devemu_set) {
248 printf("%s\n", pdp->pe_emu);
253 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
256 if (offset < pi->pi_msix.pba_offset)
259 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
267 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
270 int msix_entry_offset;
274 /* support only 4 or 8 byte writes */
275 if (size != 4 && size != 8)
279 * Return if table index is beyond what device supports
281 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
282 if (tab_index >= pi->pi_msix.table_count)
285 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
287 /* support only aligned writes */
288 if ((msix_entry_offset % size) != 0)
291 dest = (char *)(pi->pi_msix.table + tab_index);
292 dest += msix_entry_offset;
295 *((uint32_t *)dest) = value;
297 *((uint64_t *)dest) = value;
303 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
306 int msix_entry_offset;
308 uint64_t retval = ~0;
311 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
312 * table but we also allow 1 byte access to accommodate reads from
315 if (size != 1 && size != 4 && size != 8)
318 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
320 /* support only aligned reads */
321 if ((msix_entry_offset % size) != 0) {
325 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
327 if (tab_index < pi->pi_msix.table_count) {
328 /* valid MSI-X Table access */
329 dest = (char *)(pi->pi_msix.table + tab_index);
330 dest += msix_entry_offset;
333 retval = *((uint8_t *)dest);
335 retval = *((uint32_t *)dest);
337 retval = *((uint64_t *)dest);
338 } else if (pci_valid_pba_offset(pi, offset)) {
339 /* return 0 for PBA access */
347 pci_msix_table_bar(struct pci_devinst *pi)
350 if (pi->pi_msix.table != NULL)
351 return (pi->pi_msix.table_bar);
357 pci_msix_pba_bar(struct pci_devinst *pi)
360 if (pi->pi_msix.table != NULL)
361 return (pi->pi_msix.pba_bar);
367 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
368 uint32_t *eax, void *arg)
370 struct pci_devinst *pdi = arg;
371 struct pci_devemu *pe = pdi->pi_d;
375 for (i = 0; i <= PCI_BARMAX; i++) {
376 if (pdi->pi_bar[i].type == PCIBAR_IO &&
377 port >= pdi->pi_bar[i].addr &&
378 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
379 offset = port - pdi->pi_bar[i].addr;
381 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
384 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
393 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
394 int size, uint64_t *val, void *arg1, long arg2)
396 struct pci_devinst *pdi = arg1;
397 struct pci_devemu *pe = pdi->pi_d;
399 int bidx = (int) arg2;
401 assert(bidx <= PCI_BARMAX);
402 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
403 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
404 assert(addr >= pdi->pi_bar[bidx].addr &&
405 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
407 offset = addr - pdi->pi_bar[bidx].addr;
409 if (dir == MEM_F_WRITE) {
411 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
412 4, *val & 0xffffffff);
413 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
416 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
421 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
423 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
424 offset + 4, 4) << 32;
426 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
436 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
441 assert((size & (size - 1)) == 0); /* must be a power of 2 */
443 base = roundup2(*baseptr, size);
445 if (base + size <= limit) {
447 *baseptr = base + size;
454 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
458 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size));
462 * Register (or unregister) the MMIO or I/O region associated with the BAR
463 * register 'idx' of an emulated pci device.
466 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
469 struct inout_port iop;
472 switch (pi->pi_bar[idx].type) {
474 bzero(&iop, sizeof(struct inout_port));
475 iop.name = pi->pi_name;
476 iop.port = pi->pi_bar[idx].addr;
477 iop.size = pi->pi_bar[idx].size;
479 iop.flags = IOPORT_F_INOUT;
480 iop.handler = pci_emul_io_handler;
482 error = register_inout(&iop);
484 error = unregister_inout(&iop);
488 bzero(&mr, sizeof(struct mem_range));
489 mr.name = pi->pi_name;
490 mr.base = pi->pi_bar[idx].addr;
491 mr.size = pi->pi_bar[idx].size;
494 mr.handler = pci_emul_mem_handler;
497 error = register_mem(&mr);
499 error = unregister_mem(&mr);
509 unregister_bar(struct pci_devinst *pi, int idx)
512 modify_bar_registration(pi, idx, 0);
516 register_bar(struct pci_devinst *pi, int idx)
519 modify_bar_registration(pi, idx, 1);
522 /* Are we decoding i/o port accesses for the emulated pci device? */
524 porten(struct pci_devinst *pi)
528 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
530 return (cmd & PCIM_CMD_PORTEN);
533 /* Are we decoding memory accesses for the emulated pci device? */
535 memen(struct pci_devinst *pi)
539 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
541 return (cmd & PCIM_CMD_MEMEN);
545 * Update the MMIO or I/O address that is decoded by the BAR register.
547 * If the pci device has enabled the address space decoding then intercept
548 * the address range decoded by the BAR register.
551 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
555 if (pi->pi_bar[idx].type == PCIBAR_IO)
561 unregister_bar(pi, idx);
566 pi->pi_bar[idx].addr = addr;
569 pi->pi_bar[idx].addr &= ~0xffffffffUL;
570 pi->pi_bar[idx].addr |= addr;
573 pi->pi_bar[idx].addr &= 0xffffffff;
574 pi->pi_bar[idx].addr |= addr;
581 register_bar(pi, idx);
585 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
586 enum pcibar_type type, uint64_t size)
589 uint64_t *baseptr, limit, addr, mask, lobits, bar;
592 assert(idx >= 0 && idx <= PCI_BARMAX);
594 if ((size & (size - 1)) != 0)
595 size = 1UL << flsl(size); /* round up to a power of 2 */
597 /* Enforce minimum BAR sizes required by the PCI standard */
598 if (type == PCIBAR_IO) {
609 addr = mask = lobits = enbit = 0;
612 baseptr = &pci_emul_iobase;
613 limit = PCI_EMUL_IOLIMIT;
614 mask = PCIM_BAR_IO_BASE;
615 lobits = PCIM_BAR_IO_SPACE;
616 enbit = PCIM_CMD_PORTEN;
621 * Some drivers do not work well if the 64-bit BAR is allocated
622 * above 4GB. Allow for this by allocating small requests under
623 * 4GB unless then allocation size is larger than some arbitrary
624 * number (32MB currently).
626 if (size > 32 * 1024 * 1024) {
628 * XXX special case for device requiring peer-peer DMA
630 if (size == 0x100000000UL)
633 baseptr = &pci_emul_membase64;
634 limit = PCI_EMUL_MEMLIMIT64;
635 mask = PCIM_BAR_MEM_BASE;
636 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
637 PCIM_BAR_MEM_PREFETCH;
639 baseptr = &pci_emul_membase32;
640 limit = PCI_EMUL_MEMLIMIT32;
641 mask = PCIM_BAR_MEM_BASE;
642 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
644 enbit = PCIM_CMD_MEMEN;
647 baseptr = &pci_emul_membase32;
648 limit = PCI_EMUL_MEMLIMIT32;
649 mask = PCIM_BAR_MEM_BASE;
650 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
651 enbit = PCIM_CMD_MEMEN;
654 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
658 if (baseptr != NULL) {
659 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
664 pdi->pi_bar[idx].type = type;
665 pdi->pi_bar[idx].addr = addr;
666 pdi->pi_bar[idx].size = size;
668 /* Initialize the BAR register in config space */
669 bar = (addr & mask) | lobits;
670 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
672 if (type == PCIBAR_MEM64) {
673 assert(idx + 1 <= PCI_BARMAX);
674 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
675 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
678 cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND);
679 if ((cmd & enbit) != enbit)
680 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit);
681 register_bar(pdi, idx);
686 #define CAP_START_OFFSET 0x40
688 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
690 int i, capoff, reallen;
695 reallen = roundup2(caplen, 4); /* dword aligned */
697 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
698 if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
699 capoff = CAP_START_OFFSET;
701 capoff = pi->pi_capend + 1;
703 /* Check if we have enough space */
704 if (capoff + reallen > PCI_REGMAX + 1)
707 /* Set the previous capability pointer */
708 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
709 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
710 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
712 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
714 /* Copy the capability */
715 for (i = 0; i < caplen; i++)
716 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
718 /* Set the next capability pointer */
719 pci_set_cfgdata8(pi, capoff + 1, 0);
721 pi->pi_prevcap = capoff;
722 pi->pi_capend = capoff + reallen - 1;
726 static struct pci_devemu *
727 pci_emul_finddev(char *name)
729 struct pci_devemu **pdpp, *pdp;
731 SET_FOREACH(pdpp, pci_devemu_set) {
733 if (!strcmp(pdp->pe_emu, name)) {
742 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
743 int func, struct funcinfo *fi)
745 struct pci_devinst *pdi;
748 pdi = calloc(1, sizeof(struct pci_devinst));
754 pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
755 pdi->pi_lintr.pin = 0;
756 pdi->pi_lintr.state = IDLE;
757 pdi->pi_lintr.pirq_pin = 0;
758 pdi->pi_lintr.ioapic_irq = 0;
760 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
762 /* Disable legacy interrupts */
763 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
764 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
766 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN);
768 err = (*pde->pe_init)(ctx, pdi, fi->fi_param);
778 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
782 /* Number of msi messages must be a power of 2 between 1 and 32 */
783 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
784 mmc = ffs(msgnum) - 1;
786 bzero(msicap, sizeof(struct msicap));
787 msicap->capid = PCIY_MSI;
788 msicap->nextptr = nextptr;
789 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
793 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
795 struct msicap msicap;
797 pci_populate_msicap(&msicap, msgnum, 0);
799 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
803 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
804 uint32_t msix_tab_size)
807 assert(msix_tab_size % 4096 == 0);
809 bzero(msixcap, sizeof(struct msixcap));
810 msixcap->capid = PCIY_MSIX;
813 * Message Control Register, all fields set to
814 * zero except for the Table Size.
815 * Note: Table size N is encoded as N-1
817 msixcap->msgctrl = msgnum - 1;
821 * - MSI-X table start at offset 0
822 * - PBA table starts at a 4K aligned offset after the MSI-X table
824 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
825 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
829 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
833 assert(table_entries > 0);
834 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
836 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
837 pi->pi_msix.table = calloc(1, table_size);
839 /* set mask bit of vector control register */
840 for (i = 0; i < table_entries; i++)
841 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
845 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
848 struct msixcap msixcap;
850 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
851 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
853 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
855 /* Align table size to nearest 4K */
856 tab_size = roundup2(tab_size, 4096);
858 pi->pi_msix.table_bar = barnum;
859 pi->pi_msix.pba_bar = barnum;
860 pi->pi_msix.table_offset = 0;
861 pi->pi_msix.table_count = msgnum;
862 pi->pi_msix.pba_offset = tab_size;
863 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
865 pci_msix_table_init(pi, msgnum);
867 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
869 /* allocate memory for MSI-X Table and PBA */
870 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
871 tab_size + pi->pi_msix.pba_size);
873 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
878 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
879 int bytes, uint32_t val)
881 uint16_t msgctrl, rwmask;
884 off = offset - capoff;
885 /* Message Control Register */
886 if (off == 2 && bytes == 2) {
887 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
888 msgctrl = pci_get_cfgdata16(pi, offset);
890 msgctrl |= val & rwmask;
893 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
894 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
895 pci_lintr_update(pi);
898 CFGWRITE(pi, offset, val, bytes);
902 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
903 int bytes, uint32_t val)
905 uint16_t msgctrl, rwmask, msgdata, mme;
909 * If guest is writing to the message control register make sure
910 * we do not overwrite read-only fields.
912 if ((offset - capoff) == 2 && bytes == 2) {
913 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
914 msgctrl = pci_get_cfgdata16(pi, offset);
916 msgctrl |= val & rwmask;
919 CFGWRITE(pi, offset, val, bytes);
921 msgctrl = pci_get_cfgdata16(pi, capoff + 2);
922 addrlo = pci_get_cfgdata32(pi, capoff + 4);
923 if (msgctrl & PCIM_MSICTRL_64BIT)
924 msgdata = pci_get_cfgdata16(pi, capoff + 12);
926 msgdata = pci_get_cfgdata16(pi, capoff + 8);
928 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
929 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
930 if (pi->pi_msi.enabled) {
931 pi->pi_msi.addr = addrlo;
932 pi->pi_msi.msg_data = msgdata;
933 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
935 pi->pi_msi.maxmsgnum = 0;
937 pci_lintr_update(pi);
941 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
942 int bytes, uint32_t val)
945 /* XXX don't write to the readonly parts */
946 CFGWRITE(pi, offset, val, bytes);
949 #define PCIECAP_VERSION 0x2
951 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
954 struct pciecap pciecap;
956 bzero(&pciecap, sizeof(pciecap));
959 * Use the integrated endpoint type for endpoints on a root complex bus.
961 * NB: bhyve currently only supports a single PCI bus that is the root
962 * complex bus, so all endpoints are integrated.
964 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0))
965 type = PCIEM_TYPE_ROOT_INT_EP;
967 pciecap.capid = PCIY_EXPRESS;
968 pciecap.pcie_capabilities = PCIECAP_VERSION | type;
969 if (type != PCIEM_TYPE_ROOT_INT_EP) {
970 pciecap.link_capabilities = 0x411; /* gen1, x1 */
971 pciecap.link_status = 0x11; /* gen1, x1 */
974 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
979 * This function assumes that 'coff' is in the capabilities region of the
980 * config space. A capoff parameter of zero will force a search for the
984 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val,
985 uint8_t capoff, int capid)
989 /* Do not allow un-aligned writes */
990 if ((offset & (bytes - 1)) != 0)
994 /* Find the capability that we want to update */
995 capoff = CAP_START_OFFSET;
997 nextoff = pci_get_cfgdata8(pi, capoff + 1);
1000 if (offset >= capoff && offset < nextoff)
1005 assert(offset >= capoff);
1006 capid = pci_get_cfgdata8(pi, capoff);
1010 * Capability ID and Next Capability Pointer are readonly.
1011 * However, some o/s's do 4-byte writes that include these.
1012 * For this case, trim the write back to 2 bytes and adjust
1015 if (offset == capoff || offset == capoff + 1) {
1016 if (offset == capoff && bytes == 4) {
1026 msicap_cfgwrite(pi, capoff, offset, bytes, val);
1029 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1032 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1040 pci_emul_iscap(struct pci_devinst *pi, int offset)
1044 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1045 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1046 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1053 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1054 int size, uint64_t *val, void *arg1, long arg2)
1057 * Ignore writes; return 0xff's for reads. The mem read code
1058 * will take care of truncating to the correct size.
1060 if (dir == MEM_F_READ) {
1061 *val = 0xffffffffffffffff;
1068 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1069 int bytes, uint64_t *val, void *arg1, long arg2)
1071 int bus, slot, func, coff, in;
1073 coff = addr & 0xfff;
1074 func = (addr >> 12) & 0x7;
1075 slot = (addr >> 15) & 0x1f;
1076 bus = (addr >> 20) & 0xff;
1077 in = (dir == MEM_F_READ);
1080 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val);
1088 return (PCI_EMUL_ECFG_BASE);
1091 #define BUSIO_ROUNDUP 32
1092 #define BUSMEM_ROUNDUP (1024 * 1024)
1095 init_pci(struct vmctx *ctx)
1097 struct mem_range mr;
1098 struct pci_devemu *pde;
1100 struct slotinfo *si;
1101 struct funcinfo *fi;
1103 int bus, slot, func;
1106 pci_emul_iobase = PCI_EMUL_IOBASE;
1107 pci_emul_membase32 = vm_get_lowmem_limit(ctx);
1108 pci_emul_membase64 = PCI_EMUL_MEMBASE64;
1110 for (bus = 0; bus < MAXBUSES; bus++) {
1111 if ((bi = pci_businfo[bus]) == NULL)
1114 * Keep track of the i/o and memory resources allocated to
1117 bi->iobase = pci_emul_iobase;
1118 bi->membase32 = pci_emul_membase32;
1119 bi->membase64 = pci_emul_membase64;
1121 for (slot = 0; slot < MAXSLOTS; slot++) {
1122 si = &bi->slotinfo[slot];
1123 for (func = 0; func < MAXFUNCS; func++) {
1124 fi = &si->si_funcs[func];
1125 if (fi->fi_name == NULL)
1127 pde = pci_emul_finddev(fi->fi_name);
1128 assert(pde != NULL);
1129 error = pci_emul_init(ctx, pde, bus, slot,
1137 * Add some slop to the I/O and memory resources decoded by
1138 * this bus to give a guest some flexibility if it wants to
1139 * reprogram the BARs.
1141 pci_emul_iobase += BUSIO_ROUNDUP;
1142 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1143 bi->iolimit = pci_emul_iobase;
1145 pci_emul_membase32 += BUSMEM_ROUNDUP;
1146 pci_emul_membase32 = roundup2(pci_emul_membase32,
1148 bi->memlimit32 = pci_emul_membase32;
1150 pci_emul_membase64 += BUSMEM_ROUNDUP;
1151 pci_emul_membase64 = roundup2(pci_emul_membase64,
1153 bi->memlimit64 = pci_emul_membase64;
1157 * PCI backends are initialized before routing INTx interrupts
1158 * so that LPC devices are able to reserve ISA IRQs before
1159 * routing PIRQ pins.
1161 for (bus = 0; bus < MAXBUSES; bus++) {
1162 if ((bi = pci_businfo[bus]) == NULL)
1165 for (slot = 0; slot < MAXSLOTS; slot++) {
1166 si = &bi->slotinfo[slot];
1167 for (func = 0; func < MAXFUNCS; func++) {
1168 fi = &si->si_funcs[func];
1169 if (fi->fi_devi == NULL)
1171 pci_lintr_route(fi->fi_devi);
1178 * The guest physical memory map looks like the following:
1179 * [0, lowmem) guest system memory
1180 * [lowmem, lowmem_limit) memory hole (may be absent)
1181 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation)
1182 * [0xE0000000, 0xF0000000) PCI extended config window
1183 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
1184 * [4GB, 4GB + highmem)
1188 * Accesses to memory addresses that are not allocated to system
1189 * memory or PCI devices return 0xff's.
1191 lowmem = vm_get_lowmem_size(ctx);
1192 bzero(&mr, sizeof(struct mem_range));
1193 mr.name = "PCI hole";
1194 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1196 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1197 mr.handler = pci_emul_fallback_handler;
1198 error = register_mem_fallback(&mr);
1201 /* PCI extended config space */
1202 bzero(&mr, sizeof(struct mem_range));
1203 mr.name = "PCI ECFG";
1204 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1205 mr.base = PCI_EMUL_ECFG_BASE;
1206 mr.size = PCI_EMUL_ECFG_SIZE;
1207 mr.handler = pci_emul_ecfg_handler;
1208 error = register_mem(&mr);
1215 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1219 dsdt_line(" Package ()");
1221 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1222 dsdt_line(" 0x%02X,", pin - 1);
1223 dsdt_line(" Zero,");
1224 dsdt_line(" 0x%X", ioapic_irq);
1229 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1234 name = lpc_pirq_name(pirq_pin);
1237 dsdt_line(" Package ()");
1239 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1240 dsdt_line(" 0x%02X,", pin - 1);
1241 dsdt_line(" %s,", name);
1248 * A bhyve virtual machine has a flat PCI hierarchy with a root port
1249 * corresponding to each PCI bus.
1252 pci_bus_write_dsdt(int bus)
1255 struct slotinfo *si;
1256 struct pci_devinst *pi;
1257 int count, func, slot;
1260 * If there are no devices on this 'bus' then just return.
1262 if ((bi = pci_businfo[bus]) == NULL) {
1264 * Bus 0 is special because it decodes the I/O ports used
1265 * for PCI config space access even if there are no devices
1272 dsdt_line(" Device (PC%02X)", bus);
1274 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))");
1276 dsdt_line(" Method (_BBN, 0, NotSerialized)");
1278 dsdt_line(" Return (0x%08X)", bus);
1280 dsdt_line(" Name (_CRS, ResourceTemplate ()");
1282 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, "
1283 "MaxFixed, PosDecode,");
1284 dsdt_line(" 0x0000, // Granularity");
1285 dsdt_line(" 0x%04X, // Range Minimum", bus);
1286 dsdt_line(" 0x%04X, // Range Maximum", bus);
1287 dsdt_line(" 0x0000, // Translation Offset");
1288 dsdt_line(" 0x0001, // Length");
1293 dsdt_fixed_ioport(0xCF8, 8);
1296 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1297 "PosDecode, EntireRange,");
1298 dsdt_line(" 0x0000, // Granularity");
1299 dsdt_line(" 0x0000, // Range Minimum");
1300 dsdt_line(" 0x0CF7, // Range Maximum");
1301 dsdt_line(" 0x0000, // Translation Offset");
1302 dsdt_line(" 0x0CF8, // Length");
1303 dsdt_line(" ,, , TypeStatic)");
1305 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1306 "PosDecode, EntireRange,");
1307 dsdt_line(" 0x0000, // Granularity");
1308 dsdt_line(" 0x0D00, // Range Minimum");
1309 dsdt_line(" 0x%04X, // Range Maximum",
1310 PCI_EMUL_IOBASE - 1);
1311 dsdt_line(" 0x0000, // Translation Offset");
1312 dsdt_line(" 0x%04X, // Length",
1313 PCI_EMUL_IOBASE - 0x0D00);
1314 dsdt_line(" ,, , TypeStatic)");
1324 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1325 "PosDecode, EntireRange,");
1326 dsdt_line(" 0x0000, // Granularity");
1327 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase);
1328 dsdt_line(" 0x%04X, // Range Maximum",
1330 dsdt_line(" 0x0000, // Translation Offset");
1331 dsdt_line(" 0x%04X, // Length",
1332 bi->iolimit - bi->iobase);
1333 dsdt_line(" ,, , TypeStatic)");
1335 /* mmio window (32-bit) */
1336 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, "
1337 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1338 dsdt_line(" 0x00000000, // Granularity");
1339 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32);
1340 dsdt_line(" 0x%08X, // Range Maximum\n",
1341 bi->memlimit32 - 1);
1342 dsdt_line(" 0x00000000, // Translation Offset");
1343 dsdt_line(" 0x%08X, // Length\n",
1344 bi->memlimit32 - bi->membase32);
1345 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1347 /* mmio window (64-bit) */
1348 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, "
1349 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1350 dsdt_line(" 0x0000000000000000, // Granularity");
1351 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64);
1352 dsdt_line(" 0x%016lX, // Range Maximum\n",
1353 bi->memlimit64 - 1);
1354 dsdt_line(" 0x0000000000000000, // Translation Offset");
1355 dsdt_line(" 0x%016lX, // Length\n",
1356 bi->memlimit64 - bi->membase64);
1357 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1360 count = pci_count_lintr(bus);
1363 dsdt_line("Name (PPRT, Package ()");
1365 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1367 dsdt_line("Name (APRT, Package ()");
1369 pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1371 dsdt_line("Method (_PRT, 0, NotSerialized)");
1373 dsdt_line(" If (PICM)");
1375 dsdt_line(" Return (APRT)");
1379 dsdt_line(" Return (PPRT)");
1386 for (slot = 0; slot < MAXSLOTS; slot++) {
1387 si = &bi->slotinfo[slot];
1388 for (func = 0; func < MAXFUNCS; func++) {
1389 pi = si->si_funcs[func].fi_devi;
1390 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1391 pi->pi_d->pe_write_dsdt(pi);
1400 pci_write_dsdt(void)
1405 dsdt_line("Name (PICM, 0x00)");
1406 dsdt_line("Method (_PIC, 1, NotSerialized)");
1408 dsdt_line(" Store (Arg0, PICM)");
1411 dsdt_line("Scope (_SB)");
1413 for (bus = 0; bus < MAXBUSES; bus++)
1414 pci_bus_write_dsdt(bus);
1420 pci_bus_configured(int bus)
1422 assert(bus >= 0 && bus < MAXBUSES);
1423 return (pci_businfo[bus] != NULL);
1427 pci_msi_enabled(struct pci_devinst *pi)
1429 return (pi->pi_msi.enabled);
1433 pci_msi_maxmsgnum(struct pci_devinst *pi)
1435 if (pi->pi_msi.enabled)
1436 return (pi->pi_msi.maxmsgnum);
1442 pci_msix_enabled(struct pci_devinst *pi)
1445 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1449 pci_generate_msix(struct pci_devinst *pi, int index)
1451 struct msix_table_entry *mte;
1453 if (!pci_msix_enabled(pi))
1456 if (pi->pi_msix.function_mask)
1459 if (index >= pi->pi_msix.table_count)
1462 mte = &pi->pi_msix.table[index];
1463 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1464 /* XXX Set PBA bit if interrupt is disabled */
1465 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1470 pci_generate_msi(struct pci_devinst *pi, int index)
1473 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1474 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1475 pi->pi_msi.msg_data + index);
1480 pci_lintr_permitted(struct pci_devinst *pi)
1484 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1485 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1486 (cmd & PCIM_CMD_INTxDIS)));
1490 pci_lintr_request(struct pci_devinst *pi)
1493 struct slotinfo *si;
1494 int bestpin, bestcount, pin;
1496 bi = pci_businfo[pi->pi_bus];
1500 * Just allocate a pin from our slot. The pin will be
1501 * assigned IRQs later when interrupts are routed.
1503 si = &bi->slotinfo[pi->pi_slot];
1505 bestcount = si->si_intpins[0].ii_count;
1506 for (pin = 1; pin < 4; pin++) {
1507 if (si->si_intpins[pin].ii_count < bestcount) {
1509 bestcount = si->si_intpins[pin].ii_count;
1513 si->si_intpins[bestpin].ii_count++;
1514 pi->pi_lintr.pin = bestpin + 1;
1515 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1519 pci_lintr_route(struct pci_devinst *pi)
1522 struct intxinfo *ii;
1524 if (pi->pi_lintr.pin == 0)
1527 bi = pci_businfo[pi->pi_bus];
1529 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1532 * Attempt to allocate an I/O APIC pin for this intpin if one
1533 * is not yet assigned.
1535 if (ii->ii_ioapic_irq == 0)
1536 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi);
1537 assert(ii->ii_ioapic_irq > 0);
1540 * Attempt to allocate a PIRQ pin for this intpin if one is
1543 if (ii->ii_pirq_pin == 0)
1544 ii->ii_pirq_pin = pirq_alloc_pin(pi);
1545 assert(ii->ii_pirq_pin > 0);
1547 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1548 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1549 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1553 pci_lintr_assert(struct pci_devinst *pi)
1556 assert(pi->pi_lintr.pin > 0);
1558 pthread_mutex_lock(&pi->pi_lintr.lock);
1559 if (pi->pi_lintr.state == IDLE) {
1560 if (pci_lintr_permitted(pi)) {
1561 pi->pi_lintr.state = ASSERTED;
1564 pi->pi_lintr.state = PENDING;
1566 pthread_mutex_unlock(&pi->pi_lintr.lock);
1570 pci_lintr_deassert(struct pci_devinst *pi)
1573 assert(pi->pi_lintr.pin > 0);
1575 pthread_mutex_lock(&pi->pi_lintr.lock);
1576 if (pi->pi_lintr.state == ASSERTED) {
1577 pi->pi_lintr.state = IDLE;
1578 pci_irq_deassert(pi);
1579 } else if (pi->pi_lintr.state == PENDING)
1580 pi->pi_lintr.state = IDLE;
1581 pthread_mutex_unlock(&pi->pi_lintr.lock);
1585 pci_lintr_update(struct pci_devinst *pi)
1588 pthread_mutex_lock(&pi->pi_lintr.lock);
1589 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1590 pci_irq_deassert(pi);
1591 pi->pi_lintr.state = PENDING;
1592 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1593 pi->pi_lintr.state = ASSERTED;
1596 pthread_mutex_unlock(&pi->pi_lintr.lock);
1600 pci_count_lintr(int bus)
1602 int count, slot, pin;
1603 struct slotinfo *slotinfo;
1606 if (pci_businfo[bus] != NULL) {
1607 for (slot = 0; slot < MAXSLOTS; slot++) {
1608 slotinfo = &pci_businfo[bus]->slotinfo[slot];
1609 for (pin = 0; pin < 4; pin++) {
1610 if (slotinfo->si_intpins[pin].ii_count != 0)
1619 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
1622 struct slotinfo *si;
1623 struct intxinfo *ii;
1626 if ((bi = pci_businfo[bus]) == NULL)
1629 for (slot = 0; slot < MAXSLOTS; slot++) {
1630 si = &bi->slotinfo[slot];
1631 for (pin = 0; pin < 4; pin++) {
1632 ii = &si->si_intpins[pin];
1633 if (ii->ii_count != 0)
1634 cb(bus, slot, pin + 1, ii->ii_pirq_pin,
1635 ii->ii_ioapic_irq, arg);
1641 * Return 1 if the emulated device in 'slot' is a multi-function device.
1642 * Return 0 otherwise.
1645 pci_emul_is_mfdev(int bus, int slot)
1648 struct slotinfo *si;
1652 if ((bi = pci_businfo[bus]) != NULL) {
1653 si = &bi->slotinfo[slot];
1654 for (f = 0; f < MAXFUNCS; f++) {
1655 if (si->si_funcs[f].fi_devi != NULL) {
1660 return (numfuncs > 1);
1664 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1665 * whether or not is a multi-function being emulated in the pci 'slot'.
1668 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
1672 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1673 mfdev = pci_emul_is_mfdev(bus, slot);
1683 *rv &= ~(PCIM_MFDEV << 16);
1685 *rv |= (PCIM_MFDEV << 16);
1693 * Update device state in response to changes to the PCI command
1697 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old)
1700 uint16_t changed, new;
1702 new = pci_get_cfgdata16(pi, PCIR_COMMAND);
1703 changed = old ^ new;
1706 * If the MMIO or I/O address space decoding has changed then
1707 * register/unregister all BARs that decode that address space.
1709 for (i = 0; i <= PCI_BARMAX; i++) {
1710 switch (pi->pi_bar[i].type) {
1712 case PCIBAR_MEMHI64:
1715 /* I/O address space decoding changed? */
1716 if (changed & PCIM_CMD_PORTEN) {
1717 if (new & PCIM_CMD_PORTEN)
1718 register_bar(pi, i);
1720 unregister_bar(pi, i);
1725 /* MMIO address space decoding changed? */
1726 if (changed & PCIM_CMD_MEMEN) {
1727 if (new & PCIM_CMD_MEMEN)
1728 register_bar(pi, i);
1730 unregister_bar(pi, i);
1739 * If INTx has been unmasked and is pending, assert the
1742 pci_lintr_update(pi);
1746 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
1749 uint32_t cmd, old, readonly;
1751 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
1754 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3.
1756 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are
1757 * 'write 1 to clear'. However these bits are not set to '1' by
1758 * any device emulation so it is simpler to treat them as readonly.
1760 rshift = (coff & 0x3) * 8;
1761 readonly = 0xFFFFF880 >> rshift;
1763 old = CFGREAD(pi, coff, bytes);
1765 new |= (old & readonly);
1766 CFGWRITE(pi, coff, new, bytes); /* update config */
1768 pci_emul_cmd_changed(pi, cmd);
1772 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
1773 int coff, int bytes, uint32_t *eax)
1776 struct slotinfo *si;
1777 struct pci_devinst *pi;
1778 struct pci_devemu *pe;
1780 uint64_t addr, bar, mask;
1782 if ((bi = pci_businfo[bus]) != NULL) {
1783 si = &bi->slotinfo[slot];
1784 pi = si->si_funcs[func].fi_devi;
1789 * Just return if there is no device at this slot:func or if the
1790 * the guest is doing an un-aligned access.
1792 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
1793 (coff & (bytes - 1)) != 0) {
1800 * Ignore all writes beyond the standard config space and return all
1803 if (coff >= PCI_REGMAX + 1) {
1807 * Extended capabilities begin at offset 256 in config
1808 * space. Absence of extended capabilities is signaled
1809 * with all 0s in the extended capability header at
1812 if (coff <= PCI_REGMAX + 4)
1824 /* Let the device emulation override the default handler */
1825 if (pe->pe_cfgread != NULL) {
1826 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes,
1833 *eax = CFGREAD(pi, coff, bytes);
1835 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
1837 /* Let the device emulation override the default handler */
1838 if (pe->pe_cfgwrite != NULL &&
1839 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
1843 * Special handling for write to BAR registers
1845 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) {
1847 * Ignore writes to BAR registers that are not
1850 if (bytes != 4 || (coff & 0x3) != 0)
1852 idx = (coff - PCIR_BAR(0)) / 4;
1853 mask = ~(pi->pi_bar[idx].size - 1);
1854 switch (pi->pi_bar[idx].type) {
1856 pi->pi_bar[idx].addr = bar = 0;
1861 bar = addr | PCIM_BAR_IO_SPACE;
1863 * Register the new BAR value for interception
1865 if (addr != pi->pi_bar[idx].addr) {
1866 update_bar_address(pi, addr, idx,
1871 addr = bar = *eax & mask;
1872 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
1873 if (addr != pi->pi_bar[idx].addr) {
1874 update_bar_address(pi, addr, idx,
1879 addr = bar = *eax & mask;
1880 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
1881 PCIM_BAR_MEM_PREFETCH;
1882 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
1883 update_bar_address(pi, addr, idx,
1887 case PCIBAR_MEMHI64:
1888 mask = ~(pi->pi_bar[idx - 1].size - 1);
1889 addr = ((uint64_t)*eax << 32) & mask;
1891 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
1892 update_bar_address(pi, addr, idx - 1,
1899 pci_set_cfgdata32(pi, coff, bar);
1901 } else if (pci_emul_iscap(pi, coff)) {
1902 pci_emul_capwrite(pi, coff, bytes, *eax, 0, 0);
1903 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
1904 pci_emul_cmdsts_write(pi, coff, *eax, bytes);
1906 CFGWRITE(pi, coff, *eax, bytes);
1911 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
1914 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1915 uint32_t *eax, void *arg)
1921 *eax = (bytes == 2) ? 0xffff : 0xff;
1926 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
1932 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
1933 cfgoff = x & PCI_REGMAX;
1934 cfgfunc = (x >> 8) & PCI_FUNCMAX;
1935 cfgslot = (x >> 11) & PCI_SLOTMAX;
1936 cfgbus = (x >> 16) & PCI_BUSMAX;
1941 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
1944 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1945 uint32_t *eax, void *arg)
1949 assert(bytes == 1 || bytes == 2 || bytes == 4);
1951 coff = cfgoff + (port - CONF1_DATA_PORT);
1953 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
1956 /* Ignore accesses to cfgdata if not enabled by cfgaddr */
1963 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
1964 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
1965 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
1966 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
1968 #define PCI_EMUL_TEST
1969 #ifdef PCI_EMUL_TEST
1971 * Define a dummy test device
1975 struct pci_emul_dsoftc {
1976 uint8_t ioregs[DIOSZ];
1977 uint8_t memregs[2][DMEMSZ];
1980 #define PCI_EMUL_MSI_MSGS 4
1981 #define PCI_EMUL_MSIX_MSGS 16
1984 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1987 struct pci_emul_dsoftc *sc;
1989 sc = calloc(1, sizeof(struct pci_emul_dsoftc));
1993 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
1994 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
1995 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
1997 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
2000 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
2003 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
2006 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
2013 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2014 uint64_t offset, int size, uint64_t value)
2017 struct pci_emul_dsoftc *sc = pi->pi_arg;
2020 if (offset + size > DIOSZ) {
2021 printf("diow: iow too large, offset %ld size %d\n",
2027 sc->ioregs[offset] = value & 0xff;
2028 } else if (size == 2) {
2029 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
2030 } else if (size == 4) {
2031 *(uint32_t *)&sc->ioregs[offset] = value;
2033 printf("diow: iow unknown size %d\n", size);
2037 * Special magic value to generate an interrupt
2039 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2040 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2042 if (value == 0xabcdef) {
2043 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2044 pci_generate_msi(pi, i);
2048 if (baridx == 1 || baridx == 2) {
2049 if (offset + size > DMEMSZ) {
2050 printf("diow: memw too large, offset %ld size %d\n",
2055 i = baridx - 1; /* 'memregs' index */
2058 sc->memregs[i][offset] = value;
2059 } else if (size == 2) {
2060 *(uint16_t *)&sc->memregs[i][offset] = value;
2061 } else if (size == 4) {
2062 *(uint32_t *)&sc->memregs[i][offset] = value;
2063 } else if (size == 8) {
2064 *(uint64_t *)&sc->memregs[i][offset] = value;
2066 printf("diow: memw unknown size %d\n", size);
2070 * magic interrupt ??
2074 if (baridx > 2 || baridx < 0) {
2075 printf("diow: unknown bar idx %d\n", baridx);
2080 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2081 uint64_t offset, int size)
2083 struct pci_emul_dsoftc *sc = pi->pi_arg;
2088 if (offset + size > DIOSZ) {
2089 printf("dior: ior too large, offset %ld size %d\n",
2096 value = sc->ioregs[offset];
2097 } else if (size == 2) {
2098 value = *(uint16_t *) &sc->ioregs[offset];
2099 } else if (size == 4) {
2100 value = *(uint32_t *) &sc->ioregs[offset];
2102 printf("dior: ior unknown size %d\n", size);
2106 if (baridx == 1 || baridx == 2) {
2107 if (offset + size > DMEMSZ) {
2108 printf("dior: memr too large, offset %ld size %d\n",
2113 i = baridx - 1; /* 'memregs' index */
2116 value = sc->memregs[i][offset];
2117 } else if (size == 2) {
2118 value = *(uint16_t *) &sc->memregs[i][offset];
2119 } else if (size == 4) {
2120 value = *(uint32_t *) &sc->memregs[i][offset];
2121 } else if (size == 8) {
2122 value = *(uint64_t *) &sc->memregs[i][offset];
2124 printf("dior: ior unknown size %d\n", size);
2129 if (baridx > 2 || baridx < 0) {
2130 printf("dior: unknown bar idx %d\n", baridx);
2137 struct pci_devemu pci_dummy = {
2139 .pe_init = pci_emul_dinit,
2140 .pe_barwrite = pci_emul_diow,
2141 .pe_barread = pci_emul_dior
2143 PCI_EMUL_SET(pci_dummy);
2145 #endif /* PCI_EMUL_TEST */