2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
34 #include <sys/errno.h>
45 #include <machine/vmm.h>
57 #define CONF1_ADDR_PORT 0x0cf8
58 #define CONF1_DATA_PORT 0x0cfc
60 #define CONF1_ENABLE 0x80000000ul
62 #define CFGWRITE(pi,off,val,b) \
65 pci_set_cfgdata8((pi),(off),(val)); \
66 } else if ((b) == 2) { \
67 pci_set_cfgdata16((pi),(off),(val)); \
69 pci_set_cfgdata32((pi),(off),(val)); \
73 #define MAXBUSES (PCI_BUSMAX + 1)
74 #define MAXSLOTS (PCI_SLOTMAX + 1)
75 #define MAXFUNCS (PCI_FUNCMAX + 1)
80 struct pci_devinst *fi_devi;
90 struct intxinfo si_intpins[4];
91 struct funcinfo si_funcs[MAXFUNCS];
95 uint16_t iobase, iolimit; /* I/O window */
96 uint32_t membase32, memlimit32; /* mmio window below 4GB */
97 uint64_t membase64, memlimit64; /* mmio window above 4GB */
98 struct slotinfo slotinfo[MAXSLOTS];
101 static struct businfo *pci_businfo[MAXBUSES];
103 SET_DECLARE(pci_devemu_set, struct pci_devemu);
105 static uint64_t pci_emul_iobase;
106 static uint64_t pci_emul_membase32;
107 static uint64_t pci_emul_membase64;
109 #define PCI_EMUL_IOBASE 0x2000
110 #define PCI_EMUL_IOLIMIT 0x10000
112 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
113 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
114 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
116 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
118 #define PCI_EMUL_MEMBASE64 0xD000000000UL
119 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
121 static struct pci_devemu *pci_emul_finddev(char *name);
122 static void pci_lintr_route(struct pci_devinst *pi);
123 static void pci_lintr_update(struct pci_devinst *pi);
124 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
125 int func, int coff, int bytes, uint32_t *val);
132 * Slot options are in the form:
134 * <bus>:<slot>:<func>,<emul>[,<config>]
135 * <slot>[:<func>],<emul>[,<config>]
139 * emul is a string describing the type of PCI device e.g. virtio-net
140 * config is an optional string, depending on the device, that can be
141 * used for configuration.
147 pci_parse_slot_usage(char *aopt)
150 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt);
154 pci_parse_slot(char *opt)
158 char *emul, *config, *str, *cp;
159 int error, bnum, snum, fnum;
164 emul = config = NULL;
165 if ((cp = strchr(str, ',')) != NULL) {
168 if ((cp = strchr(emul, ',')) != NULL) {
173 pci_parse_slot_usage(opt);
177 /* <bus>:<slot>:<func> */
178 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
181 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
184 if (sscanf(str, "%d", &snum) != 1) {
190 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
191 fnum < 0 || fnum >= MAXFUNCS) {
192 pci_parse_slot_usage(opt);
196 if (pci_businfo[bnum] == NULL)
197 pci_businfo[bnum] = calloc(1, sizeof(struct businfo));
199 bi = pci_businfo[bnum];
200 si = &bi->slotinfo[snum];
202 if (si->si_funcs[fnum].fi_name != NULL) {
203 fprintf(stderr, "pci slot %d:%d already occupied!\n",
208 if (pci_emul_finddev(emul) == NULL) {
209 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n",
215 si->si_funcs[fnum].fi_name = emul;
216 si->si_funcs[fnum].fi_param = config;
226 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
229 if (offset < pi->pi_msix.pba_offset)
232 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
240 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
243 int msix_entry_offset;
247 /* support only 4 or 8 byte writes */
248 if (size != 4 && size != 8)
252 * Return if table index is beyond what device supports
254 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
255 if (tab_index >= pi->pi_msix.table_count)
258 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
260 /* support only aligned writes */
261 if ((msix_entry_offset % size) != 0)
264 dest = (char *)(pi->pi_msix.table + tab_index);
265 dest += msix_entry_offset;
268 *((uint32_t *)dest) = value;
270 *((uint64_t *)dest) = value;
276 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
279 int msix_entry_offset;
281 uint64_t retval = ~0;
284 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
285 * table but we also allow 1 byte access to accomodate reads from
288 if (size != 1 && size != 4 && size != 8)
291 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
293 /* support only aligned reads */
294 if ((msix_entry_offset % size) != 0) {
298 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
300 if (tab_index < pi->pi_msix.table_count) {
301 /* valid MSI-X Table access */
302 dest = (char *)(pi->pi_msix.table + tab_index);
303 dest += msix_entry_offset;
306 retval = *((uint8_t *)dest);
308 retval = *((uint32_t *)dest);
310 retval = *((uint64_t *)dest);
311 } else if (pci_valid_pba_offset(pi, offset)) {
312 /* return 0 for PBA access */
320 pci_msix_table_bar(struct pci_devinst *pi)
323 if (pi->pi_msix.table != NULL)
324 return (pi->pi_msix.table_bar);
330 pci_msix_pba_bar(struct pci_devinst *pi)
333 if (pi->pi_msix.table != NULL)
334 return (pi->pi_msix.pba_bar);
340 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
341 uint32_t *eax, void *arg)
343 struct pci_devinst *pdi = arg;
344 struct pci_devemu *pe = pdi->pi_d;
348 for (i = 0; i <= PCI_BARMAX; i++) {
349 if (pdi->pi_bar[i].type == PCIBAR_IO &&
350 port >= pdi->pi_bar[i].addr &&
351 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
352 offset = port - pdi->pi_bar[i].addr;
354 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
357 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
366 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
367 int size, uint64_t *val, void *arg1, long arg2)
369 struct pci_devinst *pdi = arg1;
370 struct pci_devemu *pe = pdi->pi_d;
372 int bidx = (int) arg2;
374 assert(bidx <= PCI_BARMAX);
375 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
376 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
377 assert(addr >= pdi->pi_bar[bidx].addr &&
378 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
380 offset = addr - pdi->pi_bar[bidx].addr;
382 if (dir == MEM_F_WRITE) {
384 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
385 4, *val & 0xffffffff);
386 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
389 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
394 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
396 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
397 offset + 4, 4) << 32;
399 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
409 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
414 assert((size & (size - 1)) == 0); /* must be a power of 2 */
416 base = roundup2(*baseptr, size);
418 if (base + size <= limit) {
420 *baseptr = base + size;
427 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
431 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size));
435 * Register (or unregister) the MMIO or I/O region associated with the BAR
436 * register 'idx' of an emulated pci device.
439 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
442 struct inout_port iop;
445 switch (pi->pi_bar[idx].type) {
447 bzero(&iop, sizeof(struct inout_port));
448 iop.name = pi->pi_name;
449 iop.port = pi->pi_bar[idx].addr;
450 iop.size = pi->pi_bar[idx].size;
452 iop.flags = IOPORT_F_INOUT;
453 iop.handler = pci_emul_io_handler;
455 error = register_inout(&iop);
457 error = unregister_inout(&iop);
461 bzero(&mr, sizeof(struct mem_range));
462 mr.name = pi->pi_name;
463 mr.base = pi->pi_bar[idx].addr;
464 mr.size = pi->pi_bar[idx].size;
467 mr.handler = pci_emul_mem_handler;
470 error = register_mem(&mr);
472 error = unregister_mem(&mr);
482 unregister_bar(struct pci_devinst *pi, int idx)
485 modify_bar_registration(pi, idx, 0);
489 register_bar(struct pci_devinst *pi, int idx)
492 modify_bar_registration(pi, idx, 1);
495 /* Are we decoding i/o port accesses for the emulated pci device? */
497 porten(struct pci_devinst *pi)
501 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
503 return (cmd & PCIM_CMD_PORTEN);
506 /* Are we decoding memory accesses for the emulated pci device? */
508 memen(struct pci_devinst *pi)
512 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
514 return (cmd & PCIM_CMD_MEMEN);
518 * Update the MMIO or I/O address that is decoded by the BAR register.
520 * If the pci device has enabled the address space decoding then intercept
521 * the address range decoded by the BAR register.
524 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
528 if (pi->pi_bar[idx].type == PCIBAR_IO)
534 unregister_bar(pi, idx);
539 pi->pi_bar[idx].addr = addr;
542 pi->pi_bar[idx].addr &= ~0xffffffffUL;
543 pi->pi_bar[idx].addr |= addr;
546 pi->pi_bar[idx].addr &= 0xffffffff;
547 pi->pi_bar[idx].addr |= addr;
554 register_bar(pi, idx);
558 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
559 enum pcibar_type type, uint64_t size)
562 uint64_t *baseptr, limit, addr, mask, lobits, bar;
564 assert(idx >= 0 && idx <= PCI_BARMAX);
566 if ((size & (size - 1)) != 0)
567 size = 1UL << flsl(size); /* round up to a power of 2 */
569 /* Enforce minimum BAR sizes required by the PCI standard */
570 if (type == PCIBAR_IO) {
581 addr = mask = lobits = 0;
584 baseptr = &pci_emul_iobase;
585 limit = PCI_EMUL_IOLIMIT;
586 mask = PCIM_BAR_IO_BASE;
587 lobits = PCIM_BAR_IO_SPACE;
592 * Some drivers do not work well if the 64-bit BAR is allocated
593 * above 4GB. Allow for this by allocating small requests under
594 * 4GB unless then allocation size is larger than some arbitrary
595 * number (32MB currently).
597 if (size > 32 * 1024 * 1024) {
599 * XXX special case for device requiring peer-peer DMA
601 if (size == 0x100000000UL)
604 baseptr = &pci_emul_membase64;
605 limit = PCI_EMUL_MEMLIMIT64;
606 mask = PCIM_BAR_MEM_BASE;
607 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
608 PCIM_BAR_MEM_PREFETCH;
611 baseptr = &pci_emul_membase32;
612 limit = PCI_EMUL_MEMLIMIT32;
613 mask = PCIM_BAR_MEM_BASE;
614 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
618 baseptr = &pci_emul_membase32;
619 limit = PCI_EMUL_MEMLIMIT32;
620 mask = PCIM_BAR_MEM_BASE;
621 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
624 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
628 if (baseptr != NULL) {
629 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
634 pdi->pi_bar[idx].type = type;
635 pdi->pi_bar[idx].addr = addr;
636 pdi->pi_bar[idx].size = size;
638 /* Initialize the BAR register in config space */
639 bar = (addr & mask) | lobits;
640 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
642 if (type == PCIBAR_MEM64) {
643 assert(idx + 1 <= PCI_BARMAX);
644 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
645 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
648 register_bar(pdi, idx);
653 #define CAP_START_OFFSET 0x40
655 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
657 int i, capoff, reallen;
662 reallen = roundup2(caplen, 4); /* dword aligned */
664 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
665 if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
666 capoff = CAP_START_OFFSET;
668 capoff = pi->pi_capend + 1;
670 /* Check if we have enough space */
671 if (capoff + reallen > PCI_REGMAX + 1)
674 /* Set the previous capability pointer */
675 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
676 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
677 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
679 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
681 /* Copy the capability */
682 for (i = 0; i < caplen; i++)
683 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
685 /* Set the next capability pointer */
686 pci_set_cfgdata8(pi, capoff + 1, 0);
688 pi->pi_prevcap = capoff;
689 pi->pi_capend = capoff + reallen - 1;
693 static struct pci_devemu *
694 pci_emul_finddev(char *name)
696 struct pci_devemu **pdpp, *pdp;
698 SET_FOREACH(pdpp, pci_devemu_set) {
700 if (!strcmp(pdp->pe_emu, name)) {
709 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
710 int func, struct funcinfo *fi)
712 struct pci_devinst *pdi;
715 pdi = calloc(1, sizeof(struct pci_devinst));
721 pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
722 pdi->pi_lintr.pin = 0;
723 pdi->pi_lintr.state = IDLE;
724 pdi->pi_lintr.pirq_pin = 0;
725 pdi->pi_lintr.ioapic_irq = 0;
727 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
729 /* Disable legacy interrupts */
730 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
731 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
733 pci_set_cfgdata8(pdi, PCIR_COMMAND,
734 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
736 err = (*pde->pe_init)(ctx, pdi, fi->fi_param);
746 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
750 CTASSERT(sizeof(struct msicap) == 14);
752 /* Number of msi messages must be a power of 2 between 1 and 32 */
753 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
754 mmc = ffs(msgnum) - 1;
756 bzero(msicap, sizeof(struct msicap));
757 msicap->capid = PCIY_MSI;
758 msicap->nextptr = nextptr;
759 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
763 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
765 struct msicap msicap;
767 pci_populate_msicap(&msicap, msgnum, 0);
769 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
773 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
774 uint32_t msix_tab_size)
776 CTASSERT(sizeof(struct msixcap) == 12);
778 assert(msix_tab_size % 4096 == 0);
780 bzero(msixcap, sizeof(struct msixcap));
781 msixcap->capid = PCIY_MSIX;
784 * Message Control Register, all fields set to
785 * zero except for the Table Size.
786 * Note: Table size N is encoded as N-1
788 msixcap->msgctrl = msgnum - 1;
792 * - MSI-X table start at offset 0
793 * - PBA table starts at a 4K aligned offset after the MSI-X table
795 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
796 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
800 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
804 assert(table_entries > 0);
805 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
807 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
808 pi->pi_msix.table = calloc(1, table_size);
810 /* set mask bit of vector control register */
811 for (i = 0; i < table_entries; i++)
812 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
816 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
819 struct msixcap msixcap;
821 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
822 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
824 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
826 /* Align table size to nearest 4K */
827 tab_size = roundup2(tab_size, 4096);
829 pi->pi_msix.table_bar = barnum;
830 pi->pi_msix.pba_bar = barnum;
831 pi->pi_msix.table_offset = 0;
832 pi->pi_msix.table_count = msgnum;
833 pi->pi_msix.pba_offset = tab_size;
834 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
836 pci_msix_table_init(pi, msgnum);
838 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
840 /* allocate memory for MSI-X Table and PBA */
841 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
842 tab_size + pi->pi_msix.pba_size);
844 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
849 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
850 int bytes, uint32_t val)
852 uint16_t msgctrl, rwmask;
855 off = offset - capoff;
856 table_bar = pi->pi_msix.table_bar;
857 /* Message Control Register */
858 if (off == 2 && bytes == 2) {
859 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
860 msgctrl = pci_get_cfgdata16(pi, offset);
862 msgctrl |= val & rwmask;
865 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
866 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
867 pci_lintr_update(pi);
870 CFGWRITE(pi, offset, val, bytes);
874 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
875 int bytes, uint32_t val)
877 uint16_t msgctrl, rwmask, msgdata, mme;
881 * If guest is writing to the message control register make sure
882 * we do not overwrite read-only fields.
884 if ((offset - capoff) == 2 && bytes == 2) {
885 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
886 msgctrl = pci_get_cfgdata16(pi, offset);
888 msgctrl |= val & rwmask;
891 addrlo = pci_get_cfgdata32(pi, capoff + 4);
892 if (msgctrl & PCIM_MSICTRL_64BIT)
893 msgdata = pci_get_cfgdata16(pi, capoff + 12);
895 msgdata = pci_get_cfgdata16(pi, capoff + 8);
897 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
898 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
899 if (pi->pi_msi.enabled) {
900 pi->pi_msi.addr = addrlo;
901 pi->pi_msi.msg_data = msgdata;
902 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
904 pi->pi_msi.maxmsgnum = 0;
906 pci_lintr_update(pi);
909 CFGWRITE(pi, offset, val, bytes);
913 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
914 int bytes, uint32_t val)
917 /* XXX don't write to the readonly parts */
918 CFGWRITE(pi, offset, val, bytes);
921 #define PCIECAP_VERSION 0x2
923 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
926 struct pciecap pciecap;
928 CTASSERT(sizeof(struct pciecap) == 60);
930 if (type != PCIEM_TYPE_ROOT_PORT)
933 bzero(&pciecap, sizeof(pciecap));
935 pciecap.capid = PCIY_EXPRESS;
936 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT;
937 pciecap.link_capabilities = 0x411; /* gen1, x1 */
938 pciecap.link_status = 0x11; /* gen1, x1 */
940 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
945 * This function assumes that 'coff' is in the capabilities region of the
949 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val)
952 uint8_t capoff, nextoff;
954 /* Do not allow un-aligned writes */
955 if ((offset & (bytes - 1)) != 0)
958 /* Find the capability that we want to update */
959 capoff = CAP_START_OFFSET;
961 nextoff = pci_get_cfgdata8(pi, capoff + 1);
964 if (offset >= capoff && offset < nextoff)
969 assert(offset >= capoff);
972 * Capability ID and Next Capability Pointer are readonly.
973 * However, some o/s's do 4-byte writes that include these.
974 * For this case, trim the write back to 2 bytes and adjust
977 if (offset == capoff || offset == capoff + 1) {
978 if (offset == capoff && bytes == 4) {
986 capid = pci_get_cfgdata8(pi, capoff);
989 msicap_cfgwrite(pi, capoff, offset, bytes, val);
992 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
995 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1003 pci_emul_iscap(struct pci_devinst *pi, int offset)
1007 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1008 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1009 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1016 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1017 int size, uint64_t *val, void *arg1, long arg2)
1020 * Ignore writes; return 0xff's for reads. The mem read code
1021 * will take care of truncating to the correct size.
1023 if (dir == MEM_F_READ) {
1024 *val = 0xffffffffffffffff;
1031 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1032 int bytes, uint64_t *val, void *arg1, long arg2)
1034 int bus, slot, func, coff, in;
1036 coff = addr & 0xfff;
1037 func = (addr >> 12) & 0x7;
1038 slot = (addr >> 15) & 0x1f;
1039 bus = (addr >> 20) & 0xff;
1040 in = (dir == MEM_F_READ);
1043 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val);
1051 return (PCI_EMUL_ECFG_BASE);
1054 #define BUSIO_ROUNDUP 32
1055 #define BUSMEM_ROUNDUP (1024 * 1024)
1058 init_pci(struct vmctx *ctx)
1060 struct mem_range mr;
1061 struct pci_devemu *pde;
1063 struct slotinfo *si;
1064 struct funcinfo *fi;
1066 int bus, slot, func;
1069 pci_emul_iobase = PCI_EMUL_IOBASE;
1070 pci_emul_membase32 = vm_get_lowmem_limit(ctx);
1071 pci_emul_membase64 = PCI_EMUL_MEMBASE64;
1073 for (bus = 0; bus < MAXBUSES; bus++) {
1074 if ((bi = pci_businfo[bus]) == NULL)
1077 * Keep track of the i/o and memory resources allocated to
1080 bi->iobase = pci_emul_iobase;
1081 bi->membase32 = pci_emul_membase32;
1082 bi->membase64 = pci_emul_membase64;
1084 for (slot = 0; slot < MAXSLOTS; slot++) {
1085 si = &bi->slotinfo[slot];
1086 for (func = 0; func < MAXFUNCS; func++) {
1087 fi = &si->si_funcs[func];
1088 if (fi->fi_name == NULL)
1090 pde = pci_emul_finddev(fi->fi_name);
1091 assert(pde != NULL);
1092 error = pci_emul_init(ctx, pde, bus, slot,
1100 * Add some slop to the I/O and memory resources decoded by
1101 * this bus to give a guest some flexibility if it wants to
1102 * reprogram the BARs.
1104 pci_emul_iobase += BUSIO_ROUNDUP;
1105 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1106 bi->iolimit = pci_emul_iobase;
1108 pci_emul_membase32 += BUSMEM_ROUNDUP;
1109 pci_emul_membase32 = roundup2(pci_emul_membase32,
1111 bi->memlimit32 = pci_emul_membase32;
1113 pci_emul_membase64 += BUSMEM_ROUNDUP;
1114 pci_emul_membase64 = roundup2(pci_emul_membase64,
1116 bi->memlimit64 = pci_emul_membase64;
1120 * PCI backends are initialized before routing INTx interrupts
1121 * so that LPC devices are able to reserve ISA IRQs before
1122 * routing PIRQ pins.
1124 for (bus = 0; bus < MAXBUSES; bus++) {
1125 if ((bi = pci_businfo[bus]) == NULL)
1128 for (slot = 0; slot < MAXSLOTS; slot++) {
1129 si = &bi->slotinfo[slot];
1130 for (func = 0; func < MAXFUNCS; func++) {
1131 fi = &si->si_funcs[func];
1132 if (fi->fi_devi == NULL)
1134 pci_lintr_route(fi->fi_devi);
1141 * The guest physical memory map looks like the following:
1142 * [0, lowmem) guest system memory
1143 * [lowmem, lowmem_limit) memory hole (may be absent)
1144 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation)
1145 * [0xE0000000, 0xF0000000) PCI extended config window
1146 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
1147 * [4GB, 4GB + highmem)
1151 * Accesses to memory addresses that are not allocated to system
1152 * memory or PCI devices return 0xff's.
1154 lowmem = vm_get_lowmem_size(ctx);
1155 bzero(&mr, sizeof(struct mem_range));
1156 mr.name = "PCI hole";
1157 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1159 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1160 mr.handler = pci_emul_fallback_handler;
1161 error = register_mem_fallback(&mr);
1164 /* PCI extended config space */
1165 bzero(&mr, sizeof(struct mem_range));
1166 mr.name = "PCI ECFG";
1167 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1168 mr.base = PCI_EMUL_ECFG_BASE;
1169 mr.size = PCI_EMUL_ECFG_SIZE;
1170 mr.handler = pci_emul_ecfg_handler;
1171 error = register_mem(&mr);
1178 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1182 dsdt_line(" Package ()");
1184 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1185 dsdt_line(" 0x%02X,", pin - 1);
1186 dsdt_line(" Zero,");
1187 dsdt_line(" 0x%X", ioapic_irq);
1192 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1197 name = lpc_pirq_name(pirq_pin);
1200 dsdt_line(" Package ()");
1202 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1203 dsdt_line(" 0x%02X,", pin - 1);
1204 dsdt_line(" %s,", name);
1211 * A bhyve virtual machine has a flat PCI hierarchy with a root port
1212 * corresponding to each PCI bus.
1215 pci_bus_write_dsdt(int bus)
1218 struct slotinfo *si;
1219 struct pci_devinst *pi;
1220 int count, func, slot;
1223 * If there are no devices on this 'bus' then just return.
1225 if ((bi = pci_businfo[bus]) == NULL) {
1227 * Bus 0 is special because it decodes the I/O ports used
1228 * for PCI config space access even if there are no devices
1235 dsdt_line(" Device (PC%02X)", bus);
1237 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))");
1238 dsdt_line(" Name (_ADR, Zero)");
1240 dsdt_line(" Method (_BBN, 0, NotSerialized)");
1242 dsdt_line(" Return (0x%08X)", bus);
1244 dsdt_line(" Name (_CRS, ResourceTemplate ()");
1246 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, "
1247 "MaxFixed, PosDecode,");
1248 dsdt_line(" 0x0000, // Granularity");
1249 dsdt_line(" 0x%04X, // Range Minimum", bus);
1250 dsdt_line(" 0x%04X, // Range Maximum", bus);
1251 dsdt_line(" 0x0000, // Translation Offset");
1252 dsdt_line(" 0x0001, // Length");
1257 dsdt_fixed_ioport(0xCF8, 8);
1260 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1261 "PosDecode, EntireRange,");
1262 dsdt_line(" 0x0000, // Granularity");
1263 dsdt_line(" 0x0000, // Range Minimum");
1264 dsdt_line(" 0x0CF7, // Range Maximum");
1265 dsdt_line(" 0x0000, // Translation Offset");
1266 dsdt_line(" 0x0CF8, // Length");
1267 dsdt_line(" ,, , TypeStatic)");
1269 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1270 "PosDecode, EntireRange,");
1271 dsdt_line(" 0x0000, // Granularity");
1272 dsdt_line(" 0x0D00, // Range Minimum");
1273 dsdt_line(" 0x%04X, // Range Maximum",
1274 PCI_EMUL_IOBASE - 1);
1275 dsdt_line(" 0x0000, // Translation Offset");
1276 dsdt_line(" 0x%04X, // Length",
1277 PCI_EMUL_IOBASE - 0x0D00);
1278 dsdt_line(" ,, , TypeStatic)");
1288 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1289 "PosDecode, EntireRange,");
1290 dsdt_line(" 0x0000, // Granularity");
1291 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase);
1292 dsdt_line(" 0x%04X, // Range Maximum",
1294 dsdt_line(" 0x0000, // Translation Offset");
1295 dsdt_line(" 0x%04X, // Length",
1296 bi->iolimit - bi->iobase);
1297 dsdt_line(" ,, , TypeStatic)");
1299 /* mmio window (32-bit) */
1300 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, "
1301 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1302 dsdt_line(" 0x00000000, // Granularity");
1303 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32);
1304 dsdt_line(" 0x%08X, // Range Maximum\n",
1305 bi->memlimit32 - 1);
1306 dsdt_line(" 0x00000000, // Translation Offset");
1307 dsdt_line(" 0x%08X, // Length\n",
1308 bi->memlimit32 - bi->membase32);
1309 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1311 /* mmio window (64-bit) */
1312 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, "
1313 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1314 dsdt_line(" 0x0000000000000000, // Granularity");
1315 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64);
1316 dsdt_line(" 0x%016lX, // Range Maximum\n",
1317 bi->memlimit64 - 1);
1318 dsdt_line(" 0x0000000000000000, // Translation Offset");
1319 dsdt_line(" 0x%016lX, // Length\n",
1320 bi->memlimit64 - bi->membase64);
1321 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1324 count = pci_count_lintr(bus);
1327 dsdt_line("Name (PPRT, Package ()");
1329 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1331 dsdt_line("Name (APRT, Package ()");
1333 pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1335 dsdt_line("Method (_PRT, 0, NotSerialized)");
1337 dsdt_line(" If (PICM)");
1339 dsdt_line(" Return (APRT)");
1343 dsdt_line(" Return (PPRT)");
1350 for (slot = 0; slot < MAXSLOTS; slot++) {
1351 si = &bi->slotinfo[slot];
1352 for (func = 0; func < MAXFUNCS; func++) {
1353 pi = si->si_funcs[func].fi_devi;
1354 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1355 pi->pi_d->pe_write_dsdt(pi);
1364 pci_write_dsdt(void)
1369 dsdt_line("Name (PICM, 0x00)");
1370 dsdt_line("Method (_PIC, 1, NotSerialized)");
1372 dsdt_line(" Store (Arg0, PICM)");
1375 dsdt_line("Scope (_SB)");
1377 for (bus = 0; bus < MAXBUSES; bus++)
1378 pci_bus_write_dsdt(bus);
1384 pci_bus_configured(int bus)
1386 assert(bus >= 0 && bus < MAXBUSES);
1387 return (pci_businfo[bus] != NULL);
1391 pci_msi_enabled(struct pci_devinst *pi)
1393 return (pi->pi_msi.enabled);
1397 pci_msi_maxmsgnum(struct pci_devinst *pi)
1399 if (pi->pi_msi.enabled)
1400 return (pi->pi_msi.maxmsgnum);
1406 pci_msix_enabled(struct pci_devinst *pi)
1409 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1413 pci_generate_msix(struct pci_devinst *pi, int index)
1415 struct msix_table_entry *mte;
1417 if (!pci_msix_enabled(pi))
1420 if (pi->pi_msix.function_mask)
1423 if (index >= pi->pi_msix.table_count)
1426 mte = &pi->pi_msix.table[index];
1427 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1428 /* XXX Set PBA bit if interrupt is disabled */
1429 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1434 pci_generate_msi(struct pci_devinst *pi, int index)
1437 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1438 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1439 pi->pi_msi.msg_data + index);
1444 pci_lintr_permitted(struct pci_devinst *pi)
1448 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1449 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1450 (cmd & PCIM_CMD_INTxDIS)));
1454 pci_lintr_request(struct pci_devinst *pi)
1457 struct slotinfo *si;
1458 int bestpin, bestcount, pin;
1460 bi = pci_businfo[pi->pi_bus];
1464 * Just allocate a pin from our slot. The pin will be
1465 * assigned IRQs later when interrupts are routed.
1467 si = &bi->slotinfo[pi->pi_slot];
1469 bestcount = si->si_intpins[0].ii_count;
1470 for (pin = 1; pin < 4; pin++) {
1471 if (si->si_intpins[pin].ii_count < bestcount) {
1473 bestcount = si->si_intpins[pin].ii_count;
1477 si->si_intpins[bestpin].ii_count++;
1478 pi->pi_lintr.pin = bestpin + 1;
1479 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1483 pci_lintr_route(struct pci_devinst *pi)
1486 struct intxinfo *ii;
1488 if (pi->pi_lintr.pin == 0)
1491 bi = pci_businfo[pi->pi_bus];
1493 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1496 * Attempt to allocate an I/O APIC pin for this intpin if one
1497 * is not yet assigned.
1499 if (ii->ii_ioapic_irq == 0)
1500 ii->ii_ioapic_irq = ioapic_pci_alloc_irq();
1501 assert(ii->ii_ioapic_irq > 0);
1504 * Attempt to allocate a PIRQ pin for this intpin if one is
1507 if (ii->ii_pirq_pin == 0)
1508 ii->ii_pirq_pin = pirq_alloc_pin(pi->pi_vmctx);
1509 assert(ii->ii_pirq_pin > 0);
1511 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1512 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1513 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1517 pci_lintr_assert(struct pci_devinst *pi)
1520 assert(pi->pi_lintr.pin > 0);
1522 pthread_mutex_lock(&pi->pi_lintr.lock);
1523 if (pi->pi_lintr.state == IDLE) {
1524 if (pci_lintr_permitted(pi)) {
1525 pi->pi_lintr.state = ASSERTED;
1528 pi->pi_lintr.state = PENDING;
1530 pthread_mutex_unlock(&pi->pi_lintr.lock);
1534 pci_lintr_deassert(struct pci_devinst *pi)
1537 assert(pi->pi_lintr.pin > 0);
1539 pthread_mutex_lock(&pi->pi_lintr.lock);
1540 if (pi->pi_lintr.state == ASSERTED) {
1541 pi->pi_lintr.state = IDLE;
1542 pci_irq_deassert(pi);
1543 } else if (pi->pi_lintr.state == PENDING)
1544 pi->pi_lintr.state = IDLE;
1545 pthread_mutex_unlock(&pi->pi_lintr.lock);
1549 pci_lintr_update(struct pci_devinst *pi)
1552 pthread_mutex_lock(&pi->pi_lintr.lock);
1553 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1554 pci_irq_deassert(pi);
1555 pi->pi_lintr.state = PENDING;
1556 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1557 pi->pi_lintr.state = ASSERTED;
1560 pthread_mutex_unlock(&pi->pi_lintr.lock);
1564 pci_count_lintr(int bus)
1566 int count, slot, pin;
1567 struct slotinfo *slotinfo;
1570 if (pci_businfo[bus] != NULL) {
1571 for (slot = 0; slot < MAXSLOTS; slot++) {
1572 slotinfo = &pci_businfo[bus]->slotinfo[slot];
1573 for (pin = 0; pin < 4; pin++) {
1574 if (slotinfo->si_intpins[pin].ii_count != 0)
1583 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
1586 struct slotinfo *si;
1587 struct intxinfo *ii;
1590 if ((bi = pci_businfo[bus]) == NULL)
1593 for (slot = 0; slot < MAXSLOTS; slot++) {
1594 si = &bi->slotinfo[slot];
1595 for (pin = 0; pin < 4; pin++) {
1596 ii = &si->si_intpins[pin];
1597 if (ii->ii_count != 0)
1598 cb(bus, slot, pin + 1, ii->ii_pirq_pin,
1599 ii->ii_ioapic_irq, arg);
1605 * Return 1 if the emulated device in 'slot' is a multi-function device.
1606 * Return 0 otherwise.
1609 pci_emul_is_mfdev(int bus, int slot)
1612 struct slotinfo *si;
1616 if ((bi = pci_businfo[bus]) != NULL) {
1617 si = &bi->slotinfo[slot];
1618 for (f = 0; f < MAXFUNCS; f++) {
1619 if (si->si_funcs[f].fi_devi != NULL) {
1624 return (numfuncs > 1);
1628 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1629 * whether or not is a multi-function being emulated in the pci 'slot'.
1632 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
1636 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1637 mfdev = pci_emul_is_mfdev(bus, slot);
1647 *rv &= ~(PCIM_MFDEV << 16);
1649 *rv |= (PCIM_MFDEV << 16);
1657 bits_changed(uint32_t old, uint32_t new, uint32_t mask)
1660 return ((old ^ new) & mask);
1664 pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes)
1670 * The command register is at an offset of 4 bytes and thus the
1671 * guest could write 1, 2 or 4 bytes starting at this offset.
1674 old = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
1675 CFGWRITE(pi, PCIR_COMMAND, new, bytes); /* update config */
1676 new = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */
1679 * If the MMIO or I/O address space decoding has changed then
1680 * register/unregister all BARs that decode that address space.
1682 for (i = 0; i <= PCI_BARMAX; i++) {
1683 switch (pi->pi_bar[i].type) {
1685 case PCIBAR_MEMHI64:
1688 /* I/O address space decoding changed? */
1689 if (bits_changed(old, new, PCIM_CMD_PORTEN)) {
1691 register_bar(pi, i);
1693 unregister_bar(pi, i);
1698 /* MMIO address space decoding changed? */
1699 if (bits_changed(old, new, PCIM_CMD_MEMEN)) {
1701 register_bar(pi, i);
1703 unregister_bar(pi, i);
1712 * If INTx has been unmasked and is pending, assert the
1715 pci_lintr_update(pi);
1719 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
1720 int coff, int bytes, uint32_t *eax)
1723 struct slotinfo *si;
1724 struct pci_devinst *pi;
1725 struct pci_devemu *pe;
1727 uint64_t addr, bar, mask;
1729 if ((bi = pci_businfo[bus]) != NULL) {
1730 si = &bi->slotinfo[slot];
1731 pi = si->si_funcs[func].fi_devi;
1736 * Just return if there is no device at this slot:func or if the
1737 * the guest is doing an un-aligned access.
1739 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
1740 (coff & (bytes - 1)) != 0) {
1747 * Ignore all writes beyond the standard config space and return all
1750 if (coff >= PCI_REGMAX + 1) {
1754 * Extended capabilities begin at offset 256 in config
1755 * space. Absence of extended capabilities is signaled
1756 * with all 0s in the extended capability header at
1759 if (coff <= PCI_REGMAX + 4)
1771 /* Let the device emulation override the default handler */
1772 if (pe->pe_cfgread != NULL) {
1773 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes,
1781 *eax = pci_get_cfgdata8(pi, coff);
1782 else if (bytes == 2)
1783 *eax = pci_get_cfgdata16(pi, coff);
1785 *eax = pci_get_cfgdata32(pi, coff);
1788 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
1790 /* Let the device emulation override the default handler */
1791 if (pe->pe_cfgwrite != NULL &&
1792 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
1796 * Special handling for write to BAR registers
1798 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) {
1800 * Ignore writes to BAR registers that are not
1803 if (bytes != 4 || (coff & 0x3) != 0)
1805 idx = (coff - PCIR_BAR(0)) / 4;
1806 mask = ~(pi->pi_bar[idx].size - 1);
1807 switch (pi->pi_bar[idx].type) {
1809 pi->pi_bar[idx].addr = bar = 0;
1814 bar = addr | PCIM_BAR_IO_SPACE;
1816 * Register the new BAR value for interception
1818 if (addr != pi->pi_bar[idx].addr) {
1819 update_bar_address(pi, addr, idx,
1824 addr = bar = *eax & mask;
1825 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
1826 if (addr != pi->pi_bar[idx].addr) {
1827 update_bar_address(pi, addr, idx,
1832 addr = bar = *eax & mask;
1833 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
1834 PCIM_BAR_MEM_PREFETCH;
1835 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
1836 update_bar_address(pi, addr, idx,
1840 case PCIBAR_MEMHI64:
1841 mask = ~(pi->pi_bar[idx - 1].size - 1);
1842 addr = ((uint64_t)*eax << 32) & mask;
1844 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
1845 update_bar_address(pi, addr, idx - 1,
1852 pci_set_cfgdata32(pi, coff, bar);
1854 } else if (pci_emul_iscap(pi, coff)) {
1855 pci_emul_capwrite(pi, coff, bytes, *eax);
1856 } else if (coff == PCIR_COMMAND) {
1857 pci_emul_cmdwrite(pi, *eax, bytes);
1859 CFGWRITE(pi, coff, *eax, bytes);
1864 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
1867 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1868 uint32_t *eax, void *arg)
1874 *eax = (bytes == 2) ? 0xffff : 0xff;
1879 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
1885 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
1886 cfgoff = x & PCI_REGMAX;
1887 cfgfunc = (x >> 8) & PCI_FUNCMAX;
1888 cfgslot = (x >> 11) & PCI_SLOTMAX;
1889 cfgbus = (x >> 16) & PCI_BUSMAX;
1894 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
1897 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1898 uint32_t *eax, void *arg)
1902 assert(bytes == 1 || bytes == 2 || bytes == 4);
1904 coff = cfgoff + (port - CONF1_DATA_PORT);
1906 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
1909 /* Ignore accesses to cfgdata if not enabled by cfgaddr */
1916 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
1917 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
1918 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
1919 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
1921 #define PCI_EMUL_TEST
1922 #ifdef PCI_EMUL_TEST
1924 * Define a dummy test device
1928 struct pci_emul_dsoftc {
1929 uint8_t ioregs[DIOSZ];
1930 uint8_t memregs[DMEMSZ];
1933 #define PCI_EMUL_MSI_MSGS 4
1934 #define PCI_EMUL_MSIX_MSGS 16
1937 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1940 struct pci_emul_dsoftc *sc;
1942 sc = calloc(1, sizeof(struct pci_emul_dsoftc));
1946 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
1947 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
1948 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
1950 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
1953 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
1956 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
1963 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1964 uint64_t offset, int size, uint64_t value)
1967 struct pci_emul_dsoftc *sc = pi->pi_arg;
1970 if (offset + size > DIOSZ) {
1971 printf("diow: iow too large, offset %ld size %d\n",
1977 sc->ioregs[offset] = value & 0xff;
1978 } else if (size == 2) {
1979 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
1980 } else if (size == 4) {
1981 *(uint32_t *)&sc->ioregs[offset] = value;
1983 printf("diow: iow unknown size %d\n", size);
1987 * Special magic value to generate an interrupt
1989 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
1990 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
1992 if (value == 0xabcdef) {
1993 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
1994 pci_generate_msi(pi, i);
1999 if (offset + size > DMEMSZ) {
2000 printf("diow: memw too large, offset %ld size %d\n",
2006 sc->memregs[offset] = value;
2007 } else if (size == 2) {
2008 *(uint16_t *)&sc->memregs[offset] = value;
2009 } else if (size == 4) {
2010 *(uint32_t *)&sc->memregs[offset] = value;
2011 } else if (size == 8) {
2012 *(uint64_t *)&sc->memregs[offset] = value;
2014 printf("diow: memw unknown size %d\n", size);
2018 * magic interrupt ??
2023 printf("diow: unknown bar idx %d\n", baridx);
2028 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2029 uint64_t offset, int size)
2031 struct pci_emul_dsoftc *sc = pi->pi_arg;
2035 if (offset + size > DIOSZ) {
2036 printf("dior: ior too large, offset %ld size %d\n",
2042 value = sc->ioregs[offset];
2043 } else if (size == 2) {
2044 value = *(uint16_t *) &sc->ioregs[offset];
2045 } else if (size == 4) {
2046 value = *(uint32_t *) &sc->ioregs[offset];
2048 printf("dior: ior unknown size %d\n", size);
2053 if (offset + size > DMEMSZ) {
2054 printf("dior: memr too large, offset %ld size %d\n",
2060 value = sc->memregs[offset];
2061 } else if (size == 2) {
2062 value = *(uint16_t *) &sc->memregs[offset];
2063 } else if (size == 4) {
2064 value = *(uint32_t *) &sc->memregs[offset];
2065 } else if (size == 8) {
2066 value = *(uint64_t *) &sc->memregs[offset];
2068 printf("dior: ior unknown size %d\n", size);
2074 printf("dior: unknown bar idx %d\n", baridx);
2081 struct pci_devemu pci_dummy = {
2083 .pe_init = pci_emul_dinit,
2084 .pe_barwrite = pci_emul_diow,
2085 .pe_barread = pci_emul_dior
2087 PCI_EMUL_SET(pci_dummy);
2089 #endif /* PCI_EMUL_TEST */