2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/linker_set.h>
47 #include <machine/vmm.h>
59 #define CONF1_ADDR_PORT 0x0cf8
60 #define CONF1_DATA_PORT 0x0cfc
62 #define CONF1_ENABLE 0x80000000ul
64 #define MAXBUSES (PCI_BUSMAX + 1)
65 #define MAXSLOTS (PCI_SLOTMAX + 1)
66 #define MAXFUNCS (PCI_FUNCMAX + 1)
71 struct pci_devinst *fi_devi;
81 struct intxinfo si_intpins[4];
82 struct funcinfo si_funcs[MAXFUNCS];
86 uint16_t iobase, iolimit; /* I/O window */
87 uint32_t membase32, memlimit32; /* mmio window below 4GB */
88 uint64_t membase64, memlimit64; /* mmio window above 4GB */
89 struct slotinfo slotinfo[MAXSLOTS];
92 static struct businfo *pci_businfo[MAXBUSES];
94 SET_DECLARE(pci_devemu_set, struct pci_devemu);
96 static uint64_t pci_emul_iobase;
97 static uint64_t pci_emul_membase32;
98 static uint64_t pci_emul_membase64;
100 #define PCI_EMUL_IOBASE 0x2000
101 #define PCI_EMUL_IOLIMIT 0x10000
103 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
104 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
105 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
107 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
109 #define PCI_EMUL_MEMBASE64 0xD000000000UL
110 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
112 static struct pci_devemu *pci_emul_finddev(char *name);
113 static void pci_lintr_route(struct pci_devinst *pi);
114 static void pci_lintr_update(struct pci_devinst *pi);
115 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
116 int func, int coff, int bytes, uint32_t *val);
119 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
123 pci_set_cfgdata8(pi, coff, val);
125 pci_set_cfgdata16(pi, coff, val);
127 pci_set_cfgdata32(pi, coff, val);
130 static __inline uint32_t
131 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
135 return (pci_get_cfgdata8(pi, coff));
137 return (pci_get_cfgdata16(pi, coff));
139 return (pci_get_cfgdata32(pi, coff));
147 * Slot options are in the form:
149 * <bus>:<slot>:<func>,<emul>[,<config>]
150 * <slot>[:<func>],<emul>[,<config>]
154 * emul is a string describing the type of PCI device e.g. virtio-net
155 * config is an optional string, depending on the device, that can be
156 * used for configuration.
162 pci_parse_slot_usage(char *aopt)
165 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt);
169 pci_parse_slot(char *opt)
173 char *emul, *config, *str, *cp;
174 int error, bnum, snum, fnum;
179 emul = config = NULL;
180 if ((cp = strchr(str, ',')) != NULL) {
183 if ((cp = strchr(emul, ',')) != NULL) {
188 pci_parse_slot_usage(opt);
192 /* <bus>:<slot>:<func> */
193 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
196 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
199 if (sscanf(str, "%d", &snum) != 1) {
205 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
206 fnum < 0 || fnum >= MAXFUNCS) {
207 pci_parse_slot_usage(opt);
211 if (pci_businfo[bnum] == NULL)
212 pci_businfo[bnum] = calloc(1, sizeof(struct businfo));
214 bi = pci_businfo[bnum];
215 si = &bi->slotinfo[snum];
217 if (si->si_funcs[fnum].fi_name != NULL) {
218 fprintf(stderr, "pci slot %d:%d already occupied!\n",
223 if (pci_emul_finddev(emul) == NULL) {
224 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n",
230 si->si_funcs[fnum].fi_name = emul;
231 si->si_funcs[fnum].fi_param = config;
241 pci_print_supported_devices()
243 struct pci_devemu **pdpp, *pdp;
245 SET_FOREACH(pdpp, pci_devemu_set) {
247 printf("%s\n", pdp->pe_emu);
252 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
255 if (offset < pi->pi_msix.pba_offset)
258 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
266 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
269 int msix_entry_offset;
273 /* support only 4 or 8 byte writes */
274 if (size != 4 && size != 8)
278 * Return if table index is beyond what device supports
280 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
281 if (tab_index >= pi->pi_msix.table_count)
284 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
286 /* support only aligned writes */
287 if ((msix_entry_offset % size) != 0)
290 dest = (char *)(pi->pi_msix.table + tab_index);
291 dest += msix_entry_offset;
294 *((uint32_t *)dest) = value;
296 *((uint64_t *)dest) = value;
302 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
305 int msix_entry_offset;
307 uint64_t retval = ~0;
310 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
311 * table but we also allow 1 byte access to accommodate reads from
314 if (size != 1 && size != 4 && size != 8)
317 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
319 /* support only aligned reads */
320 if ((msix_entry_offset % size) != 0) {
324 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
326 if (tab_index < pi->pi_msix.table_count) {
327 /* valid MSI-X Table access */
328 dest = (char *)(pi->pi_msix.table + tab_index);
329 dest += msix_entry_offset;
332 retval = *((uint8_t *)dest);
334 retval = *((uint32_t *)dest);
336 retval = *((uint64_t *)dest);
337 } else if (pci_valid_pba_offset(pi, offset)) {
338 /* return 0 for PBA access */
346 pci_msix_table_bar(struct pci_devinst *pi)
349 if (pi->pi_msix.table != NULL)
350 return (pi->pi_msix.table_bar);
356 pci_msix_pba_bar(struct pci_devinst *pi)
359 if (pi->pi_msix.table != NULL)
360 return (pi->pi_msix.pba_bar);
366 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
367 uint32_t *eax, void *arg)
369 struct pci_devinst *pdi = arg;
370 struct pci_devemu *pe = pdi->pi_d;
374 for (i = 0; i <= PCI_BARMAX; i++) {
375 if (pdi->pi_bar[i].type == PCIBAR_IO &&
376 port >= pdi->pi_bar[i].addr &&
377 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
378 offset = port - pdi->pi_bar[i].addr;
380 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
383 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
392 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
393 int size, uint64_t *val, void *arg1, long arg2)
395 struct pci_devinst *pdi = arg1;
396 struct pci_devemu *pe = pdi->pi_d;
398 int bidx = (int) arg2;
400 assert(bidx <= PCI_BARMAX);
401 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
402 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
403 assert(addr >= pdi->pi_bar[bidx].addr &&
404 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
406 offset = addr - pdi->pi_bar[bidx].addr;
408 if (dir == MEM_F_WRITE) {
410 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
411 4, *val & 0xffffffff);
412 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
415 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
420 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
422 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
423 offset + 4, 4) << 32;
425 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
435 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
440 assert((size & (size - 1)) == 0); /* must be a power of 2 */
442 base = roundup2(*baseptr, size);
444 if (base + size <= limit) {
446 *baseptr = base + size;
453 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
457 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size));
461 * Register (or unregister) the MMIO or I/O region associated with the BAR
462 * register 'idx' of an emulated pci device.
465 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
468 struct inout_port iop;
471 switch (pi->pi_bar[idx].type) {
473 bzero(&iop, sizeof(struct inout_port));
474 iop.name = pi->pi_name;
475 iop.port = pi->pi_bar[idx].addr;
476 iop.size = pi->pi_bar[idx].size;
478 iop.flags = IOPORT_F_INOUT;
479 iop.handler = pci_emul_io_handler;
481 error = register_inout(&iop);
483 error = unregister_inout(&iop);
487 bzero(&mr, sizeof(struct mem_range));
488 mr.name = pi->pi_name;
489 mr.base = pi->pi_bar[idx].addr;
490 mr.size = pi->pi_bar[idx].size;
493 mr.handler = pci_emul_mem_handler;
496 error = register_mem(&mr);
498 error = unregister_mem(&mr);
508 unregister_bar(struct pci_devinst *pi, int idx)
511 modify_bar_registration(pi, idx, 0);
515 register_bar(struct pci_devinst *pi, int idx)
518 modify_bar_registration(pi, idx, 1);
521 /* Are we decoding i/o port accesses for the emulated pci device? */
523 porten(struct pci_devinst *pi)
527 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
529 return (cmd & PCIM_CMD_PORTEN);
532 /* Are we decoding memory accesses for the emulated pci device? */
534 memen(struct pci_devinst *pi)
538 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
540 return (cmd & PCIM_CMD_MEMEN);
544 * Update the MMIO or I/O address that is decoded by the BAR register.
546 * If the pci device has enabled the address space decoding then intercept
547 * the address range decoded by the BAR register.
550 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
554 if (pi->pi_bar[idx].type == PCIBAR_IO)
560 unregister_bar(pi, idx);
565 pi->pi_bar[idx].addr = addr;
568 pi->pi_bar[idx].addr &= ~0xffffffffUL;
569 pi->pi_bar[idx].addr |= addr;
572 pi->pi_bar[idx].addr &= 0xffffffff;
573 pi->pi_bar[idx].addr |= addr;
580 register_bar(pi, idx);
584 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
585 enum pcibar_type type, uint64_t size)
588 uint64_t *baseptr, limit, addr, mask, lobits, bar;
590 assert(idx >= 0 && idx <= PCI_BARMAX);
592 if ((size & (size - 1)) != 0)
593 size = 1UL << flsl(size); /* round up to a power of 2 */
595 /* Enforce minimum BAR sizes required by the PCI standard */
596 if (type == PCIBAR_IO) {
607 addr = mask = lobits = 0;
610 baseptr = &pci_emul_iobase;
611 limit = PCI_EMUL_IOLIMIT;
612 mask = PCIM_BAR_IO_BASE;
613 lobits = PCIM_BAR_IO_SPACE;
618 * Some drivers do not work well if the 64-bit BAR is allocated
619 * above 4GB. Allow for this by allocating small requests under
620 * 4GB unless then allocation size is larger than some arbitrary
621 * number (32MB currently).
623 if (size > 32 * 1024 * 1024) {
625 * XXX special case for device requiring peer-peer DMA
627 if (size == 0x100000000UL)
630 baseptr = &pci_emul_membase64;
631 limit = PCI_EMUL_MEMLIMIT64;
632 mask = PCIM_BAR_MEM_BASE;
633 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
634 PCIM_BAR_MEM_PREFETCH;
637 baseptr = &pci_emul_membase32;
638 limit = PCI_EMUL_MEMLIMIT32;
639 mask = PCIM_BAR_MEM_BASE;
640 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
644 baseptr = &pci_emul_membase32;
645 limit = PCI_EMUL_MEMLIMIT32;
646 mask = PCIM_BAR_MEM_BASE;
647 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
650 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
654 if (baseptr != NULL) {
655 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
660 pdi->pi_bar[idx].type = type;
661 pdi->pi_bar[idx].addr = addr;
662 pdi->pi_bar[idx].size = size;
664 /* Initialize the BAR register in config space */
665 bar = (addr & mask) | lobits;
666 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
668 if (type == PCIBAR_MEM64) {
669 assert(idx + 1 <= PCI_BARMAX);
670 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
671 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
674 register_bar(pdi, idx);
679 #define CAP_START_OFFSET 0x40
681 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
683 int i, capoff, reallen;
688 reallen = roundup2(caplen, 4); /* dword aligned */
690 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
691 if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
692 capoff = CAP_START_OFFSET;
694 capoff = pi->pi_capend + 1;
696 /* Check if we have enough space */
697 if (capoff + reallen > PCI_REGMAX + 1)
700 /* Set the previous capability pointer */
701 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
702 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
703 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
705 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
707 /* Copy the capability */
708 for (i = 0; i < caplen; i++)
709 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
711 /* Set the next capability pointer */
712 pci_set_cfgdata8(pi, capoff + 1, 0);
714 pi->pi_prevcap = capoff;
715 pi->pi_capend = capoff + reallen - 1;
719 static struct pci_devemu *
720 pci_emul_finddev(char *name)
722 struct pci_devemu **pdpp, *pdp;
724 SET_FOREACH(pdpp, pci_devemu_set) {
726 if (!strcmp(pdp->pe_emu, name)) {
735 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
736 int func, struct funcinfo *fi)
738 struct pci_devinst *pdi;
741 pdi = calloc(1, sizeof(struct pci_devinst));
747 pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
748 pdi->pi_lintr.pin = 0;
749 pdi->pi_lintr.state = IDLE;
750 pdi->pi_lintr.pirq_pin = 0;
751 pdi->pi_lintr.ioapic_irq = 0;
753 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
755 /* Disable legacy interrupts */
756 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
757 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
759 pci_set_cfgdata8(pdi, PCIR_COMMAND,
760 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
762 err = (*pde->pe_init)(ctx, pdi, fi->fi_param);
772 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
776 /* Number of msi messages must be a power of 2 between 1 and 32 */
777 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
778 mmc = ffs(msgnum) - 1;
780 bzero(msicap, sizeof(struct msicap));
781 msicap->capid = PCIY_MSI;
782 msicap->nextptr = nextptr;
783 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
787 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
789 struct msicap msicap;
791 pci_populate_msicap(&msicap, msgnum, 0);
793 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
797 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
798 uint32_t msix_tab_size)
801 assert(msix_tab_size % 4096 == 0);
803 bzero(msixcap, sizeof(struct msixcap));
804 msixcap->capid = PCIY_MSIX;
807 * Message Control Register, all fields set to
808 * zero except for the Table Size.
809 * Note: Table size N is encoded as N-1
811 msixcap->msgctrl = msgnum - 1;
815 * - MSI-X table start at offset 0
816 * - PBA table starts at a 4K aligned offset after the MSI-X table
818 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
819 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
823 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
827 assert(table_entries > 0);
828 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
830 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
831 pi->pi_msix.table = calloc(1, table_size);
833 /* set mask bit of vector control register */
834 for (i = 0; i < table_entries; i++)
835 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
839 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
842 struct msixcap msixcap;
844 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
845 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
847 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
849 /* Align table size to nearest 4K */
850 tab_size = roundup2(tab_size, 4096);
852 pi->pi_msix.table_bar = barnum;
853 pi->pi_msix.pba_bar = barnum;
854 pi->pi_msix.table_offset = 0;
855 pi->pi_msix.table_count = msgnum;
856 pi->pi_msix.pba_offset = tab_size;
857 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
859 pci_msix_table_init(pi, msgnum);
861 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
863 /* allocate memory for MSI-X Table and PBA */
864 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
865 tab_size + pi->pi_msix.pba_size);
867 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
872 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
873 int bytes, uint32_t val)
875 uint16_t msgctrl, rwmask;
878 off = offset - capoff;
879 /* Message Control Register */
880 if (off == 2 && bytes == 2) {
881 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
882 msgctrl = pci_get_cfgdata16(pi, offset);
884 msgctrl |= val & rwmask;
887 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
888 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
889 pci_lintr_update(pi);
892 CFGWRITE(pi, offset, val, bytes);
896 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
897 int bytes, uint32_t val)
899 uint16_t msgctrl, rwmask, msgdata, mme;
903 * If guest is writing to the message control register make sure
904 * we do not overwrite read-only fields.
906 if ((offset - capoff) == 2 && bytes == 2) {
907 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
908 msgctrl = pci_get_cfgdata16(pi, offset);
910 msgctrl |= val & rwmask;
913 addrlo = pci_get_cfgdata32(pi, capoff + 4);
914 if (msgctrl & PCIM_MSICTRL_64BIT)
915 msgdata = pci_get_cfgdata16(pi, capoff + 12);
917 msgdata = pci_get_cfgdata16(pi, capoff + 8);
919 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
920 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
921 if (pi->pi_msi.enabled) {
922 pi->pi_msi.addr = addrlo;
923 pi->pi_msi.msg_data = msgdata;
924 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
926 pi->pi_msi.maxmsgnum = 0;
928 pci_lintr_update(pi);
931 CFGWRITE(pi, offset, val, bytes);
935 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
936 int bytes, uint32_t val)
939 /* XXX don't write to the readonly parts */
940 CFGWRITE(pi, offset, val, bytes);
943 #define PCIECAP_VERSION 0x2
945 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
948 struct pciecap pciecap;
950 bzero(&pciecap, sizeof(pciecap));
953 * Use the integrated endpoint type for endpoints on a root complex bus.
955 * NB: bhyve currently only supports a single PCI bus that is the root
956 * complex bus, so all endpoints are integrated.
958 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0))
959 type = PCIEM_TYPE_ROOT_INT_EP;
961 pciecap.capid = PCIY_EXPRESS;
962 pciecap.pcie_capabilities = PCIECAP_VERSION | type;
963 if (type != PCIEM_TYPE_ROOT_INT_EP) {
964 pciecap.link_capabilities = 0x411; /* gen1, x1 */
965 pciecap.link_status = 0x11; /* gen1, x1 */
968 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
973 * This function assumes that 'coff' is in the capabilities region of the
974 * config space. A capoff parameter of zero will force a search for the
978 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val,
979 uint8_t capoff, int capid)
983 /* Do not allow un-aligned writes */
984 if ((offset & (bytes - 1)) != 0)
988 /* Find the capability that we want to update */
989 capoff = CAP_START_OFFSET;
991 nextoff = pci_get_cfgdata8(pi, capoff + 1);
994 if (offset >= capoff && offset < nextoff)
999 assert(offset >= capoff);
1000 capid = pci_get_cfgdata8(pi, capoff);
1004 * Capability ID and Next Capability Pointer are readonly.
1005 * However, some o/s's do 4-byte writes that include these.
1006 * For this case, trim the write back to 2 bytes and adjust
1009 if (offset == capoff || offset == capoff + 1) {
1010 if (offset == capoff && bytes == 4) {
1020 msicap_cfgwrite(pi, capoff, offset, bytes, val);
1023 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1026 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1034 pci_emul_iscap(struct pci_devinst *pi, int offset)
1038 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1039 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1040 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1047 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1048 int size, uint64_t *val, void *arg1, long arg2)
1051 * Ignore writes; return 0xff's for reads. The mem read code
1052 * will take care of truncating to the correct size.
1054 if (dir == MEM_F_READ) {
1055 *val = 0xffffffffffffffff;
1062 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1063 int bytes, uint64_t *val, void *arg1, long arg2)
1065 int bus, slot, func, coff, in;
1067 coff = addr & 0xfff;
1068 func = (addr >> 12) & 0x7;
1069 slot = (addr >> 15) & 0x1f;
1070 bus = (addr >> 20) & 0xff;
1071 in = (dir == MEM_F_READ);
1074 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val);
1082 return (PCI_EMUL_ECFG_BASE);
1085 #define BUSIO_ROUNDUP 32
1086 #define BUSMEM_ROUNDUP (1024 * 1024)
1089 init_pci(struct vmctx *ctx)
1091 struct mem_range mr;
1092 struct pci_devemu *pde;
1094 struct slotinfo *si;
1095 struct funcinfo *fi;
1097 int bus, slot, func;
1100 pci_emul_iobase = PCI_EMUL_IOBASE;
1101 pci_emul_membase32 = vm_get_lowmem_limit(ctx);
1102 pci_emul_membase64 = PCI_EMUL_MEMBASE64;
1104 for (bus = 0; bus < MAXBUSES; bus++) {
1105 if ((bi = pci_businfo[bus]) == NULL)
1108 * Keep track of the i/o and memory resources allocated to
1111 bi->iobase = pci_emul_iobase;
1112 bi->membase32 = pci_emul_membase32;
1113 bi->membase64 = pci_emul_membase64;
1115 for (slot = 0; slot < MAXSLOTS; slot++) {
1116 si = &bi->slotinfo[slot];
1117 for (func = 0; func < MAXFUNCS; func++) {
1118 fi = &si->si_funcs[func];
1119 if (fi->fi_name == NULL)
1121 pde = pci_emul_finddev(fi->fi_name);
1122 assert(pde != NULL);
1123 error = pci_emul_init(ctx, pde, bus, slot,
1131 * Add some slop to the I/O and memory resources decoded by
1132 * this bus to give a guest some flexibility if it wants to
1133 * reprogram the BARs.
1135 pci_emul_iobase += BUSIO_ROUNDUP;
1136 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1137 bi->iolimit = pci_emul_iobase;
1139 pci_emul_membase32 += BUSMEM_ROUNDUP;
1140 pci_emul_membase32 = roundup2(pci_emul_membase32,
1142 bi->memlimit32 = pci_emul_membase32;
1144 pci_emul_membase64 += BUSMEM_ROUNDUP;
1145 pci_emul_membase64 = roundup2(pci_emul_membase64,
1147 bi->memlimit64 = pci_emul_membase64;
1151 * PCI backends are initialized before routing INTx interrupts
1152 * so that LPC devices are able to reserve ISA IRQs before
1153 * routing PIRQ pins.
1155 for (bus = 0; bus < MAXBUSES; bus++) {
1156 if ((bi = pci_businfo[bus]) == NULL)
1159 for (slot = 0; slot < MAXSLOTS; slot++) {
1160 si = &bi->slotinfo[slot];
1161 for (func = 0; func < MAXFUNCS; func++) {
1162 fi = &si->si_funcs[func];
1163 if (fi->fi_devi == NULL)
1165 pci_lintr_route(fi->fi_devi);
1172 * The guest physical memory map looks like the following:
1173 * [0, lowmem) guest system memory
1174 * [lowmem, lowmem_limit) memory hole (may be absent)
1175 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation)
1176 * [0xE0000000, 0xF0000000) PCI extended config window
1177 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
1178 * [4GB, 4GB + highmem)
1182 * Accesses to memory addresses that are not allocated to system
1183 * memory or PCI devices return 0xff's.
1185 lowmem = vm_get_lowmem_size(ctx);
1186 bzero(&mr, sizeof(struct mem_range));
1187 mr.name = "PCI hole";
1188 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1190 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1191 mr.handler = pci_emul_fallback_handler;
1192 error = register_mem_fallback(&mr);
1195 /* PCI extended config space */
1196 bzero(&mr, sizeof(struct mem_range));
1197 mr.name = "PCI ECFG";
1198 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1199 mr.base = PCI_EMUL_ECFG_BASE;
1200 mr.size = PCI_EMUL_ECFG_SIZE;
1201 mr.handler = pci_emul_ecfg_handler;
1202 error = register_mem(&mr);
1209 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1213 dsdt_line(" Package ()");
1215 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1216 dsdt_line(" 0x%02X,", pin - 1);
1217 dsdt_line(" Zero,");
1218 dsdt_line(" 0x%X", ioapic_irq);
1223 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1228 name = lpc_pirq_name(pirq_pin);
1231 dsdt_line(" Package ()");
1233 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1234 dsdt_line(" 0x%02X,", pin - 1);
1235 dsdt_line(" %s,", name);
1242 * A bhyve virtual machine has a flat PCI hierarchy with a root port
1243 * corresponding to each PCI bus.
1246 pci_bus_write_dsdt(int bus)
1249 struct slotinfo *si;
1250 struct pci_devinst *pi;
1251 int count, func, slot;
1254 * If there are no devices on this 'bus' then just return.
1256 if ((bi = pci_businfo[bus]) == NULL) {
1258 * Bus 0 is special because it decodes the I/O ports used
1259 * for PCI config space access even if there are no devices
1266 dsdt_line(" Device (PC%02X)", bus);
1268 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))");
1269 dsdt_line(" Name (_ADR, Zero)");
1271 dsdt_line(" Method (_BBN, 0, NotSerialized)");
1273 dsdt_line(" Return (0x%08X)", bus);
1275 dsdt_line(" Name (_CRS, ResourceTemplate ()");
1277 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, "
1278 "MaxFixed, PosDecode,");
1279 dsdt_line(" 0x0000, // Granularity");
1280 dsdt_line(" 0x%04X, // Range Minimum", bus);
1281 dsdt_line(" 0x%04X, // Range Maximum", bus);
1282 dsdt_line(" 0x0000, // Translation Offset");
1283 dsdt_line(" 0x0001, // Length");
1288 dsdt_fixed_ioport(0xCF8, 8);
1291 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1292 "PosDecode, EntireRange,");
1293 dsdt_line(" 0x0000, // Granularity");
1294 dsdt_line(" 0x0000, // Range Minimum");
1295 dsdt_line(" 0x0CF7, // Range Maximum");
1296 dsdt_line(" 0x0000, // Translation Offset");
1297 dsdt_line(" 0x0CF8, // Length");
1298 dsdt_line(" ,, , TypeStatic)");
1300 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1301 "PosDecode, EntireRange,");
1302 dsdt_line(" 0x0000, // Granularity");
1303 dsdt_line(" 0x0D00, // Range Minimum");
1304 dsdt_line(" 0x%04X, // Range Maximum",
1305 PCI_EMUL_IOBASE - 1);
1306 dsdt_line(" 0x0000, // Translation Offset");
1307 dsdt_line(" 0x%04X, // Length",
1308 PCI_EMUL_IOBASE - 0x0D00);
1309 dsdt_line(" ,, , TypeStatic)");
1319 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1320 "PosDecode, EntireRange,");
1321 dsdt_line(" 0x0000, // Granularity");
1322 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase);
1323 dsdt_line(" 0x%04X, // Range Maximum",
1325 dsdt_line(" 0x0000, // Translation Offset");
1326 dsdt_line(" 0x%04X, // Length",
1327 bi->iolimit - bi->iobase);
1328 dsdt_line(" ,, , TypeStatic)");
1330 /* mmio window (32-bit) */
1331 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, "
1332 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1333 dsdt_line(" 0x00000000, // Granularity");
1334 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32);
1335 dsdt_line(" 0x%08X, // Range Maximum\n",
1336 bi->memlimit32 - 1);
1337 dsdt_line(" 0x00000000, // Translation Offset");
1338 dsdt_line(" 0x%08X, // Length\n",
1339 bi->memlimit32 - bi->membase32);
1340 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1342 /* mmio window (64-bit) */
1343 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, "
1344 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1345 dsdt_line(" 0x0000000000000000, // Granularity");
1346 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64);
1347 dsdt_line(" 0x%016lX, // Range Maximum\n",
1348 bi->memlimit64 - 1);
1349 dsdt_line(" 0x0000000000000000, // Translation Offset");
1350 dsdt_line(" 0x%016lX, // Length\n",
1351 bi->memlimit64 - bi->membase64);
1352 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1355 count = pci_count_lintr(bus);
1358 dsdt_line("Name (PPRT, Package ()");
1360 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1362 dsdt_line("Name (APRT, Package ()");
1364 pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1366 dsdt_line("Method (_PRT, 0, NotSerialized)");
1368 dsdt_line(" If (PICM)");
1370 dsdt_line(" Return (APRT)");
1374 dsdt_line(" Return (PPRT)");
1381 for (slot = 0; slot < MAXSLOTS; slot++) {
1382 si = &bi->slotinfo[slot];
1383 for (func = 0; func < MAXFUNCS; func++) {
1384 pi = si->si_funcs[func].fi_devi;
1385 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1386 pi->pi_d->pe_write_dsdt(pi);
1395 pci_write_dsdt(void)
1400 dsdt_line("Name (PICM, 0x00)");
1401 dsdt_line("Method (_PIC, 1, NotSerialized)");
1403 dsdt_line(" Store (Arg0, PICM)");
1406 dsdt_line("Scope (_SB)");
1408 for (bus = 0; bus < MAXBUSES; bus++)
1409 pci_bus_write_dsdt(bus);
1415 pci_bus_configured(int bus)
1417 assert(bus >= 0 && bus < MAXBUSES);
1418 return (pci_businfo[bus] != NULL);
1422 pci_msi_enabled(struct pci_devinst *pi)
1424 return (pi->pi_msi.enabled);
1428 pci_msi_maxmsgnum(struct pci_devinst *pi)
1430 if (pi->pi_msi.enabled)
1431 return (pi->pi_msi.maxmsgnum);
1437 pci_msix_enabled(struct pci_devinst *pi)
1440 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1444 pci_generate_msix(struct pci_devinst *pi, int index)
1446 struct msix_table_entry *mte;
1448 if (!pci_msix_enabled(pi))
1451 if (pi->pi_msix.function_mask)
1454 if (index >= pi->pi_msix.table_count)
1457 mte = &pi->pi_msix.table[index];
1458 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1459 /* XXX Set PBA bit if interrupt is disabled */
1460 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1465 pci_generate_msi(struct pci_devinst *pi, int index)
1468 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1469 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1470 pi->pi_msi.msg_data + index);
1475 pci_lintr_permitted(struct pci_devinst *pi)
1479 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1480 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1481 (cmd & PCIM_CMD_INTxDIS)));
1485 pci_lintr_request(struct pci_devinst *pi)
1488 struct slotinfo *si;
1489 int bestpin, bestcount, pin;
1491 bi = pci_businfo[pi->pi_bus];
1495 * Just allocate a pin from our slot. The pin will be
1496 * assigned IRQs later when interrupts are routed.
1498 si = &bi->slotinfo[pi->pi_slot];
1500 bestcount = si->si_intpins[0].ii_count;
1501 for (pin = 1; pin < 4; pin++) {
1502 if (si->si_intpins[pin].ii_count < bestcount) {
1504 bestcount = si->si_intpins[pin].ii_count;
1508 si->si_intpins[bestpin].ii_count++;
1509 pi->pi_lintr.pin = bestpin + 1;
1510 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1514 pci_lintr_route(struct pci_devinst *pi)
1517 struct intxinfo *ii;
1519 if (pi->pi_lintr.pin == 0)
1522 bi = pci_businfo[pi->pi_bus];
1524 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1527 * Attempt to allocate an I/O APIC pin for this intpin if one
1528 * is not yet assigned.
1530 if (ii->ii_ioapic_irq == 0)
1531 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi);
1532 assert(ii->ii_ioapic_irq > 0);
1535 * Attempt to allocate a PIRQ pin for this intpin if one is
1538 if (ii->ii_pirq_pin == 0)
1539 ii->ii_pirq_pin = pirq_alloc_pin(pi);
1540 assert(ii->ii_pirq_pin > 0);
1542 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1543 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1544 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1548 pci_lintr_assert(struct pci_devinst *pi)
1551 assert(pi->pi_lintr.pin > 0);
1553 pthread_mutex_lock(&pi->pi_lintr.lock);
1554 if (pi->pi_lintr.state == IDLE) {
1555 if (pci_lintr_permitted(pi)) {
1556 pi->pi_lintr.state = ASSERTED;
1559 pi->pi_lintr.state = PENDING;
1561 pthread_mutex_unlock(&pi->pi_lintr.lock);
1565 pci_lintr_deassert(struct pci_devinst *pi)
1568 assert(pi->pi_lintr.pin > 0);
1570 pthread_mutex_lock(&pi->pi_lintr.lock);
1571 if (pi->pi_lintr.state == ASSERTED) {
1572 pi->pi_lintr.state = IDLE;
1573 pci_irq_deassert(pi);
1574 } else if (pi->pi_lintr.state == PENDING)
1575 pi->pi_lintr.state = IDLE;
1576 pthread_mutex_unlock(&pi->pi_lintr.lock);
1580 pci_lintr_update(struct pci_devinst *pi)
1583 pthread_mutex_lock(&pi->pi_lintr.lock);
1584 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1585 pci_irq_deassert(pi);
1586 pi->pi_lintr.state = PENDING;
1587 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1588 pi->pi_lintr.state = ASSERTED;
1591 pthread_mutex_unlock(&pi->pi_lintr.lock);
1595 pci_count_lintr(int bus)
1597 int count, slot, pin;
1598 struct slotinfo *slotinfo;
1601 if (pci_businfo[bus] != NULL) {
1602 for (slot = 0; slot < MAXSLOTS; slot++) {
1603 slotinfo = &pci_businfo[bus]->slotinfo[slot];
1604 for (pin = 0; pin < 4; pin++) {
1605 if (slotinfo->si_intpins[pin].ii_count != 0)
1614 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
1617 struct slotinfo *si;
1618 struct intxinfo *ii;
1621 if ((bi = pci_businfo[bus]) == NULL)
1624 for (slot = 0; slot < MAXSLOTS; slot++) {
1625 si = &bi->slotinfo[slot];
1626 for (pin = 0; pin < 4; pin++) {
1627 ii = &si->si_intpins[pin];
1628 if (ii->ii_count != 0)
1629 cb(bus, slot, pin + 1, ii->ii_pirq_pin,
1630 ii->ii_ioapic_irq, arg);
1636 * Return 1 if the emulated device in 'slot' is a multi-function device.
1637 * Return 0 otherwise.
1640 pci_emul_is_mfdev(int bus, int slot)
1643 struct slotinfo *si;
1647 if ((bi = pci_businfo[bus]) != NULL) {
1648 si = &bi->slotinfo[slot];
1649 for (f = 0; f < MAXFUNCS; f++) {
1650 if (si->si_funcs[f].fi_devi != NULL) {
1655 return (numfuncs > 1);
1659 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1660 * whether or not is a multi-function being emulated in the pci 'slot'.
1663 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
1667 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1668 mfdev = pci_emul_is_mfdev(bus, slot);
1678 *rv &= ~(PCIM_MFDEV << 16);
1680 *rv |= (PCIM_MFDEV << 16);
1688 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
1691 uint32_t cmd, cmd2, changed, old, readonly;
1693 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
1696 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3.
1698 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are
1699 * 'write 1 to clear'. However these bits are not set to '1' by
1700 * any device emulation so it is simpler to treat them as readonly.
1702 rshift = (coff & 0x3) * 8;
1703 readonly = 0xFFFFF880 >> rshift;
1705 old = CFGREAD(pi, coff, bytes);
1707 new |= (old & readonly);
1708 CFGWRITE(pi, coff, new, bytes); /* update config */
1710 cmd2 = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */
1711 changed = cmd ^ cmd2;
1714 * If the MMIO or I/O address space decoding has changed then
1715 * register/unregister all BARs that decode that address space.
1717 for (i = 0; i <= PCI_BARMAX; i++) {
1718 switch (pi->pi_bar[i].type) {
1720 case PCIBAR_MEMHI64:
1723 /* I/O address space decoding changed? */
1724 if (changed & PCIM_CMD_PORTEN) {
1726 register_bar(pi, i);
1728 unregister_bar(pi, i);
1733 /* MMIO address space decoding changed? */
1734 if (changed & PCIM_CMD_MEMEN) {
1736 register_bar(pi, i);
1738 unregister_bar(pi, i);
1747 * If INTx has been unmasked and is pending, assert the
1750 pci_lintr_update(pi);
1754 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
1755 int coff, int bytes, uint32_t *eax)
1758 struct slotinfo *si;
1759 struct pci_devinst *pi;
1760 struct pci_devemu *pe;
1762 uint64_t addr, bar, mask;
1764 if ((bi = pci_businfo[bus]) != NULL) {
1765 si = &bi->slotinfo[slot];
1766 pi = si->si_funcs[func].fi_devi;
1771 * Just return if there is no device at this slot:func or if the
1772 * the guest is doing an un-aligned access.
1774 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
1775 (coff & (bytes - 1)) != 0) {
1782 * Ignore all writes beyond the standard config space and return all
1785 if (coff >= PCI_REGMAX + 1) {
1789 * Extended capabilities begin at offset 256 in config
1790 * space. Absence of extended capabilities is signaled
1791 * with all 0s in the extended capability header at
1794 if (coff <= PCI_REGMAX + 4)
1806 /* Let the device emulation override the default handler */
1807 if (pe->pe_cfgread != NULL) {
1808 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes,
1815 *eax = CFGREAD(pi, coff, bytes);
1817 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
1819 /* Let the device emulation override the default handler */
1820 if (pe->pe_cfgwrite != NULL &&
1821 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
1825 * Special handling for write to BAR registers
1827 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) {
1829 * Ignore writes to BAR registers that are not
1832 if (bytes != 4 || (coff & 0x3) != 0)
1834 idx = (coff - PCIR_BAR(0)) / 4;
1835 mask = ~(pi->pi_bar[idx].size - 1);
1836 switch (pi->pi_bar[idx].type) {
1838 pi->pi_bar[idx].addr = bar = 0;
1843 bar = addr | PCIM_BAR_IO_SPACE;
1845 * Register the new BAR value for interception
1847 if (addr != pi->pi_bar[idx].addr) {
1848 update_bar_address(pi, addr, idx,
1853 addr = bar = *eax & mask;
1854 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
1855 if (addr != pi->pi_bar[idx].addr) {
1856 update_bar_address(pi, addr, idx,
1861 addr = bar = *eax & mask;
1862 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
1863 PCIM_BAR_MEM_PREFETCH;
1864 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
1865 update_bar_address(pi, addr, idx,
1869 case PCIBAR_MEMHI64:
1870 mask = ~(pi->pi_bar[idx - 1].size - 1);
1871 addr = ((uint64_t)*eax << 32) & mask;
1873 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
1874 update_bar_address(pi, addr, idx - 1,
1881 pci_set_cfgdata32(pi, coff, bar);
1883 } else if (pci_emul_iscap(pi, coff)) {
1884 pci_emul_capwrite(pi, coff, bytes, *eax, 0, 0);
1885 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
1886 pci_emul_cmdsts_write(pi, coff, *eax, bytes);
1888 CFGWRITE(pi, coff, *eax, bytes);
1893 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
1896 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1897 uint32_t *eax, void *arg)
1903 *eax = (bytes == 2) ? 0xffff : 0xff;
1908 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
1914 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
1915 cfgoff = x & PCI_REGMAX;
1916 cfgfunc = (x >> 8) & PCI_FUNCMAX;
1917 cfgslot = (x >> 11) & PCI_SLOTMAX;
1918 cfgbus = (x >> 16) & PCI_BUSMAX;
1923 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
1926 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1927 uint32_t *eax, void *arg)
1931 assert(bytes == 1 || bytes == 2 || bytes == 4);
1933 coff = cfgoff + (port - CONF1_DATA_PORT);
1935 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
1938 /* Ignore accesses to cfgdata if not enabled by cfgaddr */
1945 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
1946 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
1947 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
1948 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
1950 #define PCI_EMUL_TEST
1951 #ifdef PCI_EMUL_TEST
1953 * Define a dummy test device
1957 struct pci_emul_dsoftc {
1958 uint8_t ioregs[DIOSZ];
1959 uint8_t memregs[2][DMEMSZ];
1962 #define PCI_EMUL_MSI_MSGS 4
1963 #define PCI_EMUL_MSIX_MSGS 16
1966 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1969 struct pci_emul_dsoftc *sc;
1971 sc = calloc(1, sizeof(struct pci_emul_dsoftc));
1975 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
1976 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
1977 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
1979 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
1982 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
1985 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
1988 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
1995 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1996 uint64_t offset, int size, uint64_t value)
1999 struct pci_emul_dsoftc *sc = pi->pi_arg;
2002 if (offset + size > DIOSZ) {
2003 printf("diow: iow too large, offset %ld size %d\n",
2009 sc->ioregs[offset] = value & 0xff;
2010 } else if (size == 2) {
2011 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
2012 } else if (size == 4) {
2013 *(uint32_t *)&sc->ioregs[offset] = value;
2015 printf("diow: iow unknown size %d\n", size);
2019 * Special magic value to generate an interrupt
2021 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2022 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2024 if (value == 0xabcdef) {
2025 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2026 pci_generate_msi(pi, i);
2030 if (baridx == 1 || baridx == 2) {
2031 if (offset + size > DMEMSZ) {
2032 printf("diow: memw too large, offset %ld size %d\n",
2037 i = baridx - 1; /* 'memregs' index */
2040 sc->memregs[i][offset] = value;
2041 } else if (size == 2) {
2042 *(uint16_t *)&sc->memregs[i][offset] = value;
2043 } else if (size == 4) {
2044 *(uint32_t *)&sc->memregs[i][offset] = value;
2045 } else if (size == 8) {
2046 *(uint64_t *)&sc->memregs[i][offset] = value;
2048 printf("diow: memw unknown size %d\n", size);
2052 * magic interrupt ??
2056 if (baridx > 2 || baridx < 0) {
2057 printf("diow: unknown bar idx %d\n", baridx);
2062 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2063 uint64_t offset, int size)
2065 struct pci_emul_dsoftc *sc = pi->pi_arg;
2070 if (offset + size > DIOSZ) {
2071 printf("dior: ior too large, offset %ld size %d\n",
2078 value = sc->ioregs[offset];
2079 } else if (size == 2) {
2080 value = *(uint16_t *) &sc->ioregs[offset];
2081 } else if (size == 4) {
2082 value = *(uint32_t *) &sc->ioregs[offset];
2084 printf("dior: ior unknown size %d\n", size);
2088 if (baridx == 1 || baridx == 2) {
2089 if (offset + size > DMEMSZ) {
2090 printf("dior: memr too large, offset %ld size %d\n",
2095 i = baridx - 1; /* 'memregs' index */
2098 value = sc->memregs[i][offset];
2099 } else if (size == 2) {
2100 value = *(uint16_t *) &sc->memregs[i][offset];
2101 } else if (size == 4) {
2102 value = *(uint32_t *) &sc->memregs[i][offset];
2103 } else if (size == 8) {
2104 value = *(uint64_t *) &sc->memregs[i][offset];
2106 printf("dior: ior unknown size %d\n", size);
2111 if (baridx > 2 || baridx < 0) {
2112 printf("dior: unknown bar idx %d\n", baridx);
2119 struct pci_devemu pci_dummy = {
2121 .pe_init = pci_emul_dinit,
2122 .pe_barwrite = pci_emul_diow,
2123 .pe_barread = pci_emul_dior
2125 PCI_EMUL_SET(pci_dummy);
2127 #endif /* PCI_EMUL_TEST */