2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/linker_set.h>
47 #include <machine/vmm.h>
59 #define CONF1_ADDR_PORT 0x0cf8
60 #define CONF1_DATA_PORT 0x0cfc
62 #define CONF1_ENABLE 0x80000000ul
64 #define MAXBUSES (PCI_BUSMAX + 1)
65 #define MAXSLOTS (PCI_SLOTMAX + 1)
66 #define MAXFUNCS (PCI_FUNCMAX + 1)
71 struct pci_devinst *fi_devi;
81 struct intxinfo si_intpins[4];
82 struct funcinfo si_funcs[MAXFUNCS];
86 uint16_t iobase, iolimit; /* I/O window */
87 uint32_t membase32, memlimit32; /* mmio window below 4GB */
88 uint64_t membase64, memlimit64; /* mmio window above 4GB */
89 struct slotinfo slotinfo[MAXSLOTS];
92 static struct businfo *pci_businfo[MAXBUSES];
94 SET_DECLARE(pci_devemu_set, struct pci_devemu);
96 static uint64_t pci_emul_iobase;
97 static uint64_t pci_emul_membase32;
98 static uint64_t pci_emul_membase64;
100 #define PCI_EMUL_IOBASE 0x2000
101 #define PCI_EMUL_IOLIMIT 0x10000
103 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
104 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
105 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
107 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
109 #define PCI_EMUL_MEMBASE64 0xD000000000UL
110 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
112 static struct pci_devemu *pci_emul_finddev(char *name);
113 static void pci_lintr_route(struct pci_devinst *pi);
114 static void pci_lintr_update(struct pci_devinst *pi);
115 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
116 int func, int coff, int bytes, uint32_t *val);
119 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
123 pci_set_cfgdata8(pi, coff, val);
125 pci_set_cfgdata16(pi, coff, val);
127 pci_set_cfgdata32(pi, coff, val);
130 static __inline uint32_t
131 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
135 return (pci_get_cfgdata8(pi, coff));
137 return (pci_get_cfgdata16(pi, coff));
139 return (pci_get_cfgdata32(pi, coff));
147 * Slot options are in the form:
149 * <bus>:<slot>:<func>,<emul>[,<config>]
150 * <slot>[:<func>],<emul>[,<config>]
154 * emul is a string describing the type of PCI device e.g. virtio-net
155 * config is an optional string, depending on the device, that can be
156 * used for configuration.
162 pci_parse_slot_usage(char *aopt)
165 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt);
169 pci_parse_slot(char *opt)
173 char *emul, *config, *str, *cp;
174 int error, bnum, snum, fnum;
179 emul = config = NULL;
180 if ((cp = strchr(str, ',')) != NULL) {
183 if ((cp = strchr(emul, ',')) != NULL) {
188 pci_parse_slot_usage(opt);
192 /* <bus>:<slot>:<func> */
193 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
196 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
199 if (sscanf(str, "%d", &snum) != 1) {
205 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
206 fnum < 0 || fnum >= MAXFUNCS) {
207 pci_parse_slot_usage(opt);
211 if (pci_businfo[bnum] == NULL)
212 pci_businfo[bnum] = calloc(1, sizeof(struct businfo));
214 bi = pci_businfo[bnum];
215 si = &bi->slotinfo[snum];
217 if (si->si_funcs[fnum].fi_name != NULL) {
218 fprintf(stderr, "pci slot %d:%d already occupied!\n",
223 if (pci_emul_finddev(emul) == NULL) {
224 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n",
230 si->si_funcs[fnum].fi_name = emul;
231 si->si_funcs[fnum].fi_param = config;
241 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
244 if (offset < pi->pi_msix.pba_offset)
247 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
255 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
258 int msix_entry_offset;
262 /* support only 4 or 8 byte writes */
263 if (size != 4 && size != 8)
267 * Return if table index is beyond what device supports
269 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
270 if (tab_index >= pi->pi_msix.table_count)
273 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
275 /* support only aligned writes */
276 if ((msix_entry_offset % size) != 0)
279 dest = (char *)(pi->pi_msix.table + tab_index);
280 dest += msix_entry_offset;
283 *((uint32_t *)dest) = value;
285 *((uint64_t *)dest) = value;
291 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
294 int msix_entry_offset;
296 uint64_t retval = ~0;
299 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
300 * table but we also allow 1 byte access to accommodate reads from
303 if (size != 1 && size != 4 && size != 8)
306 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
308 /* support only aligned reads */
309 if ((msix_entry_offset % size) != 0) {
313 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
315 if (tab_index < pi->pi_msix.table_count) {
316 /* valid MSI-X Table access */
317 dest = (char *)(pi->pi_msix.table + tab_index);
318 dest += msix_entry_offset;
321 retval = *((uint8_t *)dest);
323 retval = *((uint32_t *)dest);
325 retval = *((uint64_t *)dest);
326 } else if (pci_valid_pba_offset(pi, offset)) {
327 /* return 0 for PBA access */
335 pci_msix_table_bar(struct pci_devinst *pi)
338 if (pi->pi_msix.table != NULL)
339 return (pi->pi_msix.table_bar);
345 pci_msix_pba_bar(struct pci_devinst *pi)
348 if (pi->pi_msix.table != NULL)
349 return (pi->pi_msix.pba_bar);
355 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
356 uint32_t *eax, void *arg)
358 struct pci_devinst *pdi = arg;
359 struct pci_devemu *pe = pdi->pi_d;
363 for (i = 0; i <= PCI_BARMAX; i++) {
364 if (pdi->pi_bar[i].type == PCIBAR_IO &&
365 port >= pdi->pi_bar[i].addr &&
366 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
367 offset = port - pdi->pi_bar[i].addr;
369 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
372 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
381 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
382 int size, uint64_t *val, void *arg1, long arg2)
384 struct pci_devinst *pdi = arg1;
385 struct pci_devemu *pe = pdi->pi_d;
387 int bidx = (int) arg2;
389 assert(bidx <= PCI_BARMAX);
390 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
391 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
392 assert(addr >= pdi->pi_bar[bidx].addr &&
393 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
395 offset = addr - pdi->pi_bar[bidx].addr;
397 if (dir == MEM_F_WRITE) {
399 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
400 4, *val & 0xffffffff);
401 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
404 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
409 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
411 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
412 offset + 4, 4) << 32;
414 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
424 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
429 assert((size & (size - 1)) == 0); /* must be a power of 2 */
431 base = roundup2(*baseptr, size);
433 if (base + size <= limit) {
435 *baseptr = base + size;
442 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
446 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size));
450 * Register (or unregister) the MMIO or I/O region associated with the BAR
451 * register 'idx' of an emulated pci device.
454 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
457 struct inout_port iop;
460 switch (pi->pi_bar[idx].type) {
462 bzero(&iop, sizeof(struct inout_port));
463 iop.name = pi->pi_name;
464 iop.port = pi->pi_bar[idx].addr;
465 iop.size = pi->pi_bar[idx].size;
467 iop.flags = IOPORT_F_INOUT;
468 iop.handler = pci_emul_io_handler;
470 error = register_inout(&iop);
472 error = unregister_inout(&iop);
476 bzero(&mr, sizeof(struct mem_range));
477 mr.name = pi->pi_name;
478 mr.base = pi->pi_bar[idx].addr;
479 mr.size = pi->pi_bar[idx].size;
482 mr.handler = pci_emul_mem_handler;
485 error = register_mem(&mr);
487 error = unregister_mem(&mr);
497 unregister_bar(struct pci_devinst *pi, int idx)
500 modify_bar_registration(pi, idx, 0);
504 register_bar(struct pci_devinst *pi, int idx)
507 modify_bar_registration(pi, idx, 1);
510 /* Are we decoding i/o port accesses for the emulated pci device? */
512 porten(struct pci_devinst *pi)
516 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
518 return (cmd & PCIM_CMD_PORTEN);
521 /* Are we decoding memory accesses for the emulated pci device? */
523 memen(struct pci_devinst *pi)
527 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
529 return (cmd & PCIM_CMD_MEMEN);
533 * Update the MMIO or I/O address that is decoded by the BAR register.
535 * If the pci device has enabled the address space decoding then intercept
536 * the address range decoded by the BAR register.
539 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
543 if (pi->pi_bar[idx].type == PCIBAR_IO)
549 unregister_bar(pi, idx);
554 pi->pi_bar[idx].addr = addr;
557 pi->pi_bar[idx].addr &= ~0xffffffffUL;
558 pi->pi_bar[idx].addr |= addr;
561 pi->pi_bar[idx].addr &= 0xffffffff;
562 pi->pi_bar[idx].addr |= addr;
569 register_bar(pi, idx);
573 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
574 enum pcibar_type type, uint64_t size)
577 uint64_t *baseptr, limit, addr, mask, lobits, bar;
579 assert(idx >= 0 && idx <= PCI_BARMAX);
581 if ((size & (size - 1)) != 0)
582 size = 1UL << flsl(size); /* round up to a power of 2 */
584 /* Enforce minimum BAR sizes required by the PCI standard */
585 if (type == PCIBAR_IO) {
596 addr = mask = lobits = 0;
599 baseptr = &pci_emul_iobase;
600 limit = PCI_EMUL_IOLIMIT;
601 mask = PCIM_BAR_IO_BASE;
602 lobits = PCIM_BAR_IO_SPACE;
607 * Some drivers do not work well if the 64-bit BAR is allocated
608 * above 4GB. Allow for this by allocating small requests under
609 * 4GB unless then allocation size is larger than some arbitrary
610 * number (32MB currently).
612 if (size > 32 * 1024 * 1024) {
614 * XXX special case for device requiring peer-peer DMA
616 if (size == 0x100000000UL)
619 baseptr = &pci_emul_membase64;
620 limit = PCI_EMUL_MEMLIMIT64;
621 mask = PCIM_BAR_MEM_BASE;
622 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
623 PCIM_BAR_MEM_PREFETCH;
626 baseptr = &pci_emul_membase32;
627 limit = PCI_EMUL_MEMLIMIT32;
628 mask = PCIM_BAR_MEM_BASE;
629 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
633 baseptr = &pci_emul_membase32;
634 limit = PCI_EMUL_MEMLIMIT32;
635 mask = PCIM_BAR_MEM_BASE;
636 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
639 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
643 if (baseptr != NULL) {
644 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
649 pdi->pi_bar[idx].type = type;
650 pdi->pi_bar[idx].addr = addr;
651 pdi->pi_bar[idx].size = size;
653 /* Initialize the BAR register in config space */
654 bar = (addr & mask) | lobits;
655 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
657 if (type == PCIBAR_MEM64) {
658 assert(idx + 1 <= PCI_BARMAX);
659 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
660 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
663 register_bar(pdi, idx);
668 #define CAP_START_OFFSET 0x40
670 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
672 int i, capoff, reallen;
677 reallen = roundup2(caplen, 4); /* dword aligned */
679 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
680 if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
681 capoff = CAP_START_OFFSET;
683 capoff = pi->pi_capend + 1;
685 /* Check if we have enough space */
686 if (capoff + reallen > PCI_REGMAX + 1)
689 /* Set the previous capability pointer */
690 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
691 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
692 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
694 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
696 /* Copy the capability */
697 for (i = 0; i < caplen; i++)
698 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
700 /* Set the next capability pointer */
701 pci_set_cfgdata8(pi, capoff + 1, 0);
703 pi->pi_prevcap = capoff;
704 pi->pi_capend = capoff + reallen - 1;
708 static struct pci_devemu *
709 pci_emul_finddev(char *name)
711 struct pci_devemu **pdpp, *pdp;
713 SET_FOREACH(pdpp, pci_devemu_set) {
715 if (!strcmp(pdp->pe_emu, name)) {
724 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
725 int func, struct funcinfo *fi)
727 struct pci_devinst *pdi;
730 pdi = calloc(1, sizeof(struct pci_devinst));
736 pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
737 pdi->pi_lintr.pin = 0;
738 pdi->pi_lintr.state = IDLE;
739 pdi->pi_lintr.pirq_pin = 0;
740 pdi->pi_lintr.ioapic_irq = 0;
742 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
744 /* Disable legacy interrupts */
745 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
746 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
748 pci_set_cfgdata8(pdi, PCIR_COMMAND,
749 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
751 err = (*pde->pe_init)(ctx, pdi, fi->fi_param);
761 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
765 /* Number of msi messages must be a power of 2 between 1 and 32 */
766 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
767 mmc = ffs(msgnum) - 1;
769 bzero(msicap, sizeof(struct msicap));
770 msicap->capid = PCIY_MSI;
771 msicap->nextptr = nextptr;
772 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
776 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
778 struct msicap msicap;
780 pci_populate_msicap(&msicap, msgnum, 0);
782 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
786 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
787 uint32_t msix_tab_size)
790 assert(msix_tab_size % 4096 == 0);
792 bzero(msixcap, sizeof(struct msixcap));
793 msixcap->capid = PCIY_MSIX;
796 * Message Control Register, all fields set to
797 * zero except for the Table Size.
798 * Note: Table size N is encoded as N-1
800 msixcap->msgctrl = msgnum - 1;
804 * - MSI-X table start at offset 0
805 * - PBA table starts at a 4K aligned offset after the MSI-X table
807 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
808 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
812 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
816 assert(table_entries > 0);
817 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
819 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
820 pi->pi_msix.table = calloc(1, table_size);
822 /* set mask bit of vector control register */
823 for (i = 0; i < table_entries; i++)
824 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
828 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
831 struct msixcap msixcap;
833 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
834 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
836 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
838 /* Align table size to nearest 4K */
839 tab_size = roundup2(tab_size, 4096);
841 pi->pi_msix.table_bar = barnum;
842 pi->pi_msix.pba_bar = barnum;
843 pi->pi_msix.table_offset = 0;
844 pi->pi_msix.table_count = msgnum;
845 pi->pi_msix.pba_offset = tab_size;
846 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
848 pci_msix_table_init(pi, msgnum);
850 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
852 /* allocate memory for MSI-X Table and PBA */
853 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
854 tab_size + pi->pi_msix.pba_size);
856 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
861 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
862 int bytes, uint32_t val)
864 uint16_t msgctrl, rwmask;
867 off = offset - capoff;
868 /* Message Control Register */
869 if (off == 2 && bytes == 2) {
870 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
871 msgctrl = pci_get_cfgdata16(pi, offset);
873 msgctrl |= val & rwmask;
876 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
877 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
878 pci_lintr_update(pi);
881 CFGWRITE(pi, offset, val, bytes);
885 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
886 int bytes, uint32_t val)
888 uint16_t msgctrl, rwmask, msgdata, mme;
892 * If guest is writing to the message control register make sure
893 * we do not overwrite read-only fields.
895 if ((offset - capoff) == 2 && bytes == 2) {
896 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
897 msgctrl = pci_get_cfgdata16(pi, offset);
899 msgctrl |= val & rwmask;
902 addrlo = pci_get_cfgdata32(pi, capoff + 4);
903 if (msgctrl & PCIM_MSICTRL_64BIT)
904 msgdata = pci_get_cfgdata16(pi, capoff + 12);
906 msgdata = pci_get_cfgdata16(pi, capoff + 8);
908 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
909 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
910 if (pi->pi_msi.enabled) {
911 pi->pi_msi.addr = addrlo;
912 pi->pi_msi.msg_data = msgdata;
913 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
915 pi->pi_msi.maxmsgnum = 0;
917 pci_lintr_update(pi);
920 CFGWRITE(pi, offset, val, bytes);
924 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
925 int bytes, uint32_t val)
928 /* XXX don't write to the readonly parts */
929 CFGWRITE(pi, offset, val, bytes);
932 #define PCIECAP_VERSION 0x2
934 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
937 struct pciecap pciecap;
939 if (type != PCIEM_TYPE_ROOT_PORT)
942 bzero(&pciecap, sizeof(pciecap));
944 pciecap.capid = PCIY_EXPRESS;
945 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT;
946 pciecap.link_capabilities = 0x411; /* gen1, x1 */
947 pciecap.link_status = 0x11; /* gen1, x1 */
949 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
954 * This function assumes that 'coff' is in the capabilities region of the
958 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val)
961 uint8_t capoff, nextoff;
963 /* Do not allow un-aligned writes */
964 if ((offset & (bytes - 1)) != 0)
967 /* Find the capability that we want to update */
968 capoff = CAP_START_OFFSET;
970 nextoff = pci_get_cfgdata8(pi, capoff + 1);
973 if (offset >= capoff && offset < nextoff)
978 assert(offset >= capoff);
981 * Capability ID and Next Capability Pointer are readonly.
982 * However, some o/s's do 4-byte writes that include these.
983 * For this case, trim the write back to 2 bytes and adjust
986 if (offset == capoff || offset == capoff + 1) {
987 if (offset == capoff && bytes == 4) {
995 capid = pci_get_cfgdata8(pi, capoff);
998 msicap_cfgwrite(pi, capoff, offset, bytes, val);
1001 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1004 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1012 pci_emul_iscap(struct pci_devinst *pi, int offset)
1016 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1017 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1018 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1025 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1026 int size, uint64_t *val, void *arg1, long arg2)
1029 * Ignore writes; return 0xff's for reads. The mem read code
1030 * will take care of truncating to the correct size.
1032 if (dir == MEM_F_READ) {
1033 *val = 0xffffffffffffffff;
1040 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1041 int bytes, uint64_t *val, void *arg1, long arg2)
1043 int bus, slot, func, coff, in;
1045 coff = addr & 0xfff;
1046 func = (addr >> 12) & 0x7;
1047 slot = (addr >> 15) & 0x1f;
1048 bus = (addr >> 20) & 0xff;
1049 in = (dir == MEM_F_READ);
1052 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val);
1060 return (PCI_EMUL_ECFG_BASE);
1063 #define BUSIO_ROUNDUP 32
1064 #define BUSMEM_ROUNDUP (1024 * 1024)
1067 init_pci(struct vmctx *ctx)
1069 struct mem_range mr;
1070 struct pci_devemu *pde;
1072 struct slotinfo *si;
1073 struct funcinfo *fi;
1075 int bus, slot, func;
1078 pci_emul_iobase = PCI_EMUL_IOBASE;
1079 pci_emul_membase32 = vm_get_lowmem_limit(ctx);
1080 pci_emul_membase64 = PCI_EMUL_MEMBASE64;
1082 for (bus = 0; bus < MAXBUSES; bus++) {
1083 if ((bi = pci_businfo[bus]) == NULL)
1086 * Keep track of the i/o and memory resources allocated to
1089 bi->iobase = pci_emul_iobase;
1090 bi->membase32 = pci_emul_membase32;
1091 bi->membase64 = pci_emul_membase64;
1093 for (slot = 0; slot < MAXSLOTS; slot++) {
1094 si = &bi->slotinfo[slot];
1095 for (func = 0; func < MAXFUNCS; func++) {
1096 fi = &si->si_funcs[func];
1097 if (fi->fi_name == NULL)
1099 pde = pci_emul_finddev(fi->fi_name);
1100 assert(pde != NULL);
1101 error = pci_emul_init(ctx, pde, bus, slot,
1109 * Add some slop to the I/O and memory resources decoded by
1110 * this bus to give a guest some flexibility if it wants to
1111 * reprogram the BARs.
1113 pci_emul_iobase += BUSIO_ROUNDUP;
1114 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1115 bi->iolimit = pci_emul_iobase;
1117 pci_emul_membase32 += BUSMEM_ROUNDUP;
1118 pci_emul_membase32 = roundup2(pci_emul_membase32,
1120 bi->memlimit32 = pci_emul_membase32;
1122 pci_emul_membase64 += BUSMEM_ROUNDUP;
1123 pci_emul_membase64 = roundup2(pci_emul_membase64,
1125 bi->memlimit64 = pci_emul_membase64;
1129 * PCI backends are initialized before routing INTx interrupts
1130 * so that LPC devices are able to reserve ISA IRQs before
1131 * routing PIRQ pins.
1133 for (bus = 0; bus < MAXBUSES; bus++) {
1134 if ((bi = pci_businfo[bus]) == NULL)
1137 for (slot = 0; slot < MAXSLOTS; slot++) {
1138 si = &bi->slotinfo[slot];
1139 for (func = 0; func < MAXFUNCS; func++) {
1140 fi = &si->si_funcs[func];
1141 if (fi->fi_devi == NULL)
1143 pci_lintr_route(fi->fi_devi);
1150 * The guest physical memory map looks like the following:
1151 * [0, lowmem) guest system memory
1152 * [lowmem, lowmem_limit) memory hole (may be absent)
1153 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation)
1154 * [0xE0000000, 0xF0000000) PCI extended config window
1155 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
1156 * [4GB, 4GB + highmem)
1160 * Accesses to memory addresses that are not allocated to system
1161 * memory or PCI devices return 0xff's.
1163 lowmem = vm_get_lowmem_size(ctx);
1164 bzero(&mr, sizeof(struct mem_range));
1165 mr.name = "PCI hole";
1166 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1168 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1169 mr.handler = pci_emul_fallback_handler;
1170 error = register_mem_fallback(&mr);
1173 /* PCI extended config space */
1174 bzero(&mr, sizeof(struct mem_range));
1175 mr.name = "PCI ECFG";
1176 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1177 mr.base = PCI_EMUL_ECFG_BASE;
1178 mr.size = PCI_EMUL_ECFG_SIZE;
1179 mr.handler = pci_emul_ecfg_handler;
1180 error = register_mem(&mr);
1187 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1191 dsdt_line(" Package ()");
1193 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1194 dsdt_line(" 0x%02X,", pin - 1);
1195 dsdt_line(" Zero,");
1196 dsdt_line(" 0x%X", ioapic_irq);
1201 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1206 name = lpc_pirq_name(pirq_pin);
1209 dsdt_line(" Package ()");
1211 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1212 dsdt_line(" 0x%02X,", pin - 1);
1213 dsdt_line(" %s,", name);
1220 * A bhyve virtual machine has a flat PCI hierarchy with a root port
1221 * corresponding to each PCI bus.
1224 pci_bus_write_dsdt(int bus)
1227 struct slotinfo *si;
1228 struct pci_devinst *pi;
1229 int count, func, slot;
1232 * If there are no devices on this 'bus' then just return.
1234 if ((bi = pci_businfo[bus]) == NULL) {
1236 * Bus 0 is special because it decodes the I/O ports used
1237 * for PCI config space access even if there are no devices
1244 dsdt_line(" Device (PC%02X)", bus);
1246 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))");
1247 dsdt_line(" Name (_ADR, Zero)");
1249 dsdt_line(" Method (_BBN, 0, NotSerialized)");
1251 dsdt_line(" Return (0x%08X)", bus);
1253 dsdt_line(" Name (_CRS, ResourceTemplate ()");
1255 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, "
1256 "MaxFixed, PosDecode,");
1257 dsdt_line(" 0x0000, // Granularity");
1258 dsdt_line(" 0x%04X, // Range Minimum", bus);
1259 dsdt_line(" 0x%04X, // Range Maximum", bus);
1260 dsdt_line(" 0x0000, // Translation Offset");
1261 dsdt_line(" 0x0001, // Length");
1266 dsdt_fixed_ioport(0xCF8, 8);
1269 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1270 "PosDecode, EntireRange,");
1271 dsdt_line(" 0x0000, // Granularity");
1272 dsdt_line(" 0x0000, // Range Minimum");
1273 dsdt_line(" 0x0CF7, // Range Maximum");
1274 dsdt_line(" 0x0000, // Translation Offset");
1275 dsdt_line(" 0x0CF8, // Length");
1276 dsdt_line(" ,, , TypeStatic)");
1278 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1279 "PosDecode, EntireRange,");
1280 dsdt_line(" 0x0000, // Granularity");
1281 dsdt_line(" 0x0D00, // Range Minimum");
1282 dsdt_line(" 0x%04X, // Range Maximum",
1283 PCI_EMUL_IOBASE - 1);
1284 dsdt_line(" 0x0000, // Translation Offset");
1285 dsdt_line(" 0x%04X, // Length",
1286 PCI_EMUL_IOBASE - 0x0D00);
1287 dsdt_line(" ,, , TypeStatic)");
1297 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1298 "PosDecode, EntireRange,");
1299 dsdt_line(" 0x0000, // Granularity");
1300 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase);
1301 dsdt_line(" 0x%04X, // Range Maximum",
1303 dsdt_line(" 0x0000, // Translation Offset");
1304 dsdt_line(" 0x%04X, // Length",
1305 bi->iolimit - bi->iobase);
1306 dsdt_line(" ,, , TypeStatic)");
1308 /* mmio window (32-bit) */
1309 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, "
1310 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1311 dsdt_line(" 0x00000000, // Granularity");
1312 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32);
1313 dsdt_line(" 0x%08X, // Range Maximum\n",
1314 bi->memlimit32 - 1);
1315 dsdt_line(" 0x00000000, // Translation Offset");
1316 dsdt_line(" 0x%08X, // Length\n",
1317 bi->memlimit32 - bi->membase32);
1318 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1320 /* mmio window (64-bit) */
1321 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, "
1322 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1323 dsdt_line(" 0x0000000000000000, // Granularity");
1324 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64);
1325 dsdt_line(" 0x%016lX, // Range Maximum\n",
1326 bi->memlimit64 - 1);
1327 dsdt_line(" 0x0000000000000000, // Translation Offset");
1328 dsdt_line(" 0x%016lX, // Length\n",
1329 bi->memlimit64 - bi->membase64);
1330 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1333 count = pci_count_lintr(bus);
1336 dsdt_line("Name (PPRT, Package ()");
1338 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1340 dsdt_line("Name (APRT, Package ()");
1342 pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1344 dsdt_line("Method (_PRT, 0, NotSerialized)");
1346 dsdt_line(" If (PICM)");
1348 dsdt_line(" Return (APRT)");
1352 dsdt_line(" Return (PPRT)");
1359 for (slot = 0; slot < MAXSLOTS; slot++) {
1360 si = &bi->slotinfo[slot];
1361 for (func = 0; func < MAXFUNCS; func++) {
1362 pi = si->si_funcs[func].fi_devi;
1363 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1364 pi->pi_d->pe_write_dsdt(pi);
1373 pci_write_dsdt(void)
1378 dsdt_line("Name (PICM, 0x00)");
1379 dsdt_line("Method (_PIC, 1, NotSerialized)");
1381 dsdt_line(" Store (Arg0, PICM)");
1384 dsdt_line("Scope (_SB)");
1386 for (bus = 0; bus < MAXBUSES; bus++)
1387 pci_bus_write_dsdt(bus);
1393 pci_bus_configured(int bus)
1395 assert(bus >= 0 && bus < MAXBUSES);
1396 return (pci_businfo[bus] != NULL);
1400 pci_msi_enabled(struct pci_devinst *pi)
1402 return (pi->pi_msi.enabled);
1406 pci_msi_maxmsgnum(struct pci_devinst *pi)
1408 if (pi->pi_msi.enabled)
1409 return (pi->pi_msi.maxmsgnum);
1415 pci_msix_enabled(struct pci_devinst *pi)
1418 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1422 pci_generate_msix(struct pci_devinst *pi, int index)
1424 struct msix_table_entry *mte;
1426 if (!pci_msix_enabled(pi))
1429 if (pi->pi_msix.function_mask)
1432 if (index >= pi->pi_msix.table_count)
1435 mte = &pi->pi_msix.table[index];
1436 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1437 /* XXX Set PBA bit if interrupt is disabled */
1438 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1443 pci_generate_msi(struct pci_devinst *pi, int index)
1446 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1447 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1448 pi->pi_msi.msg_data + index);
1453 pci_lintr_permitted(struct pci_devinst *pi)
1457 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1458 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1459 (cmd & PCIM_CMD_INTxDIS)));
1463 pci_lintr_request(struct pci_devinst *pi)
1466 struct slotinfo *si;
1467 int bestpin, bestcount, pin;
1469 bi = pci_businfo[pi->pi_bus];
1473 * Just allocate a pin from our slot. The pin will be
1474 * assigned IRQs later when interrupts are routed.
1476 si = &bi->slotinfo[pi->pi_slot];
1478 bestcount = si->si_intpins[0].ii_count;
1479 for (pin = 1; pin < 4; pin++) {
1480 if (si->si_intpins[pin].ii_count < bestcount) {
1482 bestcount = si->si_intpins[pin].ii_count;
1486 si->si_intpins[bestpin].ii_count++;
1487 pi->pi_lintr.pin = bestpin + 1;
1488 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1492 pci_lintr_route(struct pci_devinst *pi)
1495 struct intxinfo *ii;
1497 if (pi->pi_lintr.pin == 0)
1500 bi = pci_businfo[pi->pi_bus];
1502 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1505 * Attempt to allocate an I/O APIC pin for this intpin if one
1506 * is not yet assigned.
1508 if (ii->ii_ioapic_irq == 0)
1509 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi);
1510 assert(ii->ii_ioapic_irq > 0);
1513 * Attempt to allocate a PIRQ pin for this intpin if one is
1516 if (ii->ii_pirq_pin == 0)
1517 ii->ii_pirq_pin = pirq_alloc_pin(pi);
1518 assert(ii->ii_pirq_pin > 0);
1520 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1521 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1522 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1526 pci_lintr_assert(struct pci_devinst *pi)
1529 assert(pi->pi_lintr.pin > 0);
1531 pthread_mutex_lock(&pi->pi_lintr.lock);
1532 if (pi->pi_lintr.state == IDLE) {
1533 if (pci_lintr_permitted(pi)) {
1534 pi->pi_lintr.state = ASSERTED;
1537 pi->pi_lintr.state = PENDING;
1539 pthread_mutex_unlock(&pi->pi_lintr.lock);
1543 pci_lintr_deassert(struct pci_devinst *pi)
1546 assert(pi->pi_lintr.pin > 0);
1548 pthread_mutex_lock(&pi->pi_lintr.lock);
1549 if (pi->pi_lintr.state == ASSERTED) {
1550 pi->pi_lintr.state = IDLE;
1551 pci_irq_deassert(pi);
1552 } else if (pi->pi_lintr.state == PENDING)
1553 pi->pi_lintr.state = IDLE;
1554 pthread_mutex_unlock(&pi->pi_lintr.lock);
1558 pci_lintr_update(struct pci_devinst *pi)
1561 pthread_mutex_lock(&pi->pi_lintr.lock);
1562 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1563 pci_irq_deassert(pi);
1564 pi->pi_lintr.state = PENDING;
1565 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1566 pi->pi_lintr.state = ASSERTED;
1569 pthread_mutex_unlock(&pi->pi_lintr.lock);
1573 pci_count_lintr(int bus)
1575 int count, slot, pin;
1576 struct slotinfo *slotinfo;
1579 if (pci_businfo[bus] != NULL) {
1580 for (slot = 0; slot < MAXSLOTS; slot++) {
1581 slotinfo = &pci_businfo[bus]->slotinfo[slot];
1582 for (pin = 0; pin < 4; pin++) {
1583 if (slotinfo->si_intpins[pin].ii_count != 0)
1592 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
1595 struct slotinfo *si;
1596 struct intxinfo *ii;
1599 if ((bi = pci_businfo[bus]) == NULL)
1602 for (slot = 0; slot < MAXSLOTS; slot++) {
1603 si = &bi->slotinfo[slot];
1604 for (pin = 0; pin < 4; pin++) {
1605 ii = &si->si_intpins[pin];
1606 if (ii->ii_count != 0)
1607 cb(bus, slot, pin + 1, ii->ii_pirq_pin,
1608 ii->ii_ioapic_irq, arg);
1614 * Return 1 if the emulated device in 'slot' is a multi-function device.
1615 * Return 0 otherwise.
1618 pci_emul_is_mfdev(int bus, int slot)
1621 struct slotinfo *si;
1625 if ((bi = pci_businfo[bus]) != NULL) {
1626 si = &bi->slotinfo[slot];
1627 for (f = 0; f < MAXFUNCS; f++) {
1628 if (si->si_funcs[f].fi_devi != NULL) {
1633 return (numfuncs > 1);
1637 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1638 * whether or not is a multi-function being emulated in the pci 'slot'.
1641 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
1645 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1646 mfdev = pci_emul_is_mfdev(bus, slot);
1656 *rv &= ~(PCIM_MFDEV << 16);
1658 *rv |= (PCIM_MFDEV << 16);
1666 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
1669 uint32_t cmd, cmd2, changed, old, readonly;
1671 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
1674 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3.
1676 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are
1677 * 'write 1 to clear'. However these bits are not set to '1' by
1678 * any device emulation so it is simpler to treat them as readonly.
1680 rshift = (coff & 0x3) * 8;
1681 readonly = 0xFFFFF880 >> rshift;
1683 old = CFGREAD(pi, coff, bytes);
1685 new |= (old & readonly);
1686 CFGWRITE(pi, coff, new, bytes); /* update config */
1688 cmd2 = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */
1689 changed = cmd ^ cmd2;
1692 * If the MMIO or I/O address space decoding has changed then
1693 * register/unregister all BARs that decode that address space.
1695 for (i = 0; i <= PCI_BARMAX; i++) {
1696 switch (pi->pi_bar[i].type) {
1698 case PCIBAR_MEMHI64:
1701 /* I/O address space decoding changed? */
1702 if (changed & PCIM_CMD_PORTEN) {
1704 register_bar(pi, i);
1706 unregister_bar(pi, i);
1711 /* MMIO address space decoding changed? */
1712 if (changed & PCIM_CMD_MEMEN) {
1714 register_bar(pi, i);
1716 unregister_bar(pi, i);
1725 * If INTx has been unmasked and is pending, assert the
1728 pci_lintr_update(pi);
1732 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
1733 int coff, int bytes, uint32_t *eax)
1736 struct slotinfo *si;
1737 struct pci_devinst *pi;
1738 struct pci_devemu *pe;
1740 uint64_t addr, bar, mask;
1742 if ((bi = pci_businfo[bus]) != NULL) {
1743 si = &bi->slotinfo[slot];
1744 pi = si->si_funcs[func].fi_devi;
1749 * Just return if there is no device at this slot:func or if the
1750 * the guest is doing an un-aligned access.
1752 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
1753 (coff & (bytes - 1)) != 0) {
1760 * Ignore all writes beyond the standard config space and return all
1763 if (coff >= PCI_REGMAX + 1) {
1767 * Extended capabilities begin at offset 256 in config
1768 * space. Absence of extended capabilities is signaled
1769 * with all 0s in the extended capability header at
1772 if (coff <= PCI_REGMAX + 4)
1784 /* Let the device emulation override the default handler */
1785 if (pe->pe_cfgread != NULL) {
1786 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes,
1793 *eax = CFGREAD(pi, coff, bytes);
1795 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
1797 /* Let the device emulation override the default handler */
1798 if (pe->pe_cfgwrite != NULL &&
1799 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
1803 * Special handling for write to BAR registers
1805 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) {
1807 * Ignore writes to BAR registers that are not
1810 if (bytes != 4 || (coff & 0x3) != 0)
1812 idx = (coff - PCIR_BAR(0)) / 4;
1813 mask = ~(pi->pi_bar[idx].size - 1);
1814 switch (pi->pi_bar[idx].type) {
1816 pi->pi_bar[idx].addr = bar = 0;
1821 bar = addr | PCIM_BAR_IO_SPACE;
1823 * Register the new BAR value for interception
1825 if (addr != pi->pi_bar[idx].addr) {
1826 update_bar_address(pi, addr, idx,
1831 addr = bar = *eax & mask;
1832 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
1833 if (addr != pi->pi_bar[idx].addr) {
1834 update_bar_address(pi, addr, idx,
1839 addr = bar = *eax & mask;
1840 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
1841 PCIM_BAR_MEM_PREFETCH;
1842 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
1843 update_bar_address(pi, addr, idx,
1847 case PCIBAR_MEMHI64:
1848 mask = ~(pi->pi_bar[idx - 1].size - 1);
1849 addr = ((uint64_t)*eax << 32) & mask;
1851 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
1852 update_bar_address(pi, addr, idx - 1,
1859 pci_set_cfgdata32(pi, coff, bar);
1861 } else if (pci_emul_iscap(pi, coff)) {
1862 pci_emul_capwrite(pi, coff, bytes, *eax);
1863 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
1864 pci_emul_cmdsts_write(pi, coff, *eax, bytes);
1866 CFGWRITE(pi, coff, *eax, bytes);
1871 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
1874 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1875 uint32_t *eax, void *arg)
1881 *eax = (bytes == 2) ? 0xffff : 0xff;
1886 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
1892 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
1893 cfgoff = x & PCI_REGMAX;
1894 cfgfunc = (x >> 8) & PCI_FUNCMAX;
1895 cfgslot = (x >> 11) & PCI_SLOTMAX;
1896 cfgbus = (x >> 16) & PCI_BUSMAX;
1901 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
1904 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1905 uint32_t *eax, void *arg)
1909 assert(bytes == 1 || bytes == 2 || bytes == 4);
1911 coff = cfgoff + (port - CONF1_DATA_PORT);
1913 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
1916 /* Ignore accesses to cfgdata if not enabled by cfgaddr */
1923 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
1924 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
1925 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
1926 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
1928 #define PCI_EMUL_TEST
1929 #ifdef PCI_EMUL_TEST
1931 * Define a dummy test device
1935 struct pci_emul_dsoftc {
1936 uint8_t ioregs[DIOSZ];
1937 uint8_t memregs[2][DMEMSZ];
1940 #define PCI_EMUL_MSI_MSGS 4
1941 #define PCI_EMUL_MSIX_MSGS 16
1944 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1947 struct pci_emul_dsoftc *sc;
1949 sc = calloc(1, sizeof(struct pci_emul_dsoftc));
1953 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
1954 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
1955 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
1957 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
1960 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
1963 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
1966 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
1973 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1974 uint64_t offset, int size, uint64_t value)
1977 struct pci_emul_dsoftc *sc = pi->pi_arg;
1980 if (offset + size > DIOSZ) {
1981 printf("diow: iow too large, offset %ld size %d\n",
1987 sc->ioregs[offset] = value & 0xff;
1988 } else if (size == 2) {
1989 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
1990 } else if (size == 4) {
1991 *(uint32_t *)&sc->ioregs[offset] = value;
1993 printf("diow: iow unknown size %d\n", size);
1997 * Special magic value to generate an interrupt
1999 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2000 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2002 if (value == 0xabcdef) {
2003 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2004 pci_generate_msi(pi, i);
2008 if (baridx == 1 || baridx == 2) {
2009 if (offset + size > DMEMSZ) {
2010 printf("diow: memw too large, offset %ld size %d\n",
2015 i = baridx - 1; /* 'memregs' index */
2018 sc->memregs[i][offset] = value;
2019 } else if (size == 2) {
2020 *(uint16_t *)&sc->memregs[i][offset] = value;
2021 } else if (size == 4) {
2022 *(uint32_t *)&sc->memregs[i][offset] = value;
2023 } else if (size == 8) {
2024 *(uint64_t *)&sc->memregs[i][offset] = value;
2026 printf("diow: memw unknown size %d\n", size);
2030 * magic interrupt ??
2034 if (baridx > 2 || baridx < 0) {
2035 printf("diow: unknown bar idx %d\n", baridx);
2040 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2041 uint64_t offset, int size)
2043 struct pci_emul_dsoftc *sc = pi->pi_arg;
2048 if (offset + size > DIOSZ) {
2049 printf("dior: ior too large, offset %ld size %d\n",
2056 value = sc->ioregs[offset];
2057 } else if (size == 2) {
2058 value = *(uint16_t *) &sc->ioregs[offset];
2059 } else if (size == 4) {
2060 value = *(uint32_t *) &sc->ioregs[offset];
2062 printf("dior: ior unknown size %d\n", size);
2066 if (baridx == 1 || baridx == 2) {
2067 if (offset + size > DMEMSZ) {
2068 printf("dior: memr too large, offset %ld size %d\n",
2073 i = baridx - 1; /* 'memregs' index */
2076 value = sc->memregs[i][offset];
2077 } else if (size == 2) {
2078 value = *(uint16_t *) &sc->memregs[i][offset];
2079 } else if (size == 4) {
2080 value = *(uint32_t *) &sc->memregs[i][offset];
2081 } else if (size == 8) {
2082 value = *(uint64_t *) &sc->memregs[i][offset];
2084 printf("dior: ior unknown size %d\n", size);
2089 if (baridx > 2 || baridx < 0) {
2090 printf("dior: unknown bar idx %d\n", baridx);
2097 struct pci_devemu pci_dummy = {
2099 .pe_init = pci_emul_dinit,
2100 .pe_barwrite = pci_emul_diow,
2101 .pe_barread = pci_emul_dior
2103 PCI_EMUL_SET(pci_dummy);
2105 #endif /* PCI_EMUL_TEST */