2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
34 #include <sys/errno.h>
44 #include <machine/vmm.h>
49 #include "legacy_irq.h"
54 #define CONF1_ADDR_PORT 0x0cf8
55 #define CONF1_DATA_PORT 0x0cfc
57 #define CONF1_ENABLE 0x80000000ul
59 #define CFGWRITE(pi,off,val,b) \
62 pci_set_cfgdata8((pi),(off),(val)); \
63 } else if ((b) == 2) { \
64 pci_set_cfgdata16((pi),(off),(val)); \
66 pci_set_cfgdata32((pi),(off),(val)); \
70 #define MAXSLOTS (PCI_SLOTMAX + 1)
71 #define MAXFUNCS (PCI_FUNCMAX + 1)
73 static struct slotinfo {
76 struct pci_devinst *si_devi;
78 } pci_slotinfo[MAXSLOTS][MAXFUNCS];
80 SET_DECLARE(pci_devemu_set, struct pci_devemu);
82 static uint64_t pci_emul_iobase;
83 static uint64_t pci_emul_membase32;
84 static uint64_t pci_emul_membase64;
86 #define PCI_EMUL_IOBASE 0x2000
87 #define PCI_EMUL_IOLIMIT 0x10000
89 #define PCI_EMUL_MEMLIMIT32 0xE0000000 /* 3.5GB */
91 #define PCI_EMUL_MEMBASE64 0xD000000000UL
92 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
94 static struct pci_devemu *pci_emul_finddev(char *name);
96 static int pci_emul_devices;
103 * Slot options are in the form:
105 * <slot>[:<func>],<emul>[,<config>]
109 * emul is a string describing the type of PCI device e.g. virtio-net
110 * config is an optional string, depending on the device, that can be
111 * used for configuration.
117 pci_parse_slot_usage(char *aopt)
120 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt);
124 pci_parse_slot(char *opt, int legacy)
126 char *slot, *func, *emul, *config;
128 int error, snum, fnum;
131 str = cpy = strdup(opt);
133 slot = strsep(&str, ",");
135 if (strchr(slot, ':') != NULL) {
137 (void) strsep(&func, ":");
140 emul = strsep(&str, ",");
144 pci_parse_slot_usage(opt);
149 fnum = func ? atoi(func) : 0;
151 if (snum < 0 || snum >= MAXSLOTS || fnum < 0 || fnum >= MAXFUNCS) {
152 pci_parse_slot_usage(opt);
156 if (pci_slotinfo[snum][fnum].si_name != NULL) {
157 fprintf(stderr, "pci slot %d:%d already occupied!\n",
162 if (pci_emul_finddev(emul) == NULL) {
163 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n",
169 pci_slotinfo[snum][fnum].si_name = emul;
170 pci_slotinfo[snum][fnum].si_param = config;
171 pci_slotinfo[snum][fnum].si_legacy = legacy;
181 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
184 if (offset < pi->pi_msix.pba_offset)
187 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
195 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
198 int msix_entry_offset;
202 /* support only 4 or 8 byte writes */
203 if (size != 4 && size != 8)
207 * Return if table index is beyond what device supports
209 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
210 if (tab_index >= pi->pi_msix.table_count)
213 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
215 /* support only aligned writes */
216 if ((msix_entry_offset % size) != 0)
219 dest = (char *)(pi->pi_msix.table + tab_index);
220 dest += msix_entry_offset;
223 *((uint32_t *)dest) = value;
225 *((uint64_t *)dest) = value;
231 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
234 int msix_entry_offset;
236 uint64_t retval = ~0;
239 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
240 * table but we also allow 1 byte access to accomodate reads from
243 if (size != 1 && size != 4 && size != 8)
246 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
248 /* support only aligned reads */
249 if ((msix_entry_offset % size) != 0) {
253 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
255 if (tab_index < pi->pi_msix.table_count) {
256 /* valid MSI-X Table access */
257 dest = (char *)(pi->pi_msix.table + tab_index);
258 dest += msix_entry_offset;
261 retval = *((uint8_t *)dest);
263 retval = *((uint32_t *)dest);
265 retval = *((uint64_t *)dest);
266 } else if (pci_valid_pba_offset(pi, offset)) {
267 /* return 0 for PBA access */
275 pci_msix_table_bar(struct pci_devinst *pi)
278 if (pi->pi_msix.table != NULL)
279 return (pi->pi_msix.table_bar);
285 pci_msix_pba_bar(struct pci_devinst *pi)
288 if (pi->pi_msix.table != NULL)
289 return (pi->pi_msix.pba_bar);
295 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
296 uint32_t *eax, void *arg)
298 struct pci_devinst *pdi = arg;
299 struct pci_devemu *pe = pdi->pi_d;
303 for (i = 0; i <= PCI_BARMAX; i++) {
304 if (pdi->pi_bar[i].type == PCIBAR_IO &&
305 port >= pdi->pi_bar[i].addr &&
306 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
307 offset = port - pdi->pi_bar[i].addr;
309 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
312 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
321 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
322 int size, uint64_t *val, void *arg1, long arg2)
324 struct pci_devinst *pdi = arg1;
325 struct pci_devemu *pe = pdi->pi_d;
327 int bidx = (int) arg2;
329 assert(bidx <= PCI_BARMAX);
330 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
331 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
332 assert(addr >= pdi->pi_bar[bidx].addr &&
333 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
335 offset = addr - pdi->pi_bar[bidx].addr;
337 if (dir == MEM_F_WRITE)
338 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, size, *val);
340 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, offset, size);
347 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
352 assert((size & (size - 1)) == 0); /* must be a power of 2 */
354 base = roundup2(*baseptr, size);
356 if (base + size <= limit) {
358 *baseptr = base + size;
365 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
369 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size));
373 * Register (or unregister) the MMIO or I/O region associated with the BAR
374 * register 'idx' of an emulated pci device.
377 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
380 struct inout_port iop;
383 switch (pi->pi_bar[idx].type) {
385 bzero(&iop, sizeof(struct inout_port));
386 iop.name = pi->pi_name;
387 iop.port = pi->pi_bar[idx].addr;
388 iop.size = pi->pi_bar[idx].size;
390 iop.flags = IOPORT_F_INOUT;
391 iop.handler = pci_emul_io_handler;
393 error = register_inout(&iop);
395 error = unregister_inout(&iop);
399 bzero(&mr, sizeof(struct mem_range));
400 mr.name = pi->pi_name;
401 mr.base = pi->pi_bar[idx].addr;
402 mr.size = pi->pi_bar[idx].size;
405 mr.handler = pci_emul_mem_handler;
408 error = register_mem(&mr);
410 error = unregister_mem(&mr);
420 unregister_bar(struct pci_devinst *pi, int idx)
423 modify_bar_registration(pi, idx, 0);
427 register_bar(struct pci_devinst *pi, int idx)
430 modify_bar_registration(pi, idx, 1);
433 /* Are we decoding i/o port accesses for the emulated pci device? */
435 porten(struct pci_devinst *pi)
439 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
441 return (cmd & PCIM_CMD_PORTEN);
444 /* Are we decoding memory accesses for the emulated pci device? */
446 memen(struct pci_devinst *pi)
450 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
452 return (cmd & PCIM_CMD_MEMEN);
456 * Update the MMIO or I/O address that is decoded by the BAR register.
458 * If the pci device has enabled the address space decoding then intercept
459 * the address range decoded by the BAR register.
462 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
466 if (pi->pi_bar[idx].type == PCIBAR_IO)
472 unregister_bar(pi, idx);
477 pi->pi_bar[idx].addr = addr;
480 pi->pi_bar[idx].addr &= ~0xffffffffUL;
481 pi->pi_bar[idx].addr |= addr;
484 pi->pi_bar[idx].addr &= 0xffffffff;
485 pi->pi_bar[idx].addr |= addr;
492 register_bar(pi, idx);
496 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
497 enum pcibar_type type, uint64_t size)
500 uint64_t *baseptr, limit, addr, mask, lobits, bar;
502 assert(idx >= 0 && idx <= PCI_BARMAX);
504 if ((size & (size - 1)) != 0)
505 size = 1UL << flsl(size); /* round up to a power of 2 */
507 /* Enforce minimum BAR sizes required by the PCI standard */
508 if (type == PCIBAR_IO) {
519 addr = mask = lobits = 0;
523 pci_slotinfo[pdi->pi_slot][pdi->pi_func].si_legacy) {
524 assert(hostbase < PCI_EMUL_IOBASE);
527 baseptr = &pci_emul_iobase;
529 limit = PCI_EMUL_IOLIMIT;
530 mask = PCIM_BAR_IO_BASE;
531 lobits = PCIM_BAR_IO_SPACE;
536 * Some drivers do not work well if the 64-bit BAR is allocated
537 * above 4GB. Allow for this by allocating small requests under
538 * 4GB unless then allocation size is larger than some arbitrary
539 * number (32MB currently).
541 if (size > 32 * 1024 * 1024) {
543 * XXX special case for device requiring peer-peer DMA
545 if (size == 0x100000000UL)
548 baseptr = &pci_emul_membase64;
549 limit = PCI_EMUL_MEMLIMIT64;
550 mask = PCIM_BAR_MEM_BASE;
551 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
552 PCIM_BAR_MEM_PREFETCH;
555 baseptr = &pci_emul_membase32;
556 limit = PCI_EMUL_MEMLIMIT32;
557 mask = PCIM_BAR_MEM_BASE;
558 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
562 baseptr = &pci_emul_membase32;
563 limit = PCI_EMUL_MEMLIMIT32;
564 mask = PCIM_BAR_MEM_BASE;
565 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
568 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
572 if (baseptr != NULL) {
573 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
578 pdi->pi_bar[idx].type = type;
579 pdi->pi_bar[idx].addr = addr;
580 pdi->pi_bar[idx].size = size;
582 /* Initialize the BAR register in config space */
583 bar = (addr & mask) | lobits;
584 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
586 if (type == PCIBAR_MEM64) {
587 assert(idx + 1 <= PCI_BARMAX);
588 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
589 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
592 register_bar(pdi, idx);
597 #define CAP_START_OFFSET 0x40
599 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
601 int i, capoff, capid, reallen;
604 static u_char endofcap[4] = {
605 PCIY_RESERVED, 0, 0, 0
608 assert(caplen > 0 && capdata[0] != PCIY_RESERVED);
610 reallen = roundup2(caplen, 4); /* dword aligned */
612 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
613 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
614 capoff = CAP_START_OFFSET;
615 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
616 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
618 capoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR);
620 assert((capoff & 0x3) == 0);
621 capid = pci_get_cfgdata8(pi, capoff);
622 if (capid == PCIY_RESERVED)
624 capoff = pci_get_cfgdata8(pi, capoff + 1);
628 /* Check if we have enough space */
629 if (capoff + reallen + sizeof(endofcap) > PCI_REGMAX + 1)
632 /* Copy the capability */
633 for (i = 0; i < caplen; i++)
634 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
636 /* Set the next capability pointer */
637 pci_set_cfgdata8(pi, capoff + 1, capoff + reallen);
639 /* Copy of the reserved capability which serves as the end marker */
640 for (i = 0; i < sizeof(endofcap); i++)
641 pci_set_cfgdata8(pi, capoff + reallen + i, endofcap[i]);
646 static struct pci_devemu *
647 pci_emul_finddev(char *name)
649 struct pci_devemu **pdpp, *pdp;
651 SET_FOREACH(pdpp, pci_devemu_set) {
653 if (!strcmp(pdp->pe_emu, name)) {
662 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int slot, int func,
665 struct pci_devinst *pdi;
668 pdi = malloc(sizeof(struct pci_devinst));
669 bzero(pdi, sizeof(*pdi));
675 pdi->pi_lintr_pin = -1;
677 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
679 /* Disable legacy interrupts */
680 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
681 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
683 pci_set_cfgdata8(pdi, PCIR_COMMAND,
684 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
686 err = (*pde->pe_init)(ctx, pdi, params);
691 pci_slotinfo[slot][func].si_devi = pdi;
698 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
702 CTASSERT(sizeof(struct msicap) == 14);
704 /* Number of msi messages must be a power of 2 between 1 and 32 */
705 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
706 mmc = ffs(msgnum) - 1;
708 bzero(msicap, sizeof(struct msicap));
709 msicap->capid = PCIY_MSI;
710 msicap->nextptr = nextptr;
711 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
715 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
717 struct msicap msicap;
719 pci_populate_msicap(&msicap, msgnum, 0);
721 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
725 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
726 uint32_t msix_tab_size, int nextptr)
728 CTASSERT(sizeof(struct msixcap) == 12);
730 assert(msix_tab_size % 4096 == 0);
732 bzero(msixcap, sizeof(struct msixcap));
733 msixcap->capid = PCIY_MSIX;
734 msixcap->nextptr = nextptr;
737 * Message Control Register, all fields set to
738 * zero except for the Table Size.
739 * Note: Table size N is encoded as N-1
741 msixcap->msgctrl = msgnum - 1;
745 * - MSI-X table start at offset 0
746 * - PBA table starts at a 4K aligned offset after the MSI-X table
748 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
749 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
753 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
757 assert(table_entries > 0);
758 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
760 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
761 pi->pi_msix.table = malloc(table_size);
762 bzero(pi->pi_msix.table, table_size);
764 /* set mask bit of vector control register */
765 for (i = 0; i < table_entries; i++)
766 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
770 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
774 struct msixcap msixcap;
776 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
777 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
779 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
781 /* Align table size to nearest 4K */
782 tab_size = roundup2(tab_size, 4096);
784 pi->pi_msix.table_bar = barnum;
785 pi->pi_msix.pba_bar = barnum;
786 pi->pi_msix.table_offset = 0;
787 pi->pi_msix.table_count = msgnum;
788 pi->pi_msix.pba_offset = tab_size;
790 /* calculate the MMIO size required for MSI-X PBA */
791 pba_index = (msgnum - 1) / (PBA_TABLE_ENTRY_SIZE * 8);
792 pi->pi_msix.pba_size = (pba_index + 1) * PBA_TABLE_ENTRY_SIZE;
794 pci_msix_table_init(pi, msgnum);
796 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size, 0);
798 /* allocate memory for MSI-X Table and PBA */
799 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
800 tab_size + pi->pi_msix.pba_size);
802 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
807 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
808 int bytes, uint32_t val)
810 uint16_t msgctrl, rwmask;
813 off = offset - capoff;
814 table_bar = pi->pi_msix.table_bar;
815 /* Message Control Register */
816 if (off == 2 && bytes == 2) {
817 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
818 msgctrl = pci_get_cfgdata16(pi, offset);
820 msgctrl |= val & rwmask;
823 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
824 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
827 CFGWRITE(pi, offset, val, bytes);
831 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
832 int bytes, uint32_t val)
834 uint16_t msgctrl, rwmask, msgdata, mme;
838 * If guest is writing to the message control register make sure
839 * we do not overwrite read-only fields.
841 if ((offset - capoff) == 2 && bytes == 2) {
842 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
843 msgctrl = pci_get_cfgdata16(pi, offset);
845 msgctrl |= val & rwmask;
848 addrlo = pci_get_cfgdata32(pi, capoff + 4);
849 if (msgctrl & PCIM_MSICTRL_64BIT)
850 msgdata = pci_get_cfgdata16(pi, capoff + 12);
852 msgdata = pci_get_cfgdata16(pi, capoff + 8);
855 * XXX check delivery mode, destination mode etc
857 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
858 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
859 if (pi->pi_msi.enabled) {
860 pi->pi_msi.cpu = (addrlo >> 12) & 0xff;
861 pi->pi_msi.vector = msgdata & 0xff;
862 pi->pi_msi.msgnum = 1 << (mme >> 4);
865 pi->pi_msi.vector = 0;
866 pi->pi_msi.msgnum = 0;
870 CFGWRITE(pi, offset, val, bytes);
874 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
875 int bytes, uint32_t val)
878 /* XXX don't write to the readonly parts */
879 CFGWRITE(pi, offset, val, bytes);
882 #define PCIECAP_VERSION 0x2
884 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
887 struct pciecap pciecap;
889 CTASSERT(sizeof(struct pciecap) == 60);
891 if (type != PCIEM_TYPE_ROOT_PORT)
894 bzero(&pciecap, sizeof(pciecap));
896 pciecap.capid = PCIY_EXPRESS;
897 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT;
898 pciecap.link_capabilities = 0x411; /* gen1, x1 */
899 pciecap.link_status = 0x11; /* gen1, x1 */
901 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
906 * This function assumes that 'coff' is in the capabilities region of the
910 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val)
913 uint8_t capoff, nextoff;
915 /* Do not allow un-aligned writes */
916 if ((offset & (bytes - 1)) != 0)
919 /* Find the capability that we want to update */
920 capoff = CAP_START_OFFSET;
922 capid = pci_get_cfgdata8(pi, capoff);
923 if (capid == PCIY_RESERVED)
926 nextoff = pci_get_cfgdata8(pi, capoff + 1);
927 if (offset >= capoff && offset < nextoff)
932 assert(offset >= capoff);
935 * Capability ID and Next Capability Pointer are readonly.
936 * However, some o/s's do 4-byte writes that include these.
937 * For this case, trim the write back to 2 bytes and adjust
940 if (offset == capoff || offset == capoff + 1) {
941 if (offset == capoff && bytes == 4) {
951 msicap_cfgwrite(pi, capoff, offset, bytes, val);
954 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
957 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
965 pci_emul_iscap(struct pci_devinst *pi, int offset)
969 uint8_t capid, lastoff;
972 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
973 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
974 lastoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR);
976 assert((lastoff & 0x3) == 0);
977 capid = pci_get_cfgdata8(pi, lastoff);
978 if (capid == PCIY_RESERVED)
980 lastoff = pci_get_cfgdata8(pi, lastoff + 1);
982 if (offset >= CAP_START_OFFSET && offset <= lastoff)
989 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
990 int size, uint64_t *val, void *arg1, long arg2)
993 * Ignore writes; return 0xff's for reads. The mem read code
994 * will take care of truncating to the correct size.
996 if (dir == MEM_F_READ) {
997 *val = 0xffffffffffffffff;
1004 init_pci(struct vmctx *ctx)
1006 struct mem_range memp;
1007 struct pci_devemu *pde;
1008 struct slotinfo *si;
1013 pci_emul_iobase = PCI_EMUL_IOBASE;
1014 pci_emul_membase32 = vm_get_lowmem_limit(ctx);
1015 pci_emul_membase64 = PCI_EMUL_MEMBASE64;
1017 for (slot = 0; slot < MAXSLOTS; slot++) {
1018 for (func = 0; func < MAXFUNCS; func++) {
1019 si = &pci_slotinfo[slot][func];
1020 if (si->si_name != NULL) {
1021 pde = pci_emul_finddev(si->si_name);
1022 assert(pde != NULL);
1023 error = pci_emul_init(ctx, pde, slot, func,
1032 * The guest physical memory map looks like the following:
1033 * [0, lowmem) guest system memory
1034 * [lowmem, lowmem_limit) memory hole (may be absent)
1035 * [lowmem_limit, 4GB) PCI hole (32-bit BAR allocation)
1036 * [4GB, 4GB + highmem)
1038 * Accesses to memory addresses that are not allocated to system
1039 * memory or PCI devices return 0xff's.
1041 error = vm_get_memory_seg(ctx, 0, &lowmem, NULL);
1044 memset(&memp, 0, sizeof(struct mem_range));
1045 memp.name = "PCI hole";
1046 memp.flags = MEM_F_RW;
1048 memp.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1049 memp.handler = pci_emul_fallback_handler;
1051 error = register_mem_fallback(&memp);
1058 pci_msi_enabled(struct pci_devinst *pi)
1060 return (pi->pi_msi.enabled);
1064 pci_msi_msgnum(struct pci_devinst *pi)
1066 if (pi->pi_msi.enabled)
1067 return (pi->pi_msi.msgnum);
1073 pci_msix_enabled(struct pci_devinst *pi)
1076 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1080 pci_generate_msix(struct pci_devinst *pi, int index)
1082 struct msix_table_entry *mte;
1084 if (!pci_msix_enabled(pi))
1087 if (pi->pi_msix.function_mask)
1090 if (index >= pi->pi_msix.table_count)
1093 mte = &pi->pi_msix.table[index];
1094 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1095 /* XXX Set PBA bit if interrupt is disabled */
1096 vm_lapic_irq(pi->pi_vmctx,
1097 (mte->addr >> 12) & 0xff, mte->msg_data & 0xff);
1102 pci_generate_msi(struct pci_devinst *pi, int msg)
1105 if (pci_msi_enabled(pi) && msg < pci_msi_msgnum(pi)) {
1106 vm_lapic_irq(pi->pi_vmctx,
1108 pi->pi_msi.vector + msg);
1113 pci_is_legacy(struct pci_devinst *pi)
1116 return (pci_slotinfo[pi->pi_slot][pi->pi_func].si_legacy);
1120 pci_lintr_request(struct pci_devinst *pi, int req)
1124 irq = legacy_irq_alloc(req);
1128 pi->pi_lintr_pin = irq;
1129 pci_set_cfgdata8(pi, PCIR_INTLINE, irq);
1130 pci_set_cfgdata8(pi, PCIR_INTPIN, 1);
1135 pci_lintr_assert(struct pci_devinst *pi)
1138 assert(pi->pi_lintr_pin >= 0);
1139 ioapic_assert_pin(pi->pi_vmctx, pi->pi_lintr_pin);
1143 pci_lintr_deassert(struct pci_devinst *pi)
1146 assert(pi->pi_lintr_pin >= 0);
1147 ioapic_deassert_pin(pi->pi_vmctx, pi->pi_lintr_pin);
1151 * Return 1 if the emulated device in 'slot' is a multi-function device.
1152 * Return 0 otherwise.
1155 pci_emul_is_mfdev(int slot)
1160 for (f = 0; f < MAXFUNCS; f++) {
1161 if (pci_slotinfo[slot][f].si_devi != NULL) {
1165 return (numfuncs > 1);
1169 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1170 * whether or not is a multi-function being emulated in the pci 'slot'.
1173 pci_emul_hdrtype_fixup(int slot, int off, int bytes, uint32_t *rv)
1177 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1178 mfdev = pci_emul_is_mfdev(slot);
1188 *rv &= ~(PCIM_MFDEV << 16);
1190 *rv |= (PCIM_MFDEV << 16);
1197 static int cfgbus, cfgslot, cfgfunc, cfgoff;
1200 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1201 uint32_t *eax, void *arg)
1207 *eax = (bytes == 2) ? 0xffff : 0xff;
1212 x = (cfgbus << 16) |
1216 *eax = x | CONF1_ENABLE;
1219 cfgoff = x & PCI_REGMAX;
1220 cfgfunc = (x >> 8) & PCI_FUNCMAX;
1221 cfgslot = (x >> 11) & PCI_SLOTMAX;
1222 cfgbus = (x >> 16) & PCI_BUSMAX;
1227 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
1230 bits_changed(uint32_t old, uint32_t new, uint32_t mask)
1233 return ((old ^ new) & mask);
1237 pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes)
1243 * The command register is at an offset of 4 bytes and thus the
1244 * guest could write 1, 2 or 4 bytes starting at this offset.
1247 old = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
1248 CFGWRITE(pi, PCIR_COMMAND, new, bytes); /* update config */
1249 new = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */
1252 * If the MMIO or I/O address space decoding has changed then
1253 * register/unregister all BARs that decode that address space.
1255 for (i = 0; i < PCI_BARMAX; i++) {
1256 switch (pi->pi_bar[i].type) {
1258 case PCIBAR_MEMHI64:
1261 /* I/O address space decoding changed? */
1262 if (bits_changed(old, new, PCIM_CMD_PORTEN)) {
1264 register_bar(pi, i);
1266 unregister_bar(pi, i);
1271 /* MMIO address space decoding changed? */
1272 if (bits_changed(old, new, PCIM_CMD_MEMEN)) {
1274 register_bar(pi, i);
1276 unregister_bar(pi, i);
1286 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1287 uint32_t *eax, void *arg)
1289 struct pci_devinst *pi;
1290 struct pci_devemu *pe;
1291 int coff, idx, needcfg;
1292 uint64_t addr, bar, mask;
1294 assert(bytes == 1 || bytes == 2 || bytes == 4);
1297 pi = pci_slotinfo[cfgslot][cfgfunc].si_devi;
1301 coff = cfgoff + (port - CONF1_DATA_PORT);
1304 printf("pcicfg-%s from 0x%0x of %d bytes (%d/%d/%d)\n\r",
1305 in ? "read" : "write", coff, bytes, cfgbus, cfgslot, cfgfunc);
1309 * Just return if there is no device at this cfgslot:cfgfunc or
1310 * if the guest is doing an un-aligned access
1312 if (pi == NULL || (coff & (bytes - 1)) != 0) {
1324 /* Let the device emulation override the default handler */
1325 if (pe->pe_cfgread != NULL) {
1326 needcfg = pe->pe_cfgread(ctx, vcpu, pi,
1334 *eax = pci_get_cfgdata8(pi, coff);
1335 else if (bytes == 2)
1336 *eax = pci_get_cfgdata16(pi, coff);
1338 *eax = pci_get_cfgdata32(pi, coff);
1341 pci_emul_hdrtype_fixup(cfgslot, coff, bytes, eax);
1343 /* Let the device emulation override the default handler */
1344 if (pe->pe_cfgwrite != NULL &&
1345 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
1349 * Special handling for write to BAR registers
1351 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) {
1353 * Ignore writes to BAR registers that are not
1356 if (bytes != 4 || (coff & 0x3) != 0)
1358 idx = (coff - PCIR_BAR(0)) / 4;
1359 mask = ~(pi->pi_bar[idx].size - 1);
1360 switch (pi->pi_bar[idx].type) {
1362 pi->pi_bar[idx].addr = bar = 0;
1367 bar = addr | PCIM_BAR_IO_SPACE;
1369 * Register the new BAR value for interception
1371 if (addr != pi->pi_bar[idx].addr) {
1372 update_bar_address(pi, addr, idx,
1377 addr = bar = *eax & mask;
1378 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
1379 if (addr != pi->pi_bar[idx].addr) {
1380 update_bar_address(pi, addr, idx,
1385 addr = bar = *eax & mask;
1386 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
1387 PCIM_BAR_MEM_PREFETCH;
1388 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
1389 update_bar_address(pi, addr, idx,
1393 case PCIBAR_MEMHI64:
1394 mask = ~(pi->pi_bar[idx - 1].size - 1);
1395 addr = ((uint64_t)*eax << 32) & mask;
1397 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
1398 update_bar_address(pi, addr, idx - 1,
1405 pci_set_cfgdata32(pi, coff, bar);
1407 } else if (pci_emul_iscap(pi, coff)) {
1408 pci_emul_capwrite(pi, coff, bytes, *eax);
1409 } else if (coff == PCIR_COMMAND) {
1410 pci_emul_cmdwrite(pi, *eax, bytes);
1412 CFGWRITE(pi, coff, *eax, bytes);
1419 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
1420 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
1421 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
1422 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
1425 * I/O ports to configure PCI IRQ routing. We ignore all writes to it.
1428 pci_irq_port_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1429 uint32_t *eax, void *arg)
1434 INOUT_PORT(pci_irq, 0xC00, IOPORT_F_OUT, pci_irq_port_handler);
1435 INOUT_PORT(pci_irq, 0xC01, IOPORT_F_OUT, pci_irq_port_handler);
1437 #define PCI_EMUL_TEST
1438 #ifdef PCI_EMUL_TEST
1440 * Define a dummy test device
1444 struct pci_emul_dsoftc {
1445 uint8_t ioregs[DIOSZ];
1446 uint8_t memregs[DMEMSZ];
1449 #define PCI_EMUL_MSI_MSGS 4
1450 #define PCI_EMUL_MSIX_MSGS 16
1453 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1456 struct pci_emul_dsoftc *sc;
1458 sc = malloc(sizeof(struct pci_emul_dsoftc));
1459 memset(sc, 0, sizeof(struct pci_emul_dsoftc));
1463 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
1464 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
1465 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
1467 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
1470 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
1473 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
1480 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1481 uint64_t offset, int size, uint64_t value)
1484 struct pci_emul_dsoftc *sc = pi->pi_arg;
1487 if (offset + size > DIOSZ) {
1488 printf("diow: iow too large, offset %ld size %d\n",
1494 sc->ioregs[offset] = value & 0xff;
1495 } else if (size == 2) {
1496 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
1497 } else if (size == 4) {
1498 *(uint32_t *)&sc->ioregs[offset] = value;
1500 printf("diow: iow unknown size %d\n", size);
1504 * Special magic value to generate an interrupt
1506 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
1507 pci_generate_msi(pi, value % pci_msi_msgnum(pi));
1509 if (value == 0xabcdef) {
1510 for (i = 0; i < pci_msi_msgnum(pi); i++)
1511 pci_generate_msi(pi, i);
1516 if (offset + size > DMEMSZ) {
1517 printf("diow: memw too large, offset %ld size %d\n",
1523 sc->memregs[offset] = value;
1524 } else if (size == 2) {
1525 *(uint16_t *)&sc->memregs[offset] = value;
1526 } else if (size == 4) {
1527 *(uint32_t *)&sc->memregs[offset] = value;
1528 } else if (size == 8) {
1529 *(uint64_t *)&sc->memregs[offset] = value;
1531 printf("diow: memw unknown size %d\n", size);
1535 * magic interrupt ??
1540 printf("diow: unknown bar idx %d\n", baridx);
1545 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1546 uint64_t offset, int size)
1548 struct pci_emul_dsoftc *sc = pi->pi_arg;
1552 if (offset + size > DIOSZ) {
1553 printf("dior: ior too large, offset %ld size %d\n",
1559 value = sc->ioregs[offset];
1560 } else if (size == 2) {
1561 value = *(uint16_t *) &sc->ioregs[offset];
1562 } else if (size == 4) {
1563 value = *(uint32_t *) &sc->ioregs[offset];
1565 printf("dior: ior unknown size %d\n", size);
1570 if (offset + size > DMEMSZ) {
1571 printf("dior: memr too large, offset %ld size %d\n",
1577 value = sc->memregs[offset];
1578 } else if (size == 2) {
1579 value = *(uint16_t *) &sc->memregs[offset];
1580 } else if (size == 4) {
1581 value = *(uint32_t *) &sc->memregs[offset];
1582 } else if (size == 8) {
1583 value = *(uint64_t *) &sc->memregs[offset];
1585 printf("dior: ior unknown size %d\n", size);
1591 printf("dior: unknown bar idx %d\n", baridx);
1598 struct pci_devemu pci_dummy = {
1600 .pe_init = pci_emul_dinit,
1601 .pe_barwrite = pci_emul_diow,
1602 .pe_barread = pci_emul_dior
1604 PCI_EMUL_SET(pci_dummy);
1606 #endif /* PCI_EMUL_TEST */