2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/linker_set.h>
50 #include <machine/vmm.h>
51 #include <machine/vmm_snapshot.h>
65 #define CONF1_ADDR_PORT 0x0cf8
66 #define CONF1_DATA_PORT 0x0cfc
68 #define CONF1_ENABLE 0x80000000ul
70 #define MAXBUSES (PCI_BUSMAX + 1)
71 #define MAXSLOTS (PCI_SLOTMAX + 1)
72 #define MAXFUNCS (PCI_FUNCMAX + 1)
74 #define GB (1024 * 1024 * 1024UL)
78 struct pci_devemu *fi_pde;
79 struct pci_devinst *fi_devi;
89 struct intxinfo si_intpins[4];
90 struct funcinfo si_funcs[MAXFUNCS];
94 uint16_t iobase, iolimit; /* I/O window */
95 uint32_t membase32, memlimit32; /* mmio window below 4GB */
96 uint64_t membase64, memlimit64; /* mmio window above 4GB */
97 struct slotinfo slotinfo[MAXSLOTS];
100 static struct businfo *pci_businfo[MAXBUSES];
102 SET_DECLARE(pci_devemu_set, struct pci_devemu);
104 static uint64_t pci_emul_iobase;
105 static uint8_t *pci_emul_rombase;
106 static uint64_t pci_emul_romoffset;
107 static uint8_t *pci_emul_romlim;
108 static uint64_t pci_emul_membase32;
109 static uint64_t pci_emul_membase64;
110 static uint64_t pci_emul_memlim64;
112 struct pci_bar_allocation {
113 TAILQ_ENTRY(pci_bar_allocation) chain;
114 struct pci_devinst *pdi;
116 enum pcibar_type type;
120 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars =
121 TAILQ_HEAD_INITIALIZER(pci_bars);
123 #define PCI_EMUL_IOBASE 0x2000
124 #define PCI_EMUL_IOLIMIT 0x10000
126 #define PCI_EMUL_ROMSIZE 0x10000000
128 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
129 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
130 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
133 * OVMF always uses 0xC0000000 as base address for 32 bit PCI MMIO. Don't
134 * change this address without changing it in OVMF.
136 #define PCI_EMUL_MEMBASE32 0xC0000000
137 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
138 #define PCI_EMUL_MEMSIZE64 (32*GB)
140 static struct pci_devemu *pci_emul_finddev(const char *name);
141 static void pci_lintr_route(struct pci_devinst *pi);
142 static void pci_lintr_update(struct pci_devinst *pi);
143 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
144 int func, int coff, int bytes, uint32_t *val);
147 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
151 pci_set_cfgdata8(pi, coff, val);
153 pci_set_cfgdata16(pi, coff, val);
155 pci_set_cfgdata32(pi, coff, val);
158 static __inline uint32_t
159 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
163 return (pci_get_cfgdata8(pi, coff));
165 return (pci_get_cfgdata16(pi, coff));
167 return (pci_get_cfgdata32(pi, coff));
171 is_pcir_bar(int coff)
173 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1));
177 is_pcir_bios(int coff)
179 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4);
187 * Slot options are in the form:
189 * <bus>:<slot>:<func>,<emul>[,<config>]
190 * <slot>[:<func>],<emul>[,<config>]
194 * emul is a string describing the type of PCI device e.g. virtio-net
195 * config is an optional string, depending on the device, that can be
196 * used for configuration.
202 pci_parse_slot_usage(char *aopt)
205 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt);
209 * Helper function to parse a list of comma-separated options where
210 * each option is formatted as "name[=value]". If no value is
211 * provided, the option is treated as a boolean and is given a value
215 pci_parse_legacy_config(nvlist_t *nvl, const char *opt)
217 char *config, *name, *tofree, *value;
222 config = tofree = strdup(opt);
223 while ((name = strsep(&config, ",")) != NULL) {
224 value = strchr(name, '=');
228 set_config_value_node(nvl, name, value);
230 set_config_bool_node(nvl, name, true);
237 * PCI device configuration is stored in MIBs that encode the device's
240 * pci.<bus>.<slot>.<func>
242 * Where "bus", "slot", and "func" are all decimal values without
243 * leading zeroes. Each valid device must have a "device" node which
244 * identifies the driver model of the device.
246 * Device backends can provide a parser for the "config" string. If
247 * a custom parser is not provided, pci_parse_legacy_config() is used
248 * to parse the string.
251 pci_parse_slot(char *opt)
253 char node_name[sizeof("pci.XXX.XX.X")];
254 struct pci_devemu *pde;
255 char *emul, *config, *str, *cp;
256 int error, bnum, snum, fnum;
262 emul = config = NULL;
263 if ((cp = strchr(str, ',')) != NULL) {
266 if ((cp = strchr(emul, ',')) != NULL) {
271 pci_parse_slot_usage(opt);
275 /* <bus>:<slot>:<func> */
276 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
279 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
282 if (sscanf(str, "%d", &snum) != 1) {
288 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
289 fnum < 0 || fnum >= MAXFUNCS) {
290 pci_parse_slot_usage(opt);
294 pde = pci_emul_finddev(emul);
296 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum,
301 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum,
303 nvl = find_config_node(node_name);
305 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum,
309 nvl = create_config_node(node_name);
310 if (pde->pe_alias != NULL)
311 set_config_value_node(nvl, "device", pde->pe_alias);
313 set_config_value_node(nvl, "device", pde->pe_emu);
315 if (pde->pe_legacy_config != NULL)
316 error = pde->pe_legacy_config(nvl, config);
318 error = pci_parse_legacy_config(nvl, config);
325 pci_print_supported_devices(void)
327 struct pci_devemu **pdpp, *pdp;
329 SET_FOREACH(pdpp, pci_devemu_set) {
331 printf("%s\n", pdp->pe_emu);
336 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
339 if (offset < pi->pi_msix.pba_offset)
342 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
350 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
353 int msix_entry_offset;
357 /* support only 4 or 8 byte writes */
358 if (size != 4 && size != 8)
362 * Return if table index is beyond what device supports
364 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
365 if (tab_index >= pi->pi_msix.table_count)
368 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
370 /* support only aligned writes */
371 if ((msix_entry_offset % size) != 0)
374 dest = (char *)(pi->pi_msix.table + tab_index);
375 dest += msix_entry_offset;
378 *((uint32_t *)dest) = value;
380 *((uint64_t *)dest) = value;
386 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
389 int msix_entry_offset;
391 uint64_t retval = ~0;
394 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
395 * table but we also allow 1 byte access to accommodate reads from
398 if (size != 1 && size != 4 && size != 8)
401 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
403 /* support only aligned reads */
404 if ((msix_entry_offset % size) != 0) {
408 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
410 if (tab_index < pi->pi_msix.table_count) {
411 /* valid MSI-X Table access */
412 dest = (char *)(pi->pi_msix.table + tab_index);
413 dest += msix_entry_offset;
416 retval = *((uint8_t *)dest);
418 retval = *((uint32_t *)dest);
420 retval = *((uint64_t *)dest);
421 } else if (pci_valid_pba_offset(pi, offset)) {
422 /* return 0 for PBA access */
430 pci_msix_table_bar(struct pci_devinst *pi)
433 if (pi->pi_msix.table != NULL)
434 return (pi->pi_msix.table_bar);
440 pci_msix_pba_bar(struct pci_devinst *pi)
443 if (pi->pi_msix.table != NULL)
444 return (pi->pi_msix.pba_bar);
450 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
451 uint32_t *eax, void *arg)
453 struct pci_devinst *pdi = arg;
454 struct pci_devemu *pe = pdi->pi_d;
458 for (i = 0; i <= PCI_BARMAX; i++) {
459 if (pdi->pi_bar[i].type == PCIBAR_IO &&
460 port >= pdi->pi_bar[i].addr &&
461 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
462 offset = port - pdi->pi_bar[i].addr;
464 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
467 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
476 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
477 int size, uint64_t *val, void *arg1, long arg2)
479 struct pci_devinst *pdi = arg1;
480 struct pci_devemu *pe = pdi->pi_d;
482 int bidx = (int) arg2;
484 assert(bidx <= PCI_BARMAX);
485 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
486 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
487 assert(addr >= pdi->pi_bar[bidx].addr &&
488 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
490 offset = addr - pdi->pi_bar[bidx].addr;
492 if (dir == MEM_F_WRITE) {
494 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
495 4, *val & 0xffffffff);
496 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
499 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
504 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
506 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
507 offset + 4, 4) << 32;
509 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
519 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
524 assert((size & (size - 1)) == 0); /* must be a power of 2 */
526 base = roundup2(*baseptr, size);
528 if (base + size <= limit) {
530 *baseptr = base + size;
537 * Register (or unregister) the MMIO or I/O region associated with the BAR
538 * register 'idx' of an emulated pci device.
541 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
543 struct pci_devemu *pe;
545 struct inout_port iop;
549 switch (pi->pi_bar[idx].type) {
551 bzero(&iop, sizeof(struct inout_port));
552 iop.name = pi->pi_name;
553 iop.port = pi->pi_bar[idx].addr;
554 iop.size = pi->pi_bar[idx].size;
556 iop.flags = IOPORT_F_INOUT;
557 iop.handler = pci_emul_io_handler;
559 error = register_inout(&iop);
561 error = unregister_inout(&iop);
562 if (pe->pe_baraddr != NULL)
563 (*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration,
564 pi->pi_bar[idx].addr);
568 bzero(&mr, sizeof(struct mem_range));
569 mr.name = pi->pi_name;
570 mr.base = pi->pi_bar[idx].addr;
571 mr.size = pi->pi_bar[idx].size;
574 mr.handler = pci_emul_mem_handler;
577 error = register_mem(&mr);
579 error = unregister_mem(&mr);
580 if (pe->pe_baraddr != NULL)
581 (*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration,
582 pi->pi_bar[idx].addr);
586 if (pe->pe_baraddr != NULL)
587 (*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration,
588 pi->pi_bar[idx].addr);
598 unregister_bar(struct pci_devinst *pi, int idx)
601 modify_bar_registration(pi, idx, 0);
605 register_bar(struct pci_devinst *pi, int idx)
608 modify_bar_registration(pi, idx, 1);
611 /* Is the ROM enabled for the emulated pci device? */
613 romen(struct pci_devinst *pi)
615 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) ==
619 /* Are we decoding i/o port accesses for the emulated pci device? */
621 porten(struct pci_devinst *pi)
625 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
627 return (cmd & PCIM_CMD_PORTEN);
630 /* Are we decoding memory accesses for the emulated pci device? */
632 memen(struct pci_devinst *pi)
636 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
638 return (cmd & PCIM_CMD_MEMEN);
642 * Update the MMIO or I/O address that is decoded by the BAR register.
644 * If the pci device has enabled the address space decoding then intercept
645 * the address range decoded by the BAR register.
648 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
652 if (pi->pi_bar[idx].type == PCIBAR_IO)
658 unregister_bar(pi, idx);
663 pi->pi_bar[idx].addr = addr;
666 pi->pi_bar[idx].addr &= ~0xffffffffUL;
667 pi->pi_bar[idx].addr |= addr;
670 pi->pi_bar[idx].addr &= 0xffffffff;
671 pi->pi_bar[idx].addr |= addr;
678 register_bar(pi, idx);
682 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
685 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX));
686 assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX));
688 if ((size & (size - 1)) != 0)
689 size = 1UL << flsl(size); /* round up to a power of 2 */
691 /* Enforce minimum BAR sizes required by the PCI standard */
692 if (type == PCIBAR_IO) {
695 } else if (type == PCIBAR_ROM) {
696 if (size < ~PCIM_BIOS_ADDR_MASK + 1)
697 size = ~PCIM_BIOS_ADDR_MASK + 1;
704 * To reduce fragmentation of the MMIO space, we allocate the BARs by
705 * size. Therefore, don't allocate the BAR yet. We create a list of all
706 * BAR allocation which is sorted by BAR size. When all PCI devices are
707 * initialized, we will assign an address to the BARs.
710 /* create a new list entry */
711 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar));
712 memset(new_bar, 0, sizeof(*new_bar));
715 new_bar->type = type;
716 new_bar->size = size;
719 * Search for a BAR which size is lower than the size of our newly
722 struct pci_bar_allocation *bar = NULL;
723 TAILQ_FOREACH(bar, &pci_bars, chain) {
724 if (bar->size < size) {
731 * Either the list is empty or new BAR is the smallest BAR of
732 * the list. Append it to the end of our list.
734 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain);
737 * The found BAR is smaller than our new BAR. For that reason,
738 * insert our new BAR before the found BAR.
740 TAILQ_INSERT_BEFORE(bar, new_bar, chain);
744 * pci_passthru devices synchronize their physical and virtual command
745 * register on init. For that reason, the virtual cmd reg should be
746 * updated as early as possible.
751 enbit = PCIM_CMD_PORTEN;
755 enbit = PCIM_CMD_MEMEN;
762 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND);
763 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit);
769 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx,
770 const enum pcibar_type type, const uint64_t size)
773 uint64_t *baseptr, limit, addr, mask, lobits, bar;
778 addr = mask = lobits = 0;
781 baseptr = &pci_emul_iobase;
782 limit = PCI_EMUL_IOLIMIT;
783 mask = PCIM_BAR_IO_BASE;
784 lobits = PCIM_BAR_IO_SPACE;
789 * Some drivers do not work well if the 64-bit BAR is allocated
790 * above 4GB. Allow for this by allocating small requests under
791 * 4GB unless then allocation size is larger than some arbitrary
792 * number (128MB currently).
794 if (size > 128 * 1024 * 1024) {
795 baseptr = &pci_emul_membase64;
796 limit = pci_emul_memlim64;
797 mask = PCIM_BAR_MEM_BASE;
798 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
799 PCIM_BAR_MEM_PREFETCH;
801 baseptr = &pci_emul_membase32;
802 limit = PCI_EMUL_MEMLIMIT32;
803 mask = PCIM_BAR_MEM_BASE;
804 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
808 baseptr = &pci_emul_membase32;
809 limit = PCI_EMUL_MEMLIMIT32;
810 mask = PCIM_BAR_MEM_BASE;
811 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
814 /* do not claim memory for ROM. OVMF will do it for us. */
817 mask = PCIM_BIOS_ADDR_MASK;
821 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
825 if (baseptr != NULL) {
826 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
833 pdi->pi_bar[idx].type = type;
834 pdi->pi_bar[idx].addr = addr;
835 pdi->pi_bar[idx].size = size;
837 * passthru devices are using same lobits as physical device they set
840 if (pdi->pi_bar[idx].lobits != 0) {
841 lobits = pdi->pi_bar[idx].lobits;
843 pdi->pi_bar[idx].lobits = lobits;
846 /* Initialize the BAR register in config space */
847 bar = (addr & mask) | lobits;
848 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
850 if (type == PCIBAR_MEM64) {
851 assert(idx + 1 <= PCI_BARMAX);
852 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
853 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
856 if (type != PCIBAR_ROM) {
857 register_bar(pdi, idx);
864 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
867 /* allocate ROM space once on first call */
868 if (pci_emul_rombase == 0) {
869 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM,
870 "pcirom", PCI_EMUL_ROMSIZE);
871 if (pci_emul_rombase == MAP_FAILED) {
872 warnx("%s: failed to create rom segment", __func__);
875 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE;
876 pci_emul_romoffset = 0;
879 /* ROM size should be a power of 2 and greater than 2 KB */
880 const uint64_t rom_size = MAX(1UL << flsl(size),
881 ~PCIM_BIOS_ADDR_MASK + 1);
883 /* check if ROM fits into ROM space */
884 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) {
885 warnx("%s: no space left in rom segment:", __func__);
886 warnx("%16lu bytes left",
887 PCI_EMUL_ROMSIZE - pci_emul_romoffset);
888 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus,
889 pdi->pi_slot, pdi->pi_func);
893 /* allocate ROM BAR */
894 const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM,
900 *addr = pci_emul_rombase + pci_emul_romoffset;
902 /* save offset into ROM Space */
903 pdi->pi_romoffset = pci_emul_romoffset;
905 /* increase offset for next ROM */
906 pci_emul_romoffset += rom_size;
911 #define CAP_START_OFFSET 0x40
913 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
915 int i, capoff, reallen;
920 reallen = roundup2(caplen, 4); /* dword aligned */
922 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
923 if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
924 capoff = CAP_START_OFFSET;
926 capoff = pi->pi_capend + 1;
928 /* Check if we have enough space */
929 if (capoff + reallen > PCI_REGMAX + 1)
932 /* Set the previous capability pointer */
933 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
934 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
935 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
937 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
939 /* Copy the capability */
940 for (i = 0; i < caplen; i++)
941 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
943 /* Set the next capability pointer */
944 pci_set_cfgdata8(pi, capoff + 1, 0);
946 pi->pi_prevcap = capoff;
947 pi->pi_capend = capoff + reallen - 1;
951 static struct pci_devemu *
952 pci_emul_finddev(const char *name)
954 struct pci_devemu **pdpp, *pdp;
956 SET_FOREACH(pdpp, pci_devemu_set) {
958 if (!strcmp(pdp->pe_emu, name)) {
967 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
968 int func, struct funcinfo *fi)
970 struct pci_devinst *pdi;
973 pdi = calloc(1, sizeof(struct pci_devinst));
979 pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
980 pdi->pi_lintr.pin = 0;
981 pdi->pi_lintr.state = IDLE;
982 pdi->pi_lintr.pirq_pin = 0;
983 pdi->pi_lintr.ioapic_irq = 0;
985 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
987 /* Disable legacy interrupts */
988 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
989 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
991 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN);
993 err = (*pde->pe_init)(ctx, pdi, fi->fi_config);
1003 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
1007 /* Number of msi messages must be a power of 2 between 1 and 32 */
1008 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
1009 mmc = ffs(msgnum) - 1;
1011 bzero(msicap, sizeof(struct msicap));
1012 msicap->capid = PCIY_MSI;
1013 msicap->nextptr = nextptr;
1014 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
1018 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
1020 struct msicap msicap;
1022 pci_populate_msicap(&msicap, msgnum, 0);
1024 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
1028 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
1029 uint32_t msix_tab_size)
1032 assert(msix_tab_size % 4096 == 0);
1034 bzero(msixcap, sizeof(struct msixcap));
1035 msixcap->capid = PCIY_MSIX;
1038 * Message Control Register, all fields set to
1039 * zero except for the Table Size.
1040 * Note: Table size N is encoded as N-1
1042 msixcap->msgctrl = msgnum - 1;
1046 * - MSI-X table start at offset 0
1047 * - PBA table starts at a 4K aligned offset after the MSI-X table
1049 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
1050 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
1054 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
1058 assert(table_entries > 0);
1059 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
1061 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
1062 pi->pi_msix.table = calloc(1, table_size);
1064 /* set mask bit of vector control register */
1065 for (i = 0; i < table_entries; i++)
1066 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
1070 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
1073 struct msixcap msixcap;
1075 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
1076 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
1078 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
1080 /* Align table size to nearest 4K */
1081 tab_size = roundup2(tab_size, 4096);
1083 pi->pi_msix.table_bar = barnum;
1084 pi->pi_msix.pba_bar = barnum;
1085 pi->pi_msix.table_offset = 0;
1086 pi->pi_msix.table_count = msgnum;
1087 pi->pi_msix.pba_offset = tab_size;
1088 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
1090 pci_msix_table_init(pi, msgnum);
1092 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
1094 /* allocate memory for MSI-X Table and PBA */
1095 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
1096 tab_size + pi->pi_msix.pba_size);
1098 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
1103 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1104 int bytes, uint32_t val)
1106 uint16_t msgctrl, rwmask;
1109 off = offset - capoff;
1110 /* Message Control Register */
1111 if (off == 2 && bytes == 2) {
1112 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
1113 msgctrl = pci_get_cfgdata16(pi, offset);
1115 msgctrl |= val & rwmask;
1118 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
1119 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
1120 pci_lintr_update(pi);
1123 CFGWRITE(pi, offset, val, bytes);
1127 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1128 int bytes, uint32_t val)
1130 uint16_t msgctrl, rwmask, msgdata, mme;
1134 * If guest is writing to the message control register make sure
1135 * we do not overwrite read-only fields.
1137 if ((offset - capoff) == 2 && bytes == 2) {
1138 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
1139 msgctrl = pci_get_cfgdata16(pi, offset);
1141 msgctrl |= val & rwmask;
1144 CFGWRITE(pi, offset, val, bytes);
1146 msgctrl = pci_get_cfgdata16(pi, capoff + 2);
1147 addrlo = pci_get_cfgdata32(pi, capoff + 4);
1148 if (msgctrl & PCIM_MSICTRL_64BIT)
1149 msgdata = pci_get_cfgdata16(pi, capoff + 12);
1151 msgdata = pci_get_cfgdata16(pi, capoff + 8);
1153 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
1154 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
1155 if (pi->pi_msi.enabled) {
1156 pi->pi_msi.addr = addrlo;
1157 pi->pi_msi.msg_data = msgdata;
1158 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
1160 pi->pi_msi.maxmsgnum = 0;
1162 pci_lintr_update(pi);
1166 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1167 int bytes, uint32_t val)
1170 /* XXX don't write to the readonly parts */
1171 CFGWRITE(pi, offset, val, bytes);
1174 #define PCIECAP_VERSION 0x2
1176 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
1179 struct pciecap pciecap;
1181 bzero(&pciecap, sizeof(pciecap));
1184 * Use the integrated endpoint type for endpoints on a root complex bus.
1186 * NB: bhyve currently only supports a single PCI bus that is the root
1187 * complex bus, so all endpoints are integrated.
1189 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0))
1190 type = PCIEM_TYPE_ROOT_INT_EP;
1192 pciecap.capid = PCIY_EXPRESS;
1193 pciecap.pcie_capabilities = PCIECAP_VERSION | type;
1194 if (type != PCIEM_TYPE_ROOT_INT_EP) {
1195 pciecap.link_capabilities = 0x411; /* gen1, x1 */
1196 pciecap.link_status = 0x11; /* gen1, x1 */
1199 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
1204 * This function assumes that 'coff' is in the capabilities region of the
1205 * config space. A capoff parameter of zero will force a search for the
1209 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val,
1210 uint8_t capoff, int capid)
1214 /* Do not allow un-aligned writes */
1215 if ((offset & (bytes - 1)) != 0)
1219 /* Find the capability that we want to update */
1220 capoff = CAP_START_OFFSET;
1222 nextoff = pci_get_cfgdata8(pi, capoff + 1);
1225 if (offset >= capoff && offset < nextoff)
1230 assert(offset >= capoff);
1231 capid = pci_get_cfgdata8(pi, capoff);
1235 * Capability ID and Next Capability Pointer are readonly.
1236 * However, some o/s's do 4-byte writes that include these.
1237 * For this case, trim the write back to 2 bytes and adjust
1240 if (offset == capoff || offset == capoff + 1) {
1241 if (offset == capoff && bytes == 4) {
1251 msicap_cfgwrite(pi, capoff, offset, bytes, val);
1254 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1257 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1265 pci_emul_iscap(struct pci_devinst *pi, int offset)
1269 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1270 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1271 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1278 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1279 int size, uint64_t *val, void *arg1, long arg2)
1282 * Ignore writes; return 0xff's for reads. The mem read code
1283 * will take care of truncating to the correct size.
1285 if (dir == MEM_F_READ) {
1286 *val = 0xffffffffffffffff;
1293 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1294 int bytes, uint64_t *val, void *arg1, long arg2)
1296 int bus, slot, func, coff, in;
1298 coff = addr & 0xfff;
1299 func = (addr >> 12) & 0x7;
1300 slot = (addr >> 15) & 0x1f;
1301 bus = (addr >> 20) & 0xff;
1302 in = (dir == MEM_F_READ);
1305 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val);
1313 return (PCI_EMUL_ECFG_BASE);
1316 #define BUSIO_ROUNDUP 32
1317 #define BUSMEM32_ROUNDUP (1024 * 1024)
1318 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024)
1321 init_pci(struct vmctx *ctx)
1323 char node_name[sizeof("pci.XXX.XX.X")];
1324 struct mem_range mr;
1325 struct pci_devemu *pde;
1327 struct slotinfo *si;
1328 struct funcinfo *fi;
1332 int bus, slot, func;
1335 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32)
1336 errx(EX_OSERR, "Invalid lowmem limit");
1338 pci_emul_iobase = PCI_EMUL_IOBASE;
1339 pci_emul_membase32 = PCI_EMUL_MEMBASE32;
1341 pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx);
1342 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64);
1343 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64;
1345 for (bus = 0; bus < MAXBUSES; bus++) {
1346 snprintf(node_name, sizeof(node_name), "pci.%d", bus);
1347 nvl = find_config_node(node_name);
1350 pci_businfo[bus] = calloc(1, sizeof(struct businfo));
1351 bi = pci_businfo[bus];
1354 * Keep track of the i/o and memory resources allocated to
1357 bi->iobase = pci_emul_iobase;
1358 bi->membase32 = pci_emul_membase32;
1359 bi->membase64 = pci_emul_membase64;
1361 /* first run: init devices */
1362 for (slot = 0; slot < MAXSLOTS; slot++) {
1363 si = &bi->slotinfo[slot];
1364 for (func = 0; func < MAXFUNCS; func++) {
1365 fi = &si->si_funcs[func];
1366 snprintf(node_name, sizeof(node_name),
1367 "pci.%d.%d.%d", bus, slot, func);
1368 nvl = find_config_node(node_name);
1372 fi->fi_config = nvl;
1373 emul = get_config_value_node(nvl, "device");
1375 EPRINTLN("pci slot %d:%d:%d: missing "
1376 "\"device\" value", bus, slot, func);
1379 pde = pci_emul_finddev(emul);
1381 EPRINTLN("pci slot %d:%d:%d: unknown "
1382 "device \"%s\"", bus, slot, func,
1386 if (pde->pe_alias != NULL) {
1387 EPRINTLN("pci slot %d:%d:%d: legacy "
1388 "device \"%s\", use \"%s\" instead",
1389 bus, slot, func, emul,
1394 error = pci_emul_init(ctx, pde, bus, slot,
1401 /* second run: assign BARs and free list */
1402 struct pci_bar_allocation *bar;
1403 struct pci_bar_allocation *bar_tmp;
1404 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) {
1405 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type,
1409 TAILQ_INIT(&pci_bars);
1412 * Add some slop to the I/O and memory resources decoded by
1413 * this bus to give a guest some flexibility if it wants to
1414 * reprogram the BARs.
1416 pci_emul_iobase += BUSIO_ROUNDUP;
1417 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1418 bi->iolimit = pci_emul_iobase;
1420 pci_emul_membase32 += BUSMEM32_ROUNDUP;
1421 pci_emul_membase32 = roundup2(pci_emul_membase32,
1423 bi->memlimit32 = pci_emul_membase32;
1425 pci_emul_membase64 += BUSMEM64_ROUNDUP;
1426 pci_emul_membase64 = roundup2(pci_emul_membase64,
1428 bi->memlimit64 = pci_emul_membase64;
1432 * PCI backends are initialized before routing INTx interrupts
1433 * so that LPC devices are able to reserve ISA IRQs before
1434 * routing PIRQ pins.
1436 for (bus = 0; bus < MAXBUSES; bus++) {
1437 if ((bi = pci_businfo[bus]) == NULL)
1440 for (slot = 0; slot < MAXSLOTS; slot++) {
1441 si = &bi->slotinfo[slot];
1442 for (func = 0; func < MAXFUNCS; func++) {
1443 fi = &si->si_funcs[func];
1444 if (fi->fi_devi == NULL)
1446 pci_lintr_route(fi->fi_devi);
1453 * The guest physical memory map looks like the following:
1454 * [0, lowmem) guest system memory
1455 * [lowmem, 0xC0000000) memory hole (may be absent)
1456 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation)
1457 * [0xE0000000, 0xF0000000) PCI extended config window
1458 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
1459 * [4GB, 4GB + highmem)
1463 * Accesses to memory addresses that are not allocated to system
1464 * memory or PCI devices return 0xff's.
1466 lowmem = vm_get_lowmem_size(ctx);
1467 bzero(&mr, sizeof(struct mem_range));
1468 mr.name = "PCI hole";
1469 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1471 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1472 mr.handler = pci_emul_fallback_handler;
1473 error = register_mem_fallback(&mr);
1476 /* PCI extended config space */
1477 bzero(&mr, sizeof(struct mem_range));
1478 mr.name = "PCI ECFG";
1479 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1480 mr.base = PCI_EMUL_ECFG_BASE;
1481 mr.size = PCI_EMUL_ECFG_SIZE;
1482 mr.handler = pci_emul_ecfg_handler;
1483 error = register_mem(&mr);
1490 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1494 dsdt_line(" Package ()");
1496 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1497 dsdt_line(" 0x%02X,", pin - 1);
1498 dsdt_line(" Zero,");
1499 dsdt_line(" 0x%X", ioapic_irq);
1504 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1509 name = lpc_pirq_name(pirq_pin);
1512 dsdt_line(" Package ()");
1514 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1515 dsdt_line(" 0x%02X,", pin - 1);
1516 dsdt_line(" %s,", name);
1523 * A bhyve virtual machine has a flat PCI hierarchy with a root port
1524 * corresponding to each PCI bus.
1527 pci_bus_write_dsdt(int bus)
1530 struct slotinfo *si;
1531 struct pci_devinst *pi;
1532 int count, func, slot;
1535 * If there are no devices on this 'bus' then just return.
1537 if ((bi = pci_businfo[bus]) == NULL) {
1539 * Bus 0 is special because it decodes the I/O ports used
1540 * for PCI config space access even if there are no devices
1547 dsdt_line(" Device (PC%02X)", bus);
1549 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))");
1551 dsdt_line(" Method (_BBN, 0, NotSerialized)");
1553 dsdt_line(" Return (0x%08X)", bus);
1555 dsdt_line(" Name (_CRS, ResourceTemplate ()");
1557 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, "
1558 "MaxFixed, PosDecode,");
1559 dsdt_line(" 0x0000, // Granularity");
1560 dsdt_line(" 0x%04X, // Range Minimum", bus);
1561 dsdt_line(" 0x%04X, // Range Maximum", bus);
1562 dsdt_line(" 0x0000, // Translation Offset");
1563 dsdt_line(" 0x0001, // Length");
1568 dsdt_fixed_ioport(0xCF8, 8);
1571 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1572 "PosDecode, EntireRange,");
1573 dsdt_line(" 0x0000, // Granularity");
1574 dsdt_line(" 0x0000, // Range Minimum");
1575 dsdt_line(" 0x0CF7, // Range Maximum");
1576 dsdt_line(" 0x0000, // Translation Offset");
1577 dsdt_line(" 0x0CF8, // Length");
1578 dsdt_line(" ,, , TypeStatic)");
1580 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1581 "PosDecode, EntireRange,");
1582 dsdt_line(" 0x0000, // Granularity");
1583 dsdt_line(" 0x0D00, // Range Minimum");
1584 dsdt_line(" 0x%04X, // Range Maximum",
1585 PCI_EMUL_IOBASE - 1);
1586 dsdt_line(" 0x0000, // Translation Offset");
1587 dsdt_line(" 0x%04X, // Length",
1588 PCI_EMUL_IOBASE - 0x0D00);
1589 dsdt_line(" ,, , TypeStatic)");
1599 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1600 "PosDecode, EntireRange,");
1601 dsdt_line(" 0x0000, // Granularity");
1602 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase);
1603 dsdt_line(" 0x%04X, // Range Maximum",
1605 dsdt_line(" 0x0000, // Translation Offset");
1606 dsdt_line(" 0x%04X, // Length",
1607 bi->iolimit - bi->iobase);
1608 dsdt_line(" ,, , TypeStatic)");
1610 /* mmio window (32-bit) */
1611 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, "
1612 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1613 dsdt_line(" 0x00000000, // Granularity");
1614 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32);
1615 dsdt_line(" 0x%08X, // Range Maximum\n",
1616 bi->memlimit32 - 1);
1617 dsdt_line(" 0x00000000, // Translation Offset");
1618 dsdt_line(" 0x%08X, // Length\n",
1619 bi->memlimit32 - bi->membase32);
1620 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1622 /* mmio window (64-bit) */
1623 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, "
1624 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1625 dsdt_line(" 0x0000000000000000, // Granularity");
1626 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64);
1627 dsdt_line(" 0x%016lX, // Range Maximum\n",
1628 bi->memlimit64 - 1);
1629 dsdt_line(" 0x0000000000000000, // Translation Offset");
1630 dsdt_line(" 0x%016lX, // Length\n",
1631 bi->memlimit64 - bi->membase64);
1632 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1635 count = pci_count_lintr(bus);
1638 dsdt_line("Name (PPRT, Package ()");
1640 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1642 dsdt_line("Name (APRT, Package ()");
1644 pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1646 dsdt_line("Method (_PRT, 0, NotSerialized)");
1648 dsdt_line(" If (PICM)");
1650 dsdt_line(" Return (APRT)");
1654 dsdt_line(" Return (PPRT)");
1661 for (slot = 0; slot < MAXSLOTS; slot++) {
1662 si = &bi->slotinfo[slot];
1663 for (func = 0; func < MAXFUNCS; func++) {
1664 pi = si->si_funcs[func].fi_devi;
1665 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1666 pi->pi_d->pe_write_dsdt(pi);
1675 pci_write_dsdt(void)
1680 dsdt_line("Name (PICM, 0x00)");
1681 dsdt_line("Method (_PIC, 1, NotSerialized)");
1683 dsdt_line(" Store (Arg0, PICM)");
1686 dsdt_line("Scope (_SB)");
1688 for (bus = 0; bus < MAXBUSES; bus++)
1689 pci_bus_write_dsdt(bus);
1695 pci_bus_configured(int bus)
1697 assert(bus >= 0 && bus < MAXBUSES);
1698 return (pci_businfo[bus] != NULL);
1702 pci_msi_enabled(struct pci_devinst *pi)
1704 return (pi->pi_msi.enabled);
1708 pci_msi_maxmsgnum(struct pci_devinst *pi)
1710 if (pi->pi_msi.enabled)
1711 return (pi->pi_msi.maxmsgnum);
1717 pci_msix_enabled(struct pci_devinst *pi)
1720 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1724 pci_generate_msix(struct pci_devinst *pi, int index)
1726 struct msix_table_entry *mte;
1728 if (!pci_msix_enabled(pi))
1731 if (pi->pi_msix.function_mask)
1734 if (index >= pi->pi_msix.table_count)
1737 mte = &pi->pi_msix.table[index];
1738 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1739 /* XXX Set PBA bit if interrupt is disabled */
1740 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1745 pci_generate_msi(struct pci_devinst *pi, int index)
1748 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1749 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1750 pi->pi_msi.msg_data + index);
1755 pci_lintr_permitted(struct pci_devinst *pi)
1759 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1760 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1761 (cmd & PCIM_CMD_INTxDIS)));
1765 pci_lintr_request(struct pci_devinst *pi)
1768 struct slotinfo *si;
1769 int bestpin, bestcount, pin;
1771 bi = pci_businfo[pi->pi_bus];
1775 * Just allocate a pin from our slot. The pin will be
1776 * assigned IRQs later when interrupts are routed.
1778 si = &bi->slotinfo[pi->pi_slot];
1780 bestcount = si->si_intpins[0].ii_count;
1781 for (pin = 1; pin < 4; pin++) {
1782 if (si->si_intpins[pin].ii_count < bestcount) {
1784 bestcount = si->si_intpins[pin].ii_count;
1788 si->si_intpins[bestpin].ii_count++;
1789 pi->pi_lintr.pin = bestpin + 1;
1790 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1794 pci_lintr_route(struct pci_devinst *pi)
1797 struct intxinfo *ii;
1799 if (pi->pi_lintr.pin == 0)
1802 bi = pci_businfo[pi->pi_bus];
1804 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1807 * Attempt to allocate an I/O APIC pin for this intpin if one
1808 * is not yet assigned.
1810 if (ii->ii_ioapic_irq == 0)
1811 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi);
1812 assert(ii->ii_ioapic_irq > 0);
1815 * Attempt to allocate a PIRQ pin for this intpin if one is
1818 if (ii->ii_pirq_pin == 0)
1819 ii->ii_pirq_pin = pirq_alloc_pin(pi);
1820 assert(ii->ii_pirq_pin > 0);
1822 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1823 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1824 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1828 pci_lintr_assert(struct pci_devinst *pi)
1831 assert(pi->pi_lintr.pin > 0);
1833 pthread_mutex_lock(&pi->pi_lintr.lock);
1834 if (pi->pi_lintr.state == IDLE) {
1835 if (pci_lintr_permitted(pi)) {
1836 pi->pi_lintr.state = ASSERTED;
1839 pi->pi_lintr.state = PENDING;
1841 pthread_mutex_unlock(&pi->pi_lintr.lock);
1845 pci_lintr_deassert(struct pci_devinst *pi)
1848 assert(pi->pi_lintr.pin > 0);
1850 pthread_mutex_lock(&pi->pi_lintr.lock);
1851 if (pi->pi_lintr.state == ASSERTED) {
1852 pi->pi_lintr.state = IDLE;
1853 pci_irq_deassert(pi);
1854 } else if (pi->pi_lintr.state == PENDING)
1855 pi->pi_lintr.state = IDLE;
1856 pthread_mutex_unlock(&pi->pi_lintr.lock);
1860 pci_lintr_update(struct pci_devinst *pi)
1863 pthread_mutex_lock(&pi->pi_lintr.lock);
1864 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1865 pci_irq_deassert(pi);
1866 pi->pi_lintr.state = PENDING;
1867 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1868 pi->pi_lintr.state = ASSERTED;
1871 pthread_mutex_unlock(&pi->pi_lintr.lock);
1875 pci_count_lintr(int bus)
1877 int count, slot, pin;
1878 struct slotinfo *slotinfo;
1881 if (pci_businfo[bus] != NULL) {
1882 for (slot = 0; slot < MAXSLOTS; slot++) {
1883 slotinfo = &pci_businfo[bus]->slotinfo[slot];
1884 for (pin = 0; pin < 4; pin++) {
1885 if (slotinfo->si_intpins[pin].ii_count != 0)
1894 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
1897 struct slotinfo *si;
1898 struct intxinfo *ii;
1901 if ((bi = pci_businfo[bus]) == NULL)
1904 for (slot = 0; slot < MAXSLOTS; slot++) {
1905 si = &bi->slotinfo[slot];
1906 for (pin = 0; pin < 4; pin++) {
1907 ii = &si->si_intpins[pin];
1908 if (ii->ii_count != 0)
1909 cb(bus, slot, pin + 1, ii->ii_pirq_pin,
1910 ii->ii_ioapic_irq, arg);
1916 * Return 1 if the emulated device in 'slot' is a multi-function device.
1917 * Return 0 otherwise.
1920 pci_emul_is_mfdev(int bus, int slot)
1923 struct slotinfo *si;
1927 if ((bi = pci_businfo[bus]) != NULL) {
1928 si = &bi->slotinfo[slot];
1929 for (f = 0; f < MAXFUNCS; f++) {
1930 if (si->si_funcs[f].fi_devi != NULL) {
1935 return (numfuncs > 1);
1939 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1940 * whether or not is a multi-function being emulated in the pci 'slot'.
1943 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
1947 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1948 mfdev = pci_emul_is_mfdev(bus, slot);
1958 *rv &= ~(PCIM_MFDEV << 16);
1960 *rv |= (PCIM_MFDEV << 16);
1968 * Update device state in response to changes to the PCI command
1972 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old)
1975 uint16_t changed, new;
1977 new = pci_get_cfgdata16(pi, PCIR_COMMAND);
1978 changed = old ^ new;
1981 * If the MMIO or I/O address space decoding has changed then
1982 * register/unregister all BARs that decode that address space.
1984 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) {
1985 switch (pi->pi_bar[i].type) {
1987 case PCIBAR_MEMHI64:
1990 /* I/O address space decoding changed? */
1991 if (changed & PCIM_CMD_PORTEN) {
1992 if (new & PCIM_CMD_PORTEN)
1993 register_bar(pi, i);
1995 unregister_bar(pi, i);
1999 /* skip (un-)register of ROM if it disabled */
2005 /* MMIO address space decoding changed? */
2006 if (changed & PCIM_CMD_MEMEN) {
2007 if (new & PCIM_CMD_MEMEN)
2008 register_bar(pi, i);
2010 unregister_bar(pi, i);
2019 * If INTx has been unmasked and is pending, assert the
2022 pci_lintr_update(pi);
2026 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
2029 uint32_t cmd, old, readonly;
2031 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
2034 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3.
2036 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are
2037 * 'write 1 to clear'. However these bits are not set to '1' by
2038 * any device emulation so it is simpler to treat them as readonly.
2040 rshift = (coff & 0x3) * 8;
2041 readonly = 0xFFFFF880 >> rshift;
2043 old = CFGREAD(pi, coff, bytes);
2045 new |= (old & readonly);
2046 CFGWRITE(pi, coff, new, bytes); /* update config */
2048 pci_emul_cmd_changed(pi, cmd);
2052 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
2053 int coff, int bytes, uint32_t *eax)
2056 struct slotinfo *si;
2057 struct pci_devinst *pi;
2058 struct pci_devemu *pe;
2060 uint64_t addr, bar, mask;
2062 if ((bi = pci_businfo[bus]) != NULL) {
2063 si = &bi->slotinfo[slot];
2064 pi = si->si_funcs[func].fi_devi;
2069 * Just return if there is no device at this slot:func or if the
2070 * the guest is doing an un-aligned access.
2072 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
2073 (coff & (bytes - 1)) != 0) {
2080 * Ignore all writes beyond the standard config space and return all
2083 if (coff >= PCI_REGMAX + 1) {
2087 * Extended capabilities begin at offset 256 in config
2088 * space. Absence of extended capabilities is signaled
2089 * with all 0s in the extended capability header at
2092 if (coff <= PCI_REGMAX + 4)
2104 /* Let the device emulation override the default handler */
2105 if (pe->pe_cfgread != NULL) {
2106 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes,
2113 *eax = CFGREAD(pi, coff, bytes);
2115 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
2117 /* Let the device emulation override the default handler */
2118 if (pe->pe_cfgwrite != NULL &&
2119 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
2123 * Special handling for write to BAR and ROM registers
2125 if (is_pcir_bar(coff) || is_pcir_bios(coff)) {
2127 * Ignore writes to BAR registers that are not
2130 if (bytes != 4 || (coff & 0x3) != 0)
2133 if (is_pcir_bar(coff)) {
2134 idx = (coff - PCIR_BAR(0)) / 4;
2135 } else if (is_pcir_bios(coff)) {
2138 errx(4, "%s: invalid BAR offset %d", __func__,
2142 mask = ~(pi->pi_bar[idx].size - 1);
2143 switch (pi->pi_bar[idx].type) {
2145 pi->pi_bar[idx].addr = bar = 0;
2150 bar = addr | pi->pi_bar[idx].lobits;
2152 * Register the new BAR value for interception
2154 if (addr != pi->pi_bar[idx].addr) {
2155 update_bar_address(pi, addr, idx,
2160 addr = bar = *eax & mask;
2161 bar |= pi->pi_bar[idx].lobits;
2162 if (addr != pi->pi_bar[idx].addr) {
2163 update_bar_address(pi, addr, idx,
2168 addr = bar = *eax & mask;
2169 bar |= pi->pi_bar[idx].lobits;
2170 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
2171 update_bar_address(pi, addr, idx,
2175 case PCIBAR_MEMHI64:
2176 mask = ~(pi->pi_bar[idx - 1].size - 1);
2177 addr = ((uint64_t)*eax << 32) & mask;
2179 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
2180 update_bar_address(pi, addr, idx - 1,
2185 addr = bar = *eax & mask;
2186 if (memen(pi) && romen(pi)) {
2187 unregister_bar(pi, idx);
2189 pi->pi_bar[idx].addr = addr;
2190 pi->pi_bar[idx].lobits = *eax &
2192 /* romen could have changed it value */
2193 if (memen(pi) && romen(pi)) {
2194 register_bar(pi, idx);
2196 bar |= pi->pi_bar[idx].lobits;
2201 pci_set_cfgdata32(pi, coff, bar);
2203 } else if (pci_emul_iscap(pi, coff)) {
2204 pci_emul_capwrite(pi, coff, bytes, *eax, 0, 0);
2205 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
2206 pci_emul_cmdsts_write(pi, coff, *eax, bytes);
2208 CFGWRITE(pi, coff, *eax, bytes);
2213 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
2216 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
2217 uint32_t *eax, void *arg)
2223 *eax = (bytes == 2) ? 0xffff : 0xff;
2228 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
2234 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
2235 cfgoff = (x & PCI_REGMAX) & ~0x03;
2236 cfgfunc = (x >> 8) & PCI_FUNCMAX;
2237 cfgslot = (x >> 11) & PCI_SLOTMAX;
2238 cfgbus = (x >> 16) & PCI_BUSMAX;
2243 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
2246 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
2247 uint32_t *eax, void *arg)
2251 assert(bytes == 1 || bytes == 2 || bytes == 4);
2253 coff = cfgoff + (port - CONF1_DATA_PORT);
2255 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
2258 /* Ignore accesses to cfgdata if not enabled by cfgaddr */
2265 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
2266 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
2267 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
2268 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
2270 #ifdef BHYVE_SNAPSHOT
2272 * Saves/restores PCI device emulated state. Returns 0 on success.
2275 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta)
2277 struct pci_devinst *pi;
2281 pi = meta->dev_data;
2283 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done);
2284 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done);
2285 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done);
2286 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done);
2288 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done);
2289 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done);
2290 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done);
2291 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done);
2292 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done);
2293 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done);
2294 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done);
2295 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done);
2297 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata),
2300 for (i = 0; i < nitems(pi->pi_bar); i++) {
2301 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done);
2302 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done);
2303 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done);
2306 /* Restore MSI-X table. */
2307 for (i = 0; i < pi->pi_msix.table_count; i++) {
2308 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr,
2310 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data,
2312 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control,
2321 pci_find_slotted_dev(const char *dev_name, struct pci_devemu **pde,
2322 struct pci_devinst **pdi)
2325 struct slotinfo *si;
2326 struct funcinfo *fi;
2327 int bus, slot, func;
2329 assert(dev_name != NULL);
2330 assert(pde != NULL);
2331 assert(pdi != NULL);
2333 for (bus = 0; bus < MAXBUSES; bus++) {
2334 if ((bi = pci_businfo[bus]) == NULL)
2337 for (slot = 0; slot < MAXSLOTS; slot++) {
2338 si = &bi->slotinfo[slot];
2339 for (func = 0; func < MAXFUNCS; func++) {
2340 fi = &si->si_funcs[func];
2341 if (fi->fi_pde == NULL)
2343 if (strcmp(dev_name, fi->fi_pde->pe_emu) != 0)
2357 pci_snapshot(struct vm_snapshot_meta *meta)
2359 struct pci_devemu *pde;
2360 struct pci_devinst *pdi;
2363 assert(meta->dev_name != NULL);
2365 ret = pci_find_slotted_dev(meta->dev_name, &pde, &pdi);
2367 fprintf(stderr, "%s: no such name: %s\r\n",
2368 __func__, meta->dev_name);
2369 memset(meta->buffer.buf_start, 0, meta->buffer.buf_size);
2373 meta->dev_data = pdi;
2375 if (pde->pe_snapshot == NULL) {
2376 fprintf(stderr, "%s: not implemented yet for: %s\r\n",
2377 __func__, meta->dev_name);
2381 ret = pci_snapshot_pci_dev(meta);
2383 fprintf(stderr, "%s: failed to snapshot pci dev\r\n",
2388 ret = (*pde->pe_snapshot)(meta);
2394 pci_pause(struct vmctx *ctx, const char *dev_name)
2396 struct pci_devemu *pde;
2397 struct pci_devinst *pdi;
2400 assert(dev_name != NULL);
2402 ret = pci_find_slotted_dev(dev_name, &pde, &pdi);
2405 * It is possible to call this function without
2406 * checking that the device is inserted first.
2408 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name);
2412 if (pde->pe_pause == NULL) {
2413 /* The pause/resume functionality is optional. */
2414 fprintf(stderr, "%s: not implemented for: %s\n",
2415 __func__, dev_name);
2419 return (*pde->pe_pause)(ctx, pdi);
2423 pci_resume(struct vmctx *ctx, const char *dev_name)
2425 struct pci_devemu *pde;
2426 struct pci_devinst *pdi;
2429 assert(dev_name != NULL);
2431 ret = pci_find_slotted_dev(dev_name, &pde, &pdi);
2434 * It is possible to call this function without
2435 * checking that the device is inserted first.
2437 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name);
2441 if (pde->pe_resume == NULL) {
2442 /* The pause/resume functionality is optional. */
2443 fprintf(stderr, "%s: not implemented for: %s\n",
2444 __func__, dev_name);
2448 return (*pde->pe_resume)(ctx, pdi);
2452 #define PCI_EMUL_TEST
2453 #ifdef PCI_EMUL_TEST
2455 * Define a dummy test device
2459 struct pci_emul_dsoftc {
2460 uint8_t ioregs[DIOSZ];
2461 uint8_t memregs[2][DMEMSZ];
2464 #define PCI_EMUL_MSI_MSGS 4
2465 #define PCI_EMUL_MSIX_MSGS 16
2468 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
2471 struct pci_emul_dsoftc *sc;
2473 sc = calloc(1, sizeof(struct pci_emul_dsoftc));
2477 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
2478 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
2479 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
2481 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
2484 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
2487 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
2490 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
2497 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2498 uint64_t offset, int size, uint64_t value)
2501 struct pci_emul_dsoftc *sc = pi->pi_arg;
2504 if (offset + size > DIOSZ) {
2505 printf("diow: iow too large, offset %ld size %d\n",
2511 sc->ioregs[offset] = value & 0xff;
2512 } else if (size == 2) {
2513 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
2514 } else if (size == 4) {
2515 *(uint32_t *)&sc->ioregs[offset] = value;
2517 printf("diow: iow unknown size %d\n", size);
2521 * Special magic value to generate an interrupt
2523 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2524 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2526 if (value == 0xabcdef) {
2527 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2528 pci_generate_msi(pi, i);
2532 if (baridx == 1 || baridx == 2) {
2533 if (offset + size > DMEMSZ) {
2534 printf("diow: memw too large, offset %ld size %d\n",
2539 i = baridx - 1; /* 'memregs' index */
2542 sc->memregs[i][offset] = value;
2543 } else if (size == 2) {
2544 *(uint16_t *)&sc->memregs[i][offset] = value;
2545 } else if (size == 4) {
2546 *(uint32_t *)&sc->memregs[i][offset] = value;
2547 } else if (size == 8) {
2548 *(uint64_t *)&sc->memregs[i][offset] = value;
2550 printf("diow: memw unknown size %d\n", size);
2554 * magic interrupt ??
2558 if (baridx > 2 || baridx < 0) {
2559 printf("diow: unknown bar idx %d\n", baridx);
2564 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2565 uint64_t offset, int size)
2567 struct pci_emul_dsoftc *sc = pi->pi_arg;
2572 if (offset + size > DIOSZ) {
2573 printf("dior: ior too large, offset %ld size %d\n",
2580 value = sc->ioregs[offset];
2581 } else if (size == 2) {
2582 value = *(uint16_t *) &sc->ioregs[offset];
2583 } else if (size == 4) {
2584 value = *(uint32_t *) &sc->ioregs[offset];
2586 printf("dior: ior unknown size %d\n", size);
2590 if (baridx == 1 || baridx == 2) {
2591 if (offset + size > DMEMSZ) {
2592 printf("dior: memr too large, offset %ld size %d\n",
2597 i = baridx - 1; /* 'memregs' index */
2600 value = sc->memregs[i][offset];
2601 } else if (size == 2) {
2602 value = *(uint16_t *) &sc->memregs[i][offset];
2603 } else if (size == 4) {
2604 value = *(uint32_t *) &sc->memregs[i][offset];
2605 } else if (size == 8) {
2606 value = *(uint64_t *) &sc->memregs[i][offset];
2608 printf("dior: ior unknown size %d\n", size);
2613 if (baridx > 2 || baridx < 0) {
2614 printf("dior: unknown bar idx %d\n", baridx);
2621 #ifdef BHYVE_SNAPSHOT
2623 pci_emul_snapshot(struct vm_snapshot_meta *meta)
2630 static const struct pci_devemu pci_dummy = {
2632 .pe_init = pci_emul_dinit,
2633 .pe_barwrite = pci_emul_diow,
2634 .pe_barread = pci_emul_dior,
2635 #ifdef BHYVE_SNAPSHOT
2636 .pe_snapshot = pci_emul_snapshot,
2639 PCI_EMUL_SET(pci_dummy);
2641 #endif /* PCI_EMUL_TEST */