2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/linker_set.h>
50 #include <machine/vmm.h>
51 #include <machine/vmm_snapshot.h>
64 #include "pci_passthru.h"
66 #define CONF1_ADDR_PORT 0x0cf8
67 #define CONF1_DATA_PORT 0x0cfc
69 #define CONF1_ENABLE 0x80000000ul
71 #define MAXBUSES (PCI_BUSMAX + 1)
72 #define MAXSLOTS (PCI_SLOTMAX + 1)
73 #define MAXFUNCS (PCI_FUNCMAX + 1)
75 #define GB (1024 * 1024 * 1024UL)
79 struct pci_devemu *fi_pde;
80 struct pci_devinst *fi_devi;
90 struct intxinfo si_intpins[4];
91 struct funcinfo si_funcs[MAXFUNCS];
95 uint16_t iobase, iolimit; /* I/O window */
96 uint32_t membase32, memlimit32; /* mmio window below 4GB */
97 uint64_t membase64, memlimit64; /* mmio window above 4GB */
98 struct slotinfo slotinfo[MAXSLOTS];
101 static struct businfo *pci_businfo[MAXBUSES];
103 SET_DECLARE(pci_devemu_set, struct pci_devemu);
105 static uint64_t pci_emul_iobase;
106 static uint8_t *pci_emul_rombase;
107 static uint64_t pci_emul_romoffset;
108 static uint8_t *pci_emul_romlim;
109 static uint64_t pci_emul_membase32;
110 static uint64_t pci_emul_membase64;
111 static uint64_t pci_emul_memlim64;
113 struct pci_bar_allocation {
114 TAILQ_ENTRY(pci_bar_allocation) chain;
115 struct pci_devinst *pdi;
117 enum pcibar_type type;
121 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars =
122 TAILQ_HEAD_INITIALIZER(pci_bars);
124 #define PCI_EMUL_IOBASE 0x2000
125 #define PCI_EMUL_IOLIMIT 0x10000
127 #define PCI_EMUL_ROMSIZE 0x10000000
129 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
130 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
131 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
134 * OVMF always uses 0xC0000000 as base address for 32 bit PCI MMIO. Don't
135 * change this address without changing it in OVMF.
137 #define PCI_EMUL_MEMBASE32 0xC0000000
138 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
139 #define PCI_EMUL_MEMSIZE64 (32*GB)
141 static struct pci_devemu *pci_emul_finddev(const char *name);
142 static void pci_lintr_route(struct pci_devinst *pi);
143 static void pci_lintr_update(struct pci_devinst *pi);
144 static void pci_cfgrw(int in, int bus, int slot, int func, int coff,
145 int bytes, uint32_t *val);
148 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
152 pci_set_cfgdata8(pi, coff, val);
154 pci_set_cfgdata16(pi, coff, val);
156 pci_set_cfgdata32(pi, coff, val);
159 static __inline uint32_t
160 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
164 return (pci_get_cfgdata8(pi, coff));
166 return (pci_get_cfgdata16(pi, coff));
168 return (pci_get_cfgdata32(pi, coff));
172 is_pcir_bar(int coff)
174 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1));
178 is_pcir_bios(int coff)
180 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4);
188 * Slot options are in the form:
190 * <bus>:<slot>:<func>,<emul>[,<config>]
191 * <slot>[:<func>],<emul>[,<config>]
195 * emul is a string describing the type of PCI device e.g. virtio-net
196 * config is an optional string, depending on the device, that can be
197 * used for configuration.
203 pci_parse_slot_usage(char *aopt)
206 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt);
210 * Helper function to parse a list of comma-separated options where
211 * each option is formatted as "name[=value]". If no value is
212 * provided, the option is treated as a boolean and is given a value
216 pci_parse_legacy_config(nvlist_t *nvl, const char *opt)
218 char *config, *name, *tofree, *value;
223 config = tofree = strdup(opt);
224 while ((name = strsep(&config, ",")) != NULL) {
225 value = strchr(name, '=');
229 set_config_value_node(nvl, name, value);
231 set_config_bool_node(nvl, name, true);
238 * PCI device configuration is stored in MIBs that encode the device's
241 * pci.<bus>.<slot>.<func>
243 * Where "bus", "slot", and "func" are all decimal values without
244 * leading zeroes. Each valid device must have a "device" node which
245 * identifies the driver model of the device.
247 * Device backends can provide a parser for the "config" string. If
248 * a custom parser is not provided, pci_parse_legacy_config() is used
249 * to parse the string.
252 pci_parse_slot(char *opt)
254 char node_name[sizeof("pci.XXX.XX.X")];
255 struct pci_devemu *pde;
256 char *emul, *config, *str, *cp;
257 int error, bnum, snum, fnum;
263 emul = config = NULL;
264 if ((cp = strchr(str, ',')) != NULL) {
267 if ((cp = strchr(emul, ',')) != NULL) {
272 pci_parse_slot_usage(opt);
276 /* <bus>:<slot>:<func> */
277 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
280 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
283 if (sscanf(str, "%d", &snum) != 1) {
289 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
290 fnum < 0 || fnum >= MAXFUNCS) {
291 pci_parse_slot_usage(opt);
295 pde = pci_emul_finddev(emul);
297 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum,
302 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum,
304 nvl = find_config_node(node_name);
306 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum,
310 nvl = create_config_node(node_name);
311 if (pde->pe_alias != NULL)
312 set_config_value_node(nvl, "device", pde->pe_alias);
314 set_config_value_node(nvl, "device", pde->pe_emu);
316 if (pde->pe_legacy_config != NULL)
317 error = pde->pe_legacy_config(nvl, config);
319 error = pci_parse_legacy_config(nvl, config);
326 pci_print_supported_devices(void)
328 struct pci_devemu **pdpp, *pdp;
330 SET_FOREACH(pdpp, pci_devemu_set) {
332 printf("%s\n", pdp->pe_emu);
337 pci_config_read_reg(const struct pcisel *const host_sel, nvlist_t *nvl,
338 const uint32_t reg, const uint8_t size, const uint32_t def)
341 const nvlist_t *pci_regs;
343 assert(size == 1 || size == 2 || size == 4);
345 pci_regs = find_relative_config_node(nvl, "pcireg");
346 if (pci_regs == NULL) {
352 config = get_config_value_node(pci_regs, "device");
355 config = get_config_value_node(pci_regs, "vendor");
358 config = get_config_value_node(pci_regs, "revid");
361 config = get_config_value_node(pci_regs, "subvendor");
364 config = get_config_value_node(pci_regs, "subdevice");
370 if (config == NULL) {
372 } else if (host_sel != NULL && strcmp(config, "host") == 0) {
373 return read_config(host_sel, reg, size);
375 return strtol(config, NULL, 16);
380 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
383 if (offset < pi->pi_msix.pba_offset)
386 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
394 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
397 int msix_entry_offset;
401 /* support only 4 or 8 byte writes */
402 if (size != 4 && size != 8)
406 * Return if table index is beyond what device supports
408 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
409 if (tab_index >= pi->pi_msix.table_count)
412 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
414 /* support only aligned writes */
415 if ((msix_entry_offset % size) != 0)
418 dest = (char *)(pi->pi_msix.table + tab_index);
419 dest += msix_entry_offset;
422 *((uint32_t *)dest) = value;
424 *((uint64_t *)dest) = value;
430 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
433 int msix_entry_offset;
435 uint64_t retval = ~0;
438 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
439 * table but we also allow 1 byte access to accommodate reads from
442 if (size != 1 && size != 4 && size != 8)
445 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
447 /* support only aligned reads */
448 if ((msix_entry_offset % size) != 0) {
452 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
454 if (tab_index < pi->pi_msix.table_count) {
455 /* valid MSI-X Table access */
456 dest = (char *)(pi->pi_msix.table + tab_index);
457 dest += msix_entry_offset;
460 retval = *((uint8_t *)dest);
462 retval = *((uint32_t *)dest);
464 retval = *((uint64_t *)dest);
465 } else if (pci_valid_pba_offset(pi, offset)) {
466 /* return 0 for PBA access */
474 pci_msix_table_bar(struct pci_devinst *pi)
477 if (pi->pi_msix.table != NULL)
478 return (pi->pi_msix.table_bar);
484 pci_msix_pba_bar(struct pci_devinst *pi)
487 if (pi->pi_msix.table != NULL)
488 return (pi->pi_msix.pba_bar);
494 pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port,
495 int bytes, uint32_t *eax, void *arg)
497 struct pci_devinst *pdi = arg;
498 struct pci_devemu *pe = pdi->pi_d;
504 for (i = 0; i <= PCI_BARMAX; i++) {
505 if (pdi->pi_bar[i].type == PCIBAR_IO &&
506 (uint64_t)port >= pdi->pi_bar[i].addr &&
507 (uint64_t)port + bytes <=
508 pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
509 offset = port - pdi->pi_bar[i].addr;
511 *eax = (*pe->pe_barread)(pdi, i,
514 (*pe->pe_barwrite)(pdi, i, offset,
523 pci_emul_mem_handler(struct vcpu *vcpu __unused, int dir,
524 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2)
526 struct pci_devinst *pdi = arg1;
527 struct pci_devemu *pe = pdi->pi_d;
529 int bidx = (int) arg2;
531 assert(bidx <= PCI_BARMAX);
532 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
533 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
534 assert(addr >= pdi->pi_bar[bidx].addr &&
535 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
537 offset = addr - pdi->pi_bar[bidx].addr;
539 if (dir == MEM_F_WRITE) {
541 (*pe->pe_barwrite)(pdi, bidx, offset,
542 4, *val & 0xffffffff);
543 (*pe->pe_barwrite)(pdi, bidx, offset + 4,
546 (*pe->pe_barwrite)(pdi, bidx, offset,
551 *val = (*pe->pe_barread)(pdi, bidx,
553 *val |= (*pe->pe_barread)(pdi, bidx,
554 offset + 4, 4) << 32;
556 *val = (*pe->pe_barread)(pdi, bidx,
566 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
571 assert((size & (size - 1)) == 0); /* must be a power of 2 */
573 base = roundup2(*baseptr, size);
575 if (base + size <= limit) {
577 *baseptr = base + size;
584 * Register (or unregister) the MMIO or I/O region associated with the BAR
585 * register 'idx' of an emulated pci device.
588 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
590 struct pci_devemu *pe;
592 struct inout_port iop;
596 switch (pi->pi_bar[idx].type) {
598 bzero(&iop, sizeof(struct inout_port));
599 iop.name = pi->pi_name;
600 iop.port = pi->pi_bar[idx].addr;
601 iop.size = pi->pi_bar[idx].size;
603 iop.flags = IOPORT_F_INOUT;
604 iop.handler = pci_emul_io_handler;
606 error = register_inout(&iop);
608 error = unregister_inout(&iop);
609 if (pe->pe_baraddr != NULL)
610 (*pe->pe_baraddr)(pi, idx, registration,
611 pi->pi_bar[idx].addr);
615 bzero(&mr, sizeof(struct mem_range));
616 mr.name = pi->pi_name;
617 mr.base = pi->pi_bar[idx].addr;
618 mr.size = pi->pi_bar[idx].size;
621 mr.handler = pci_emul_mem_handler;
624 error = register_mem(&mr);
626 error = unregister_mem(&mr);
627 if (pe->pe_baraddr != NULL)
628 (*pe->pe_baraddr)(pi, idx, registration,
629 pi->pi_bar[idx].addr);
633 if (pe->pe_baraddr != NULL)
634 (*pe->pe_baraddr)(pi, idx, registration,
635 pi->pi_bar[idx].addr);
645 unregister_bar(struct pci_devinst *pi, int idx)
648 modify_bar_registration(pi, idx, 0);
652 register_bar(struct pci_devinst *pi, int idx)
655 modify_bar_registration(pi, idx, 1);
658 /* Is the ROM enabled for the emulated pci device? */
660 romen(struct pci_devinst *pi)
662 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) ==
666 /* Are we decoding i/o port accesses for the emulated pci device? */
668 porten(struct pci_devinst *pi)
672 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
674 return (cmd & PCIM_CMD_PORTEN);
677 /* Are we decoding memory accesses for the emulated pci device? */
679 memen(struct pci_devinst *pi)
683 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
685 return (cmd & PCIM_CMD_MEMEN);
689 * Update the MMIO or I/O address that is decoded by the BAR register.
691 * If the pci device has enabled the address space decoding then intercept
692 * the address range decoded by the BAR register.
695 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
699 if (pi->pi_bar[idx].type == PCIBAR_IO)
705 unregister_bar(pi, idx);
710 pi->pi_bar[idx].addr = addr;
713 pi->pi_bar[idx].addr &= ~0xffffffffUL;
714 pi->pi_bar[idx].addr |= addr;
717 pi->pi_bar[idx].addr &= 0xffffffff;
718 pi->pi_bar[idx].addr |= addr;
725 register_bar(pi, idx);
729 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
732 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX));
733 assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX));
735 if ((size & (size - 1)) != 0)
736 size = 1UL << flsl(size); /* round up to a power of 2 */
738 /* Enforce minimum BAR sizes required by the PCI standard */
739 if (type == PCIBAR_IO) {
742 } else if (type == PCIBAR_ROM) {
743 if (size < ~PCIM_BIOS_ADDR_MASK + 1)
744 size = ~PCIM_BIOS_ADDR_MASK + 1;
751 * To reduce fragmentation of the MMIO space, we allocate the BARs by
752 * size. Therefore, don't allocate the BAR yet. We create a list of all
753 * BAR allocation which is sorted by BAR size. When all PCI devices are
754 * initialized, we will assign an address to the BARs.
757 /* create a new list entry */
758 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar));
759 memset(new_bar, 0, sizeof(*new_bar));
762 new_bar->type = type;
763 new_bar->size = size;
766 * Search for a BAR which size is lower than the size of our newly
769 struct pci_bar_allocation *bar = NULL;
770 TAILQ_FOREACH(bar, &pci_bars, chain) {
771 if (bar->size < size) {
778 * Either the list is empty or new BAR is the smallest BAR of
779 * the list. Append it to the end of our list.
781 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain);
784 * The found BAR is smaller than our new BAR. For that reason,
785 * insert our new BAR before the found BAR.
787 TAILQ_INSERT_BEFORE(bar, new_bar, chain);
791 * pci_passthru devices synchronize their physical and virtual command
792 * register on init. For that reason, the virtual cmd reg should be
793 * updated as early as possible.
798 enbit = PCIM_CMD_PORTEN;
802 enbit = PCIM_CMD_MEMEN;
809 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND);
810 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit);
816 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx,
817 const enum pcibar_type type, const uint64_t size)
820 uint64_t *baseptr, limit, addr, mask, lobits, bar;
825 addr = mask = lobits = 0;
828 baseptr = &pci_emul_iobase;
829 limit = PCI_EMUL_IOLIMIT;
830 mask = PCIM_BAR_IO_BASE;
831 lobits = PCIM_BAR_IO_SPACE;
836 * Some drivers do not work well if the 64-bit BAR is allocated
837 * above 4GB. Allow for this by allocating small requests under
838 * 4GB unless then allocation size is larger than some arbitrary
839 * number (128MB currently).
841 if (size > 128 * 1024 * 1024) {
842 baseptr = &pci_emul_membase64;
843 limit = pci_emul_memlim64;
844 mask = PCIM_BAR_MEM_BASE;
845 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
846 PCIM_BAR_MEM_PREFETCH;
848 baseptr = &pci_emul_membase32;
849 limit = PCI_EMUL_MEMLIMIT32;
850 mask = PCIM_BAR_MEM_BASE;
851 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
855 baseptr = &pci_emul_membase32;
856 limit = PCI_EMUL_MEMLIMIT32;
857 mask = PCIM_BAR_MEM_BASE;
858 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
861 /* do not claim memory for ROM. OVMF will do it for us. */
864 mask = PCIM_BIOS_ADDR_MASK;
868 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
872 if (baseptr != NULL) {
873 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
880 pdi->pi_bar[idx].type = type;
881 pdi->pi_bar[idx].addr = addr;
882 pdi->pi_bar[idx].size = size;
884 * passthru devices are using same lobits as physical device they set
887 if (pdi->pi_bar[idx].lobits != 0) {
888 lobits = pdi->pi_bar[idx].lobits;
890 pdi->pi_bar[idx].lobits = lobits;
893 /* Initialize the BAR register in config space */
894 bar = (addr & mask) | lobits;
895 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
897 if (type == PCIBAR_MEM64) {
898 assert(idx + 1 <= PCI_BARMAX);
899 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
900 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
903 if (type != PCIBAR_ROM) {
904 register_bar(pdi, idx);
911 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
914 /* allocate ROM space once on first call */
915 if (pci_emul_rombase == 0) {
916 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM,
917 "pcirom", PCI_EMUL_ROMSIZE);
918 if (pci_emul_rombase == MAP_FAILED) {
919 warnx("%s: failed to create rom segment", __func__);
922 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE;
923 pci_emul_romoffset = 0;
926 /* ROM size should be a power of 2 and greater than 2 KB */
927 const uint64_t rom_size = MAX(1UL << flsl(size),
928 ~PCIM_BIOS_ADDR_MASK + 1);
930 /* check if ROM fits into ROM space */
931 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) {
932 warnx("%s: no space left in rom segment:", __func__);
933 warnx("%16lu bytes left",
934 PCI_EMUL_ROMSIZE - pci_emul_romoffset);
935 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus,
936 pdi->pi_slot, pdi->pi_func);
940 /* allocate ROM BAR */
941 const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM,
947 *addr = pci_emul_rombase + pci_emul_romoffset;
949 /* save offset into ROM Space */
950 pdi->pi_romoffset = pci_emul_romoffset;
952 /* increase offset for next ROM */
953 pci_emul_romoffset += rom_size;
958 #define CAP_START_OFFSET 0x40
960 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
962 int i, capoff, reallen;
967 reallen = roundup2(caplen, 4); /* dword aligned */
969 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
970 if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
971 capoff = CAP_START_OFFSET;
973 capoff = pi->pi_capend + 1;
975 /* Check if we have enough space */
976 if (capoff + reallen > PCI_REGMAX + 1)
979 /* Set the previous capability pointer */
980 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
981 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
982 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
984 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
986 /* Copy the capability */
987 for (i = 0; i < caplen; i++)
988 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
990 /* Set the next capability pointer */
991 pci_set_cfgdata8(pi, capoff + 1, 0);
993 pi->pi_prevcap = capoff;
994 pi->pi_capend = capoff + reallen - 1;
998 static struct pci_devemu *
999 pci_emul_finddev(const char *name)
1001 struct pci_devemu **pdpp, *pdp;
1003 SET_FOREACH(pdpp, pci_devemu_set) {
1005 if (!strcmp(pdp->pe_emu, name)) {
1014 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
1015 int func, struct funcinfo *fi)
1017 struct pci_devinst *pdi;
1020 pdi = calloc(1, sizeof(struct pci_devinst));
1022 pdi->pi_vmctx = ctx;
1024 pdi->pi_slot = slot;
1025 pdi->pi_func = func;
1026 pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
1027 pdi->pi_lintr.pin = 0;
1028 pdi->pi_lintr.state = IDLE;
1029 pdi->pi_lintr.pirq_pin = 0;
1030 pdi->pi_lintr.ioapic_irq = 0;
1032 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
1034 /* Disable legacy interrupts */
1035 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
1036 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
1038 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN);
1040 err = (*pde->pe_init)(pdi, fi->fi_config);
1050 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
1054 /* Number of msi messages must be a power of 2 between 1 and 32 */
1055 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
1056 mmc = ffs(msgnum) - 1;
1058 bzero(msicap, sizeof(struct msicap));
1059 msicap->capid = PCIY_MSI;
1060 msicap->nextptr = nextptr;
1061 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
1065 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
1067 struct msicap msicap;
1069 pci_populate_msicap(&msicap, msgnum, 0);
1071 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
1075 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
1076 uint32_t msix_tab_size)
1079 assert(msix_tab_size % 4096 == 0);
1081 bzero(msixcap, sizeof(struct msixcap));
1082 msixcap->capid = PCIY_MSIX;
1085 * Message Control Register, all fields set to
1086 * zero except for the Table Size.
1087 * Note: Table size N is encoded as N-1
1089 msixcap->msgctrl = msgnum - 1;
1093 * - MSI-X table start at offset 0
1094 * - PBA table starts at a 4K aligned offset after the MSI-X table
1096 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
1097 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
1101 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
1105 assert(table_entries > 0);
1106 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
1108 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
1109 pi->pi_msix.table = calloc(1, table_size);
1111 /* set mask bit of vector control register */
1112 for (i = 0; i < table_entries; i++)
1113 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
1117 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
1120 struct msixcap msixcap;
1122 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
1123 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
1125 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
1127 /* Align table size to nearest 4K */
1128 tab_size = roundup2(tab_size, 4096);
1130 pi->pi_msix.table_bar = barnum;
1131 pi->pi_msix.pba_bar = barnum;
1132 pi->pi_msix.table_offset = 0;
1133 pi->pi_msix.table_count = msgnum;
1134 pi->pi_msix.pba_offset = tab_size;
1135 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
1137 pci_msix_table_init(pi, msgnum);
1139 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
1141 /* allocate memory for MSI-X Table and PBA */
1142 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
1143 tab_size + pi->pi_msix.pba_size);
1145 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
1150 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1151 int bytes, uint32_t val)
1153 uint16_t msgctrl, rwmask;
1156 off = offset - capoff;
1157 /* Message Control Register */
1158 if (off == 2 && bytes == 2) {
1159 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
1160 msgctrl = pci_get_cfgdata16(pi, offset);
1162 msgctrl |= val & rwmask;
1165 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
1166 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
1167 pci_lintr_update(pi);
1170 CFGWRITE(pi, offset, val, bytes);
1174 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1175 int bytes, uint32_t val)
1177 uint16_t msgctrl, rwmask, msgdata, mme;
1181 * If guest is writing to the message control register make sure
1182 * we do not overwrite read-only fields.
1184 if ((offset - capoff) == 2 && bytes == 2) {
1185 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
1186 msgctrl = pci_get_cfgdata16(pi, offset);
1188 msgctrl |= val & rwmask;
1191 CFGWRITE(pi, offset, val, bytes);
1193 msgctrl = pci_get_cfgdata16(pi, capoff + 2);
1194 addrlo = pci_get_cfgdata32(pi, capoff + 4);
1195 if (msgctrl & PCIM_MSICTRL_64BIT)
1196 msgdata = pci_get_cfgdata16(pi, capoff + 12);
1198 msgdata = pci_get_cfgdata16(pi, capoff + 8);
1200 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
1201 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
1202 if (pi->pi_msi.enabled) {
1203 pi->pi_msi.addr = addrlo;
1204 pi->pi_msi.msg_data = msgdata;
1205 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
1207 pi->pi_msi.maxmsgnum = 0;
1209 pci_lintr_update(pi);
1213 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset,
1214 int bytes, uint32_t val)
1217 /* XXX don't write to the readonly parts */
1218 CFGWRITE(pi, offset, val, bytes);
1221 #define PCIECAP_VERSION 0x2
1223 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
1226 struct pciecap pciecap;
1228 bzero(&pciecap, sizeof(pciecap));
1231 * Use the integrated endpoint type for endpoints on a root complex bus.
1233 * NB: bhyve currently only supports a single PCI bus that is the root
1234 * complex bus, so all endpoints are integrated.
1236 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0))
1237 type = PCIEM_TYPE_ROOT_INT_EP;
1239 pciecap.capid = PCIY_EXPRESS;
1240 pciecap.pcie_capabilities = PCIECAP_VERSION | type;
1241 if (type != PCIEM_TYPE_ROOT_INT_EP) {
1242 pciecap.link_capabilities = 0x411; /* gen1, x1 */
1243 pciecap.link_status = 0x11; /* gen1, x1 */
1246 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
1251 * This function assumes that 'coff' is in the capabilities region of the
1252 * config space. A capoff parameter of zero will force a search for the
1256 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val,
1257 uint8_t capoff, int capid)
1261 /* Do not allow un-aligned writes */
1262 if ((offset & (bytes - 1)) != 0)
1266 /* Find the capability that we want to update */
1267 capoff = CAP_START_OFFSET;
1269 nextoff = pci_get_cfgdata8(pi, capoff + 1);
1272 if (offset >= capoff && offset < nextoff)
1277 assert(offset >= capoff);
1278 capid = pci_get_cfgdata8(pi, capoff);
1282 * Capability ID and Next Capability Pointer are readonly.
1283 * However, some o/s's do 4-byte writes that include these.
1284 * For this case, trim the write back to 2 bytes and adjust
1287 if (offset == capoff || offset == capoff + 1) {
1288 if (offset == capoff && bytes == 4) {
1298 msicap_cfgwrite(pi, capoff, offset, bytes, val);
1301 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1304 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1312 pci_emul_iscap(struct pci_devinst *pi, int offset)
1316 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1317 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1318 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1325 pci_emul_fallback_handler(struct vcpu *vcpu __unused, int dir,
1326 uint64_t addr __unused, int size __unused, uint64_t *val,
1327 void *arg1 __unused, long arg2 __unused)
1330 * Ignore writes; return 0xff's for reads. The mem read code
1331 * will take care of truncating to the correct size.
1333 if (dir == MEM_F_READ) {
1334 *val = 0xffffffffffffffff;
1341 pci_emul_ecfg_handler(struct vcpu *vcpu __unused, int dir, uint64_t addr,
1342 int bytes, uint64_t *val, void *arg1 __unused, long arg2 __unused)
1344 int bus, slot, func, coff, in;
1346 coff = addr & 0xfff;
1347 func = (addr >> 12) & 0x7;
1348 slot = (addr >> 15) & 0x1f;
1349 bus = (addr >> 20) & 0xff;
1350 in = (dir == MEM_F_READ);
1353 pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val);
1361 return (PCI_EMUL_ECFG_BASE);
1364 #define BUSIO_ROUNDUP 32
1365 #define BUSMEM32_ROUNDUP (1024 * 1024)
1366 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024)
1369 init_pci(struct vmctx *ctx)
1371 char node_name[sizeof("pci.XXX.XX.X")];
1372 struct mem_range mr;
1373 struct pci_devemu *pde;
1375 struct slotinfo *si;
1376 struct funcinfo *fi;
1380 int bus, slot, func;
1383 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32)
1384 errx(EX_OSERR, "Invalid lowmem limit");
1386 pci_emul_iobase = PCI_EMUL_IOBASE;
1387 pci_emul_membase32 = PCI_EMUL_MEMBASE32;
1389 pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx);
1390 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64);
1391 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64;
1393 for (bus = 0; bus < MAXBUSES; bus++) {
1394 snprintf(node_name, sizeof(node_name), "pci.%d", bus);
1395 nvl = find_config_node(node_name);
1398 pci_businfo[bus] = calloc(1, sizeof(struct businfo));
1399 bi = pci_businfo[bus];
1402 * Keep track of the i/o and memory resources allocated to
1405 bi->iobase = pci_emul_iobase;
1406 bi->membase32 = pci_emul_membase32;
1407 bi->membase64 = pci_emul_membase64;
1409 /* first run: init devices */
1410 for (slot = 0; slot < MAXSLOTS; slot++) {
1411 si = &bi->slotinfo[slot];
1412 for (func = 0; func < MAXFUNCS; func++) {
1413 fi = &si->si_funcs[func];
1414 snprintf(node_name, sizeof(node_name),
1415 "pci.%d.%d.%d", bus, slot, func);
1416 nvl = find_config_node(node_name);
1420 fi->fi_config = nvl;
1421 emul = get_config_value_node(nvl, "device");
1423 EPRINTLN("pci slot %d:%d:%d: missing "
1424 "\"device\" value", bus, slot, func);
1427 pde = pci_emul_finddev(emul);
1429 EPRINTLN("pci slot %d:%d:%d: unknown "
1430 "device \"%s\"", bus, slot, func,
1434 if (pde->pe_alias != NULL) {
1435 EPRINTLN("pci slot %d:%d:%d: legacy "
1436 "device \"%s\", use \"%s\" instead",
1437 bus, slot, func, emul,
1442 error = pci_emul_init(ctx, pde, bus, slot,
1449 /* second run: assign BARs and free list */
1450 struct pci_bar_allocation *bar;
1451 struct pci_bar_allocation *bar_tmp;
1452 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) {
1453 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type,
1457 TAILQ_INIT(&pci_bars);
1460 * Add some slop to the I/O and memory resources decoded by
1461 * this bus to give a guest some flexibility if it wants to
1462 * reprogram the BARs.
1464 pci_emul_iobase += BUSIO_ROUNDUP;
1465 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1466 bi->iolimit = pci_emul_iobase;
1468 pci_emul_membase32 += BUSMEM32_ROUNDUP;
1469 pci_emul_membase32 = roundup2(pci_emul_membase32,
1471 bi->memlimit32 = pci_emul_membase32;
1473 pci_emul_membase64 += BUSMEM64_ROUNDUP;
1474 pci_emul_membase64 = roundup2(pci_emul_membase64,
1476 bi->memlimit64 = pci_emul_membase64;
1480 * PCI backends are initialized before routing INTx interrupts
1481 * so that LPC devices are able to reserve ISA IRQs before
1482 * routing PIRQ pins.
1484 for (bus = 0; bus < MAXBUSES; bus++) {
1485 if ((bi = pci_businfo[bus]) == NULL)
1488 for (slot = 0; slot < MAXSLOTS; slot++) {
1489 si = &bi->slotinfo[slot];
1490 for (func = 0; func < MAXFUNCS; func++) {
1491 fi = &si->si_funcs[func];
1492 if (fi->fi_devi == NULL)
1494 pci_lintr_route(fi->fi_devi);
1501 * The guest physical memory map looks like the following:
1502 * [0, lowmem) guest system memory
1503 * [lowmem, 0xC0000000) memory hole (may be absent)
1504 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation)
1505 * [0xE0000000, 0xF0000000) PCI extended config window
1506 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
1507 * [4GB, 4GB + highmem)
1511 * Accesses to memory addresses that are not allocated to system
1512 * memory or PCI devices return 0xff's.
1514 lowmem = vm_get_lowmem_size(ctx);
1515 bzero(&mr, sizeof(struct mem_range));
1516 mr.name = "PCI hole";
1517 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1519 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1520 mr.handler = pci_emul_fallback_handler;
1521 error = register_mem_fallback(&mr);
1524 /* PCI extended config space */
1525 bzero(&mr, sizeof(struct mem_range));
1526 mr.name = "PCI ECFG";
1527 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1528 mr.base = PCI_EMUL_ECFG_BASE;
1529 mr.size = PCI_EMUL_ECFG_SIZE;
1530 mr.handler = pci_emul_ecfg_handler;
1531 error = register_mem(&mr);
1538 pci_apic_prt_entry(int bus __unused, int slot, int pin, int pirq_pin __unused,
1539 int ioapic_irq, void *arg __unused)
1542 dsdt_line(" Package ()");
1544 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1545 dsdt_line(" 0x%02X,", pin - 1);
1546 dsdt_line(" Zero,");
1547 dsdt_line(" 0x%X", ioapic_irq);
1552 pci_pirq_prt_entry(int bus __unused, int slot, int pin, int pirq_pin,
1553 int ioapic_irq __unused, void *arg __unused)
1557 name = lpc_pirq_name(pirq_pin);
1560 dsdt_line(" Package ()");
1562 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1563 dsdt_line(" 0x%02X,", pin - 1);
1564 dsdt_line(" %s,", name);
1571 * A bhyve virtual machine has a flat PCI hierarchy with a root port
1572 * corresponding to each PCI bus.
1575 pci_bus_write_dsdt(int bus)
1578 struct slotinfo *si;
1579 struct pci_devinst *pi;
1580 int count, func, slot;
1583 * If there are no devices on this 'bus' then just return.
1585 if ((bi = pci_businfo[bus]) == NULL) {
1587 * Bus 0 is special because it decodes the I/O ports used
1588 * for PCI config space access even if there are no devices
1595 dsdt_line(" Device (PC%02X)", bus);
1597 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))");
1599 dsdt_line(" Method (_BBN, 0, NotSerialized)");
1601 dsdt_line(" Return (0x%08X)", bus);
1603 dsdt_line(" Name (_CRS, ResourceTemplate ()");
1605 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, "
1606 "MaxFixed, PosDecode,");
1607 dsdt_line(" 0x0000, // Granularity");
1608 dsdt_line(" 0x%04X, // Range Minimum", bus);
1609 dsdt_line(" 0x%04X, // Range Maximum", bus);
1610 dsdt_line(" 0x0000, // Translation Offset");
1611 dsdt_line(" 0x0001, // Length");
1616 dsdt_fixed_ioport(0xCF8, 8);
1619 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1620 "PosDecode, EntireRange,");
1621 dsdt_line(" 0x0000, // Granularity");
1622 dsdt_line(" 0x0000, // Range Minimum");
1623 dsdt_line(" 0x0CF7, // Range Maximum");
1624 dsdt_line(" 0x0000, // Translation Offset");
1625 dsdt_line(" 0x0CF8, // Length");
1626 dsdt_line(" ,, , TypeStatic)");
1628 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1629 "PosDecode, EntireRange,");
1630 dsdt_line(" 0x0000, // Granularity");
1631 dsdt_line(" 0x0D00, // Range Minimum");
1632 dsdt_line(" 0x%04X, // Range Maximum",
1633 PCI_EMUL_IOBASE - 1);
1634 dsdt_line(" 0x0000, // Translation Offset");
1635 dsdt_line(" 0x%04X, // Length",
1636 PCI_EMUL_IOBASE - 0x0D00);
1637 dsdt_line(" ,, , TypeStatic)");
1647 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1648 "PosDecode, EntireRange,");
1649 dsdt_line(" 0x0000, // Granularity");
1650 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase);
1651 dsdt_line(" 0x%04X, // Range Maximum",
1653 dsdt_line(" 0x0000, // Translation Offset");
1654 dsdt_line(" 0x%04X, // Length",
1655 bi->iolimit - bi->iobase);
1656 dsdt_line(" ,, , TypeStatic)");
1658 /* mmio window (32-bit) */
1659 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, "
1660 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1661 dsdt_line(" 0x00000000, // Granularity");
1662 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32);
1663 dsdt_line(" 0x%08X, // Range Maximum\n",
1664 bi->memlimit32 - 1);
1665 dsdt_line(" 0x00000000, // Translation Offset");
1666 dsdt_line(" 0x%08X, // Length\n",
1667 bi->memlimit32 - bi->membase32);
1668 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1670 /* mmio window (64-bit) */
1671 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, "
1672 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1673 dsdt_line(" 0x0000000000000000, // Granularity");
1674 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64);
1675 dsdt_line(" 0x%016lX, // Range Maximum\n",
1676 bi->memlimit64 - 1);
1677 dsdt_line(" 0x0000000000000000, // Translation Offset");
1678 dsdt_line(" 0x%016lX, // Length\n",
1679 bi->memlimit64 - bi->membase64);
1680 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1683 count = pci_count_lintr(bus);
1686 dsdt_line("Name (PPRT, Package ()");
1688 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1690 dsdt_line("Name (APRT, Package ()");
1692 pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1694 dsdt_line("Method (_PRT, 0, NotSerialized)");
1696 dsdt_line(" If (PICM)");
1698 dsdt_line(" Return (APRT)");
1702 dsdt_line(" Return (PPRT)");
1709 for (slot = 0; slot < MAXSLOTS; slot++) {
1710 si = &bi->slotinfo[slot];
1711 for (func = 0; func < MAXFUNCS; func++) {
1712 pi = si->si_funcs[func].fi_devi;
1713 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1714 pi->pi_d->pe_write_dsdt(pi);
1723 pci_write_dsdt(void)
1728 dsdt_line("Name (PICM, 0x00)");
1729 dsdt_line("Method (_PIC, 1, NotSerialized)");
1731 dsdt_line(" Store (Arg0, PICM)");
1734 dsdt_line("Scope (_SB)");
1736 for (bus = 0; bus < MAXBUSES; bus++)
1737 pci_bus_write_dsdt(bus);
1743 pci_bus_configured(int bus)
1745 assert(bus >= 0 && bus < MAXBUSES);
1746 return (pci_businfo[bus] != NULL);
1750 pci_msi_enabled(struct pci_devinst *pi)
1752 return (pi->pi_msi.enabled);
1756 pci_msi_maxmsgnum(struct pci_devinst *pi)
1758 if (pi->pi_msi.enabled)
1759 return (pi->pi_msi.maxmsgnum);
1765 pci_msix_enabled(struct pci_devinst *pi)
1768 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1772 pci_generate_msix(struct pci_devinst *pi, int index)
1774 struct msix_table_entry *mte;
1776 if (!pci_msix_enabled(pi))
1779 if (pi->pi_msix.function_mask)
1782 if (index >= pi->pi_msix.table_count)
1785 mte = &pi->pi_msix.table[index];
1786 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1787 /* XXX Set PBA bit if interrupt is disabled */
1788 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1793 pci_generate_msi(struct pci_devinst *pi, int index)
1796 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1797 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1798 pi->pi_msi.msg_data + index);
1803 pci_lintr_permitted(struct pci_devinst *pi)
1807 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1808 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1809 (cmd & PCIM_CMD_INTxDIS)));
1813 pci_lintr_request(struct pci_devinst *pi)
1816 struct slotinfo *si;
1817 int bestpin, bestcount, pin;
1819 bi = pci_businfo[pi->pi_bus];
1823 * Just allocate a pin from our slot. The pin will be
1824 * assigned IRQs later when interrupts are routed.
1826 si = &bi->slotinfo[pi->pi_slot];
1828 bestcount = si->si_intpins[0].ii_count;
1829 for (pin = 1; pin < 4; pin++) {
1830 if (si->si_intpins[pin].ii_count < bestcount) {
1832 bestcount = si->si_intpins[pin].ii_count;
1836 si->si_intpins[bestpin].ii_count++;
1837 pi->pi_lintr.pin = bestpin + 1;
1838 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1842 pci_lintr_route(struct pci_devinst *pi)
1845 struct intxinfo *ii;
1847 if (pi->pi_lintr.pin == 0)
1850 bi = pci_businfo[pi->pi_bus];
1852 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1855 * Attempt to allocate an I/O APIC pin for this intpin if one
1856 * is not yet assigned.
1858 if (ii->ii_ioapic_irq == 0)
1859 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi);
1860 assert(ii->ii_ioapic_irq > 0);
1863 * Attempt to allocate a PIRQ pin for this intpin if one is
1866 if (ii->ii_pirq_pin == 0)
1867 ii->ii_pirq_pin = pirq_alloc_pin(pi);
1868 assert(ii->ii_pirq_pin > 0);
1870 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1871 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1872 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1876 pci_lintr_assert(struct pci_devinst *pi)
1879 assert(pi->pi_lintr.pin > 0);
1881 pthread_mutex_lock(&pi->pi_lintr.lock);
1882 if (pi->pi_lintr.state == IDLE) {
1883 if (pci_lintr_permitted(pi)) {
1884 pi->pi_lintr.state = ASSERTED;
1887 pi->pi_lintr.state = PENDING;
1889 pthread_mutex_unlock(&pi->pi_lintr.lock);
1893 pci_lintr_deassert(struct pci_devinst *pi)
1896 assert(pi->pi_lintr.pin > 0);
1898 pthread_mutex_lock(&pi->pi_lintr.lock);
1899 if (pi->pi_lintr.state == ASSERTED) {
1900 pi->pi_lintr.state = IDLE;
1901 pci_irq_deassert(pi);
1902 } else if (pi->pi_lintr.state == PENDING)
1903 pi->pi_lintr.state = IDLE;
1904 pthread_mutex_unlock(&pi->pi_lintr.lock);
1908 pci_lintr_update(struct pci_devinst *pi)
1911 pthread_mutex_lock(&pi->pi_lintr.lock);
1912 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1913 pci_irq_deassert(pi);
1914 pi->pi_lintr.state = PENDING;
1915 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1916 pi->pi_lintr.state = ASSERTED;
1919 pthread_mutex_unlock(&pi->pi_lintr.lock);
1923 pci_count_lintr(int bus)
1925 int count, slot, pin;
1926 struct slotinfo *slotinfo;
1929 if (pci_businfo[bus] != NULL) {
1930 for (slot = 0; slot < MAXSLOTS; slot++) {
1931 slotinfo = &pci_businfo[bus]->slotinfo[slot];
1932 for (pin = 0; pin < 4; pin++) {
1933 if (slotinfo->si_intpins[pin].ii_count != 0)
1942 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
1945 struct slotinfo *si;
1946 struct intxinfo *ii;
1949 if ((bi = pci_businfo[bus]) == NULL)
1952 for (slot = 0; slot < MAXSLOTS; slot++) {
1953 si = &bi->slotinfo[slot];
1954 for (pin = 0; pin < 4; pin++) {
1955 ii = &si->si_intpins[pin];
1956 if (ii->ii_count != 0)
1957 cb(bus, slot, pin + 1, ii->ii_pirq_pin,
1958 ii->ii_ioapic_irq, arg);
1964 * Return 1 if the emulated device in 'slot' is a multi-function device.
1965 * Return 0 otherwise.
1968 pci_emul_is_mfdev(int bus, int slot)
1971 struct slotinfo *si;
1975 if ((bi = pci_businfo[bus]) != NULL) {
1976 si = &bi->slotinfo[slot];
1977 for (f = 0; f < MAXFUNCS; f++) {
1978 if (si->si_funcs[f].fi_devi != NULL) {
1983 return (numfuncs > 1);
1987 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1988 * whether or not is a multi-function being emulated in the pci 'slot'.
1991 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
1995 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1996 mfdev = pci_emul_is_mfdev(bus, slot);
2006 *rv &= ~(PCIM_MFDEV << 16);
2008 *rv |= (PCIM_MFDEV << 16);
2016 * Update device state in response to changes to the PCI command
2020 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old)
2023 uint16_t changed, new;
2025 new = pci_get_cfgdata16(pi, PCIR_COMMAND);
2026 changed = old ^ new;
2029 * If the MMIO or I/O address space decoding has changed then
2030 * register/unregister all BARs that decode that address space.
2032 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) {
2033 switch (pi->pi_bar[i].type) {
2035 case PCIBAR_MEMHI64:
2038 /* I/O address space decoding changed? */
2039 if (changed & PCIM_CMD_PORTEN) {
2040 if (new & PCIM_CMD_PORTEN)
2041 register_bar(pi, i);
2043 unregister_bar(pi, i);
2047 /* skip (un-)register of ROM if it disabled */
2053 /* MMIO address space decoding changed? */
2054 if (changed & PCIM_CMD_MEMEN) {
2055 if (new & PCIM_CMD_MEMEN)
2056 register_bar(pi, i);
2058 unregister_bar(pi, i);
2067 * If INTx has been unmasked and is pending, assert the
2070 pci_lintr_update(pi);
2074 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
2077 uint32_t cmd, old, readonly;
2079 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
2082 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3.
2084 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are
2085 * 'write 1 to clear'. However these bits are not set to '1' by
2086 * any device emulation so it is simpler to treat them as readonly.
2088 rshift = (coff & 0x3) * 8;
2089 readonly = 0xFFFFF880 >> rshift;
2091 old = CFGREAD(pi, coff, bytes);
2093 new |= (old & readonly);
2094 CFGWRITE(pi, coff, new, bytes); /* update config */
2096 pci_emul_cmd_changed(pi, cmd);
2100 pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes,
2104 struct slotinfo *si;
2105 struct pci_devinst *pi;
2106 struct pci_devemu *pe;
2108 uint64_t addr, bar, mask;
2110 if ((bi = pci_businfo[bus]) != NULL) {
2111 si = &bi->slotinfo[slot];
2112 pi = si->si_funcs[func].fi_devi;
2117 * Just return if there is no device at this slot:func or if the
2118 * the guest is doing an un-aligned access.
2120 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
2121 (coff & (bytes - 1)) != 0) {
2128 * Ignore all writes beyond the standard config space and return all
2131 if (coff >= PCI_REGMAX + 1) {
2135 * Extended capabilities begin at offset 256 in config
2136 * space. Absence of extended capabilities is signaled
2137 * with all 0s in the extended capability header at
2140 if (coff <= PCI_REGMAX + 4)
2152 /* Let the device emulation override the default handler */
2153 if (pe->pe_cfgread != NULL) {
2154 needcfg = pe->pe_cfgread(pi, coff, bytes, eax);
2160 *eax = CFGREAD(pi, coff, bytes);
2162 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
2164 /* Let the device emulation override the default handler */
2165 if (pe->pe_cfgwrite != NULL &&
2166 (*pe->pe_cfgwrite)(pi, coff, bytes, *eax) == 0)
2170 * Special handling for write to BAR and ROM registers
2172 if (is_pcir_bar(coff) || is_pcir_bios(coff)) {
2174 * Ignore writes to BAR registers that are not
2177 if (bytes != 4 || (coff & 0x3) != 0)
2180 if (is_pcir_bar(coff)) {
2181 idx = (coff - PCIR_BAR(0)) / 4;
2182 } else if (is_pcir_bios(coff)) {
2185 errx(4, "%s: invalid BAR offset %d", __func__,
2189 mask = ~(pi->pi_bar[idx].size - 1);
2190 switch (pi->pi_bar[idx].type) {
2192 pi->pi_bar[idx].addr = bar = 0;
2197 bar = addr | pi->pi_bar[idx].lobits;
2199 * Register the new BAR value for interception
2201 if (addr != pi->pi_bar[idx].addr) {
2202 update_bar_address(pi, addr, idx,
2207 addr = bar = *eax & mask;
2208 bar |= pi->pi_bar[idx].lobits;
2209 if (addr != pi->pi_bar[idx].addr) {
2210 update_bar_address(pi, addr, idx,
2215 addr = bar = *eax & mask;
2216 bar |= pi->pi_bar[idx].lobits;
2217 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
2218 update_bar_address(pi, addr, idx,
2222 case PCIBAR_MEMHI64:
2223 mask = ~(pi->pi_bar[idx - 1].size - 1);
2224 addr = ((uint64_t)*eax << 32) & mask;
2226 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
2227 update_bar_address(pi, addr, idx - 1,
2232 addr = bar = *eax & mask;
2233 if (memen(pi) && romen(pi)) {
2234 unregister_bar(pi, idx);
2236 pi->pi_bar[idx].addr = addr;
2237 pi->pi_bar[idx].lobits = *eax &
2239 /* romen could have changed it value */
2240 if (memen(pi) && romen(pi)) {
2241 register_bar(pi, idx);
2243 bar |= pi->pi_bar[idx].lobits;
2248 pci_set_cfgdata32(pi, coff, bar);
2250 } else if (pci_emul_iscap(pi, coff)) {
2251 pci_emul_capwrite(pi, coff, bytes, *eax, 0, 0);
2252 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
2253 pci_emul_cmdsts_write(pi, coff, *eax, bytes);
2255 CFGWRITE(pi, coff, *eax, bytes);
2260 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
2263 pci_emul_cfgaddr(struct vmctx *ctx __unused, int in,
2264 int port __unused, int bytes, uint32_t *eax, void *arg __unused)
2270 *eax = (bytes == 2) ? 0xffff : 0xff;
2275 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
2281 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
2282 cfgoff = (x & PCI_REGMAX) & ~0x03;
2283 cfgfunc = (x >> 8) & PCI_FUNCMAX;
2284 cfgslot = (x >> 11) & PCI_SLOTMAX;
2285 cfgbus = (x >> 16) & PCI_BUSMAX;
2290 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
2293 pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port,
2294 int bytes, uint32_t *eax, void *arg __unused)
2298 assert(bytes == 1 || bytes == 2 || bytes == 4);
2300 coff = cfgoff + (port - CONF1_DATA_PORT);
2302 pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax);
2304 /* Ignore accesses to cfgdata if not enabled by cfgaddr */
2311 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
2312 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
2313 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
2314 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
2316 #ifdef BHYVE_SNAPSHOT
2318 * Saves/restores PCI device emulated state. Returns 0 on success.
2321 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta)
2323 struct pci_devinst *pi;
2327 pi = meta->dev_data;
2329 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done);
2330 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done);
2331 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done);
2332 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done);
2334 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done);
2335 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done);
2336 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done);
2337 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done);
2338 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done);
2339 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done);
2340 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done);
2341 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done);
2343 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata),
2346 for (i = 0; i < (int)nitems(pi->pi_bar); i++) {
2347 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done);
2348 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done);
2349 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done);
2352 /* Restore MSI-X table. */
2353 for (i = 0; i < pi->pi_msix.table_count; i++) {
2354 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr,
2356 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data,
2358 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control,
2367 pci_find_slotted_dev(const char *dev_name, struct pci_devemu **pde,
2368 struct pci_devinst **pdi)
2371 struct slotinfo *si;
2372 struct funcinfo *fi;
2373 int bus, slot, func;
2375 assert(dev_name != NULL);
2376 assert(pde != NULL);
2377 assert(pdi != NULL);
2379 for (bus = 0; bus < MAXBUSES; bus++) {
2380 if ((bi = pci_businfo[bus]) == NULL)
2383 for (slot = 0; slot < MAXSLOTS; slot++) {
2384 si = &bi->slotinfo[slot];
2385 for (func = 0; func < MAXFUNCS; func++) {
2386 fi = &si->si_funcs[func];
2387 if (fi->fi_pde == NULL)
2389 if (strcmp(dev_name, fi->fi_pde->pe_emu) != 0)
2403 pci_snapshot(struct vm_snapshot_meta *meta)
2405 struct pci_devemu *pde;
2406 struct pci_devinst *pdi;
2409 assert(meta->dev_name != NULL);
2411 ret = pci_find_slotted_dev(meta->dev_name, &pde, &pdi);
2413 fprintf(stderr, "%s: no such name: %s\r\n",
2414 __func__, meta->dev_name);
2415 memset(meta->buffer.buf_start, 0, meta->buffer.buf_size);
2419 meta->dev_data = pdi;
2421 if (pde->pe_snapshot == NULL) {
2422 fprintf(stderr, "%s: not implemented yet for: %s\r\n",
2423 __func__, meta->dev_name);
2427 ret = pci_snapshot_pci_dev(meta);
2429 fprintf(stderr, "%s: failed to snapshot pci dev\r\n",
2434 ret = (*pde->pe_snapshot)(meta);
2440 pci_pause(const char *dev_name)
2442 struct pci_devemu *pde;
2443 struct pci_devinst *pdi;
2446 assert(dev_name != NULL);
2448 ret = pci_find_slotted_dev(dev_name, &pde, &pdi);
2451 * It is possible to call this function without
2452 * checking that the device is inserted first.
2454 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name);
2458 if (pde->pe_pause == NULL) {
2459 /* The pause/resume functionality is optional. */
2460 fprintf(stderr, "%s: not implemented for: %s\n",
2461 __func__, dev_name);
2465 return (*pde->pe_pause)(pdi);
2469 pci_resume(const char *dev_name)
2471 struct pci_devemu *pde;
2472 struct pci_devinst *pdi;
2475 assert(dev_name != NULL);
2477 ret = pci_find_slotted_dev(dev_name, &pde, &pdi);
2480 * It is possible to call this function without
2481 * checking that the device is inserted first.
2483 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name);
2487 if (pde->pe_resume == NULL) {
2488 /* The pause/resume functionality is optional. */
2489 fprintf(stderr, "%s: not implemented for: %s\n",
2490 __func__, dev_name);
2494 return (*pde->pe_resume)(pdi);
2498 #define PCI_EMUL_TEST
2499 #ifdef PCI_EMUL_TEST
2501 * Define a dummy test device
2505 struct pci_emul_dsoftc {
2506 uint8_t ioregs[DIOSZ];
2507 uint8_t memregs[2][DMEMSZ];
2510 #define PCI_EMUL_MSI_MSGS 4
2511 #define PCI_EMUL_MSIX_MSGS 16
2514 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused)
2517 struct pci_emul_dsoftc *sc;
2519 sc = calloc(1, sizeof(struct pci_emul_dsoftc));
2523 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
2524 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
2525 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
2527 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
2530 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
2533 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
2536 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
2543 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2547 struct pci_emul_dsoftc *sc = pi->pi_arg;
2550 if (offset + size > DIOSZ) {
2551 printf("diow: iow too large, offset %ld size %d\n",
2557 sc->ioregs[offset] = value & 0xff;
2558 } else if (size == 2) {
2559 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
2560 } else if (size == 4) {
2561 *(uint32_t *)&sc->ioregs[offset] = value;
2563 printf("diow: iow unknown size %d\n", size);
2567 * Special magic value to generate an interrupt
2569 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2570 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2572 if (value == 0xabcdef) {
2573 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2574 pci_generate_msi(pi, i);
2578 if (baridx == 1 || baridx == 2) {
2579 if (offset + size > DMEMSZ) {
2580 printf("diow: memw too large, offset %ld size %d\n",
2585 i = baridx - 1; /* 'memregs' index */
2588 sc->memregs[i][offset] = value;
2589 } else if (size == 2) {
2590 *(uint16_t *)&sc->memregs[i][offset] = value;
2591 } else if (size == 4) {
2592 *(uint32_t *)&sc->memregs[i][offset] = value;
2593 } else if (size == 8) {
2594 *(uint64_t *)&sc->memregs[i][offset] = value;
2596 printf("diow: memw unknown size %d\n", size);
2600 * magic interrupt ??
2604 if (baridx > 2 || baridx < 0) {
2605 printf("diow: unknown bar idx %d\n", baridx);
2610 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
2612 struct pci_emul_dsoftc *sc = pi->pi_arg;
2617 if (offset + size > DIOSZ) {
2618 printf("dior: ior too large, offset %ld size %d\n",
2625 value = sc->ioregs[offset];
2626 } else if (size == 2) {
2627 value = *(uint16_t *) &sc->ioregs[offset];
2628 } else if (size == 4) {
2629 value = *(uint32_t *) &sc->ioregs[offset];
2631 printf("dior: ior unknown size %d\n", size);
2635 if (baridx == 1 || baridx == 2) {
2636 if (offset + size > DMEMSZ) {
2637 printf("dior: memr too large, offset %ld size %d\n",
2642 i = baridx - 1; /* 'memregs' index */
2645 value = sc->memregs[i][offset];
2646 } else if (size == 2) {
2647 value = *(uint16_t *) &sc->memregs[i][offset];
2648 } else if (size == 4) {
2649 value = *(uint32_t *) &sc->memregs[i][offset];
2650 } else if (size == 8) {
2651 value = *(uint64_t *) &sc->memregs[i][offset];
2653 printf("dior: ior unknown size %d\n", size);
2658 if (baridx > 2 || baridx < 0) {
2659 printf("dior: unknown bar idx %d\n", baridx);
2666 #ifdef BHYVE_SNAPSHOT
2668 pci_emul_snapshot(struct vm_snapshot_meta *meta __unused)
2674 static const struct pci_devemu pci_dummy = {
2676 .pe_init = pci_emul_dinit,
2677 .pe_barwrite = pci_emul_diow,
2678 .pe_barread = pci_emul_dior,
2679 #ifdef BHYVE_SNAPSHOT
2680 .pe_snapshot = pci_emul_snapshot,
2683 PCI_EMUL_SET(pci_dummy);
2685 #endif /* PCI_EMUL_TEST */