2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/linker_set.h>
47 #include <machine/vmm.h>
48 #include <machine/vmm_snapshot.h>
61 #define CONF1_ADDR_PORT 0x0cf8
62 #define CONF1_DATA_PORT 0x0cfc
64 #define CONF1_ENABLE 0x80000000ul
66 #define MAXBUSES (PCI_BUSMAX + 1)
67 #define MAXSLOTS (PCI_SLOTMAX + 1)
68 #define MAXFUNCS (PCI_FUNCMAX + 1)
73 struct pci_devinst *fi_devi;
83 struct intxinfo si_intpins[4];
84 struct funcinfo si_funcs[MAXFUNCS];
88 uint16_t iobase, iolimit; /* I/O window */
89 uint32_t membase32, memlimit32; /* mmio window below 4GB */
90 uint64_t membase64, memlimit64; /* mmio window above 4GB */
91 struct slotinfo slotinfo[MAXSLOTS];
94 static struct businfo *pci_businfo[MAXBUSES];
96 SET_DECLARE(pci_devemu_set, struct pci_devemu);
98 static uint64_t pci_emul_iobase;
99 static uint64_t pci_emul_membase32;
100 static uint64_t pci_emul_membase64;
102 #define PCI_EMUL_IOBASE 0x2000
103 #define PCI_EMUL_IOLIMIT 0x10000
105 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
106 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
107 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
109 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
111 #define PCI_EMUL_MEMBASE64 0xD000000000UL
112 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
114 static struct pci_devemu *pci_emul_finddev(char *name);
115 static void pci_lintr_route(struct pci_devinst *pi);
116 static void pci_lintr_update(struct pci_devinst *pi);
117 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
118 int func, int coff, int bytes, uint32_t *val);
121 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
125 pci_set_cfgdata8(pi, coff, val);
127 pci_set_cfgdata16(pi, coff, val);
129 pci_set_cfgdata32(pi, coff, val);
132 static __inline uint32_t
133 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
137 return (pci_get_cfgdata8(pi, coff));
139 return (pci_get_cfgdata16(pi, coff));
141 return (pci_get_cfgdata32(pi, coff));
149 * Slot options are in the form:
151 * <bus>:<slot>:<func>,<emul>[,<config>]
152 * <slot>[:<func>],<emul>[,<config>]
156 * emul is a string describing the type of PCI device e.g. virtio-net
157 * config is an optional string, depending on the device, that can be
158 * used for configuration.
164 pci_parse_slot_usage(char *aopt)
167 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt);
171 pci_parse_slot(char *opt)
175 char *emul, *config, *str, *cp;
176 int error, bnum, snum, fnum;
181 emul = config = NULL;
182 if ((cp = strchr(str, ',')) != NULL) {
185 if ((cp = strchr(emul, ',')) != NULL) {
190 pci_parse_slot_usage(opt);
194 /* <bus>:<slot>:<func> */
195 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
198 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
201 if (sscanf(str, "%d", &snum) != 1) {
207 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
208 fnum < 0 || fnum >= MAXFUNCS) {
209 pci_parse_slot_usage(opt);
213 if (pci_businfo[bnum] == NULL)
214 pci_businfo[bnum] = calloc(1, sizeof(struct businfo));
216 bi = pci_businfo[bnum];
217 si = &bi->slotinfo[snum];
219 if (si->si_funcs[fnum].fi_name != NULL) {
220 EPRINTLN("pci slot %d:%d already occupied!",
225 if (pci_emul_finddev(emul) == NULL) {
226 EPRINTLN("pci slot %d:%d: unknown device \"%s\"",
232 si->si_funcs[fnum].fi_name = emul;
233 si->si_funcs[fnum].fi_param = config;
243 pci_print_supported_devices()
245 struct pci_devemu **pdpp, *pdp;
247 SET_FOREACH(pdpp, pci_devemu_set) {
249 printf("%s\n", pdp->pe_emu);
254 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
257 if (offset < pi->pi_msix.pba_offset)
260 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
268 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
271 int msix_entry_offset;
275 /* support only 4 or 8 byte writes */
276 if (size != 4 && size != 8)
280 * Return if table index is beyond what device supports
282 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
283 if (tab_index >= pi->pi_msix.table_count)
286 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
288 /* support only aligned writes */
289 if ((msix_entry_offset % size) != 0)
292 dest = (char *)(pi->pi_msix.table + tab_index);
293 dest += msix_entry_offset;
296 *((uint32_t *)dest) = value;
298 *((uint64_t *)dest) = value;
304 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
307 int msix_entry_offset;
309 uint64_t retval = ~0;
312 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
313 * table but we also allow 1 byte access to accommodate reads from
316 if (size != 1 && size != 4 && size != 8)
319 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
321 /* support only aligned reads */
322 if ((msix_entry_offset % size) != 0) {
326 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
328 if (tab_index < pi->pi_msix.table_count) {
329 /* valid MSI-X Table access */
330 dest = (char *)(pi->pi_msix.table + tab_index);
331 dest += msix_entry_offset;
334 retval = *((uint8_t *)dest);
336 retval = *((uint32_t *)dest);
338 retval = *((uint64_t *)dest);
339 } else if (pci_valid_pba_offset(pi, offset)) {
340 /* return 0 for PBA access */
348 pci_msix_table_bar(struct pci_devinst *pi)
351 if (pi->pi_msix.table != NULL)
352 return (pi->pi_msix.table_bar);
358 pci_msix_pba_bar(struct pci_devinst *pi)
361 if (pi->pi_msix.table != NULL)
362 return (pi->pi_msix.pba_bar);
368 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
369 uint32_t *eax, void *arg)
371 struct pci_devinst *pdi = arg;
372 struct pci_devemu *pe = pdi->pi_d;
376 for (i = 0; i <= PCI_BARMAX; i++) {
377 if (pdi->pi_bar[i].type == PCIBAR_IO &&
378 port >= pdi->pi_bar[i].addr &&
379 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
380 offset = port - pdi->pi_bar[i].addr;
382 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
385 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
394 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
395 int size, uint64_t *val, void *arg1, long arg2)
397 struct pci_devinst *pdi = arg1;
398 struct pci_devemu *pe = pdi->pi_d;
400 int bidx = (int) arg2;
402 assert(bidx <= PCI_BARMAX);
403 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
404 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
405 assert(addr >= pdi->pi_bar[bidx].addr &&
406 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
408 offset = addr - pdi->pi_bar[bidx].addr;
410 if (dir == MEM_F_WRITE) {
412 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
413 4, *val & 0xffffffff);
414 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
417 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
422 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
424 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
425 offset + 4, 4) << 32;
427 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
437 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
442 assert((size & (size - 1)) == 0); /* must be a power of 2 */
444 base = roundup2(*baseptr, size);
446 if (base + size <= limit) {
448 *baseptr = base + size;
455 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
459 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size));
463 * Register (or unregister) the MMIO or I/O region associated with the BAR
464 * register 'idx' of an emulated pci device.
467 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
470 struct inout_port iop;
473 switch (pi->pi_bar[idx].type) {
475 bzero(&iop, sizeof(struct inout_port));
476 iop.name = pi->pi_name;
477 iop.port = pi->pi_bar[idx].addr;
478 iop.size = pi->pi_bar[idx].size;
480 iop.flags = IOPORT_F_INOUT;
481 iop.handler = pci_emul_io_handler;
483 error = register_inout(&iop);
485 error = unregister_inout(&iop);
489 bzero(&mr, sizeof(struct mem_range));
490 mr.name = pi->pi_name;
491 mr.base = pi->pi_bar[idx].addr;
492 mr.size = pi->pi_bar[idx].size;
495 mr.handler = pci_emul_mem_handler;
498 error = register_mem(&mr);
500 error = unregister_mem(&mr);
510 unregister_bar(struct pci_devinst *pi, int idx)
513 modify_bar_registration(pi, idx, 0);
517 register_bar(struct pci_devinst *pi, int idx)
520 modify_bar_registration(pi, idx, 1);
523 /* Are we decoding i/o port accesses for the emulated pci device? */
525 porten(struct pci_devinst *pi)
529 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
531 return (cmd & PCIM_CMD_PORTEN);
534 /* Are we decoding memory accesses for the emulated pci device? */
536 memen(struct pci_devinst *pi)
540 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
542 return (cmd & PCIM_CMD_MEMEN);
546 * Update the MMIO or I/O address that is decoded by the BAR register.
548 * If the pci device has enabled the address space decoding then intercept
549 * the address range decoded by the BAR register.
552 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
556 if (pi->pi_bar[idx].type == PCIBAR_IO)
562 unregister_bar(pi, idx);
567 pi->pi_bar[idx].addr = addr;
570 pi->pi_bar[idx].addr &= ~0xffffffffUL;
571 pi->pi_bar[idx].addr |= addr;
574 pi->pi_bar[idx].addr &= 0xffffffff;
575 pi->pi_bar[idx].addr |= addr;
582 register_bar(pi, idx);
586 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
587 enum pcibar_type type, uint64_t size)
590 uint64_t *baseptr, limit, addr, mask, lobits, bar;
593 assert(idx >= 0 && idx <= PCI_BARMAX);
595 if ((size & (size - 1)) != 0)
596 size = 1UL << flsl(size); /* round up to a power of 2 */
598 /* Enforce minimum BAR sizes required by the PCI standard */
599 if (type == PCIBAR_IO) {
610 addr = mask = lobits = enbit = 0;
613 baseptr = &pci_emul_iobase;
614 limit = PCI_EMUL_IOLIMIT;
615 mask = PCIM_BAR_IO_BASE;
616 lobits = PCIM_BAR_IO_SPACE;
617 enbit = PCIM_CMD_PORTEN;
622 * Some drivers do not work well if the 64-bit BAR is allocated
623 * above 4GB. Allow for this by allocating small requests under
624 * 4GB unless then allocation size is larger than some arbitrary
625 * number (32MB currently).
627 if (size > 32 * 1024 * 1024) {
629 * XXX special case for device requiring peer-peer DMA
631 if (size == 0x100000000UL)
634 baseptr = &pci_emul_membase64;
635 limit = PCI_EMUL_MEMLIMIT64;
636 mask = PCIM_BAR_MEM_BASE;
637 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
638 PCIM_BAR_MEM_PREFETCH;
640 baseptr = &pci_emul_membase32;
641 limit = PCI_EMUL_MEMLIMIT32;
642 mask = PCIM_BAR_MEM_BASE;
643 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
645 enbit = PCIM_CMD_MEMEN;
648 baseptr = &pci_emul_membase32;
649 limit = PCI_EMUL_MEMLIMIT32;
650 mask = PCIM_BAR_MEM_BASE;
651 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
652 enbit = PCIM_CMD_MEMEN;
655 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
659 if (baseptr != NULL) {
660 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
665 pdi->pi_bar[idx].type = type;
666 pdi->pi_bar[idx].addr = addr;
667 pdi->pi_bar[idx].size = size;
669 /* Initialize the BAR register in config space */
670 bar = (addr & mask) | lobits;
671 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
673 if (type == PCIBAR_MEM64) {
674 assert(idx + 1 <= PCI_BARMAX);
675 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
676 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
679 cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND);
680 if ((cmd & enbit) != enbit)
681 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit);
682 register_bar(pdi, idx);
687 #define CAP_START_OFFSET 0x40
689 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
691 int i, capoff, reallen;
696 reallen = roundup2(caplen, 4); /* dword aligned */
698 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
699 if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
700 capoff = CAP_START_OFFSET;
702 capoff = pi->pi_capend + 1;
704 /* Check if we have enough space */
705 if (capoff + reallen > PCI_REGMAX + 1)
708 /* Set the previous capability pointer */
709 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
710 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
711 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
713 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
715 /* Copy the capability */
716 for (i = 0; i < caplen; i++)
717 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
719 /* Set the next capability pointer */
720 pci_set_cfgdata8(pi, capoff + 1, 0);
722 pi->pi_prevcap = capoff;
723 pi->pi_capend = capoff + reallen - 1;
727 static struct pci_devemu *
728 pci_emul_finddev(char *name)
730 struct pci_devemu **pdpp, *pdp;
732 SET_FOREACH(pdpp, pci_devemu_set) {
734 if (!strcmp(pdp->pe_emu, name)) {
743 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
744 int func, struct funcinfo *fi)
746 struct pci_devinst *pdi;
749 pdi = calloc(1, sizeof(struct pci_devinst));
755 pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
756 pdi->pi_lintr.pin = 0;
757 pdi->pi_lintr.state = IDLE;
758 pdi->pi_lintr.pirq_pin = 0;
759 pdi->pi_lintr.ioapic_irq = 0;
761 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
763 /* Disable legacy interrupts */
764 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
765 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
767 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN);
769 err = (*pde->pe_init)(ctx, pdi, fi->fi_param);
779 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
783 /* Number of msi messages must be a power of 2 between 1 and 32 */
784 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
785 mmc = ffs(msgnum) - 1;
787 bzero(msicap, sizeof(struct msicap));
788 msicap->capid = PCIY_MSI;
789 msicap->nextptr = nextptr;
790 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
794 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
796 struct msicap msicap;
798 pci_populate_msicap(&msicap, msgnum, 0);
800 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
804 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
805 uint32_t msix_tab_size)
808 assert(msix_tab_size % 4096 == 0);
810 bzero(msixcap, sizeof(struct msixcap));
811 msixcap->capid = PCIY_MSIX;
814 * Message Control Register, all fields set to
815 * zero except for the Table Size.
816 * Note: Table size N is encoded as N-1
818 msixcap->msgctrl = msgnum - 1;
822 * - MSI-X table start at offset 0
823 * - PBA table starts at a 4K aligned offset after the MSI-X table
825 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
826 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
830 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
834 assert(table_entries > 0);
835 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
837 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
838 pi->pi_msix.table = calloc(1, table_size);
840 /* set mask bit of vector control register */
841 for (i = 0; i < table_entries; i++)
842 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
846 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
849 struct msixcap msixcap;
851 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
852 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
854 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
856 /* Align table size to nearest 4K */
857 tab_size = roundup2(tab_size, 4096);
859 pi->pi_msix.table_bar = barnum;
860 pi->pi_msix.pba_bar = barnum;
861 pi->pi_msix.table_offset = 0;
862 pi->pi_msix.table_count = msgnum;
863 pi->pi_msix.pba_offset = tab_size;
864 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
866 pci_msix_table_init(pi, msgnum);
868 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
870 /* allocate memory for MSI-X Table and PBA */
871 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
872 tab_size + pi->pi_msix.pba_size);
874 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
879 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
880 int bytes, uint32_t val)
882 uint16_t msgctrl, rwmask;
885 off = offset - capoff;
886 /* Message Control Register */
887 if (off == 2 && bytes == 2) {
888 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
889 msgctrl = pci_get_cfgdata16(pi, offset);
891 msgctrl |= val & rwmask;
894 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
895 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
896 pci_lintr_update(pi);
899 CFGWRITE(pi, offset, val, bytes);
903 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
904 int bytes, uint32_t val)
906 uint16_t msgctrl, rwmask, msgdata, mme;
910 * If guest is writing to the message control register make sure
911 * we do not overwrite read-only fields.
913 if ((offset - capoff) == 2 && bytes == 2) {
914 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
915 msgctrl = pci_get_cfgdata16(pi, offset);
917 msgctrl |= val & rwmask;
920 CFGWRITE(pi, offset, val, bytes);
922 msgctrl = pci_get_cfgdata16(pi, capoff + 2);
923 addrlo = pci_get_cfgdata32(pi, capoff + 4);
924 if (msgctrl & PCIM_MSICTRL_64BIT)
925 msgdata = pci_get_cfgdata16(pi, capoff + 12);
927 msgdata = pci_get_cfgdata16(pi, capoff + 8);
929 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
930 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
931 if (pi->pi_msi.enabled) {
932 pi->pi_msi.addr = addrlo;
933 pi->pi_msi.msg_data = msgdata;
934 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
936 pi->pi_msi.maxmsgnum = 0;
938 pci_lintr_update(pi);
942 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
943 int bytes, uint32_t val)
946 /* XXX don't write to the readonly parts */
947 CFGWRITE(pi, offset, val, bytes);
950 #define PCIECAP_VERSION 0x2
952 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
955 struct pciecap pciecap;
957 bzero(&pciecap, sizeof(pciecap));
960 * Use the integrated endpoint type for endpoints on a root complex bus.
962 * NB: bhyve currently only supports a single PCI bus that is the root
963 * complex bus, so all endpoints are integrated.
965 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0))
966 type = PCIEM_TYPE_ROOT_INT_EP;
968 pciecap.capid = PCIY_EXPRESS;
969 pciecap.pcie_capabilities = PCIECAP_VERSION | type;
970 if (type != PCIEM_TYPE_ROOT_INT_EP) {
971 pciecap.link_capabilities = 0x411; /* gen1, x1 */
972 pciecap.link_status = 0x11; /* gen1, x1 */
975 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
980 * This function assumes that 'coff' is in the capabilities region of the
984 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val)
987 uint8_t capoff, nextoff;
989 /* Do not allow un-aligned writes */
990 if ((offset & (bytes - 1)) != 0)
993 /* Find the capability that we want to update */
994 capoff = CAP_START_OFFSET;
996 nextoff = pci_get_cfgdata8(pi, capoff + 1);
999 if (offset >= capoff && offset < nextoff)
1004 assert(offset >= capoff);
1007 * Capability ID and Next Capability Pointer are readonly.
1008 * However, some o/s's do 4-byte writes that include these.
1009 * For this case, trim the write back to 2 bytes and adjust
1012 if (offset == capoff || offset == capoff + 1) {
1013 if (offset == capoff && bytes == 4) {
1021 capid = pci_get_cfgdata8(pi, capoff);
1024 msicap_cfgwrite(pi, capoff, offset, bytes, val);
1027 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1030 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1038 pci_emul_iscap(struct pci_devinst *pi, int offset)
1042 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1043 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1044 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1051 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1052 int size, uint64_t *val, void *arg1, long arg2)
1055 * Ignore writes; return 0xff's for reads. The mem read code
1056 * will take care of truncating to the correct size.
1058 if (dir == MEM_F_READ) {
1059 *val = 0xffffffffffffffff;
1066 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1067 int bytes, uint64_t *val, void *arg1, long arg2)
1069 int bus, slot, func, coff, in;
1071 coff = addr & 0xfff;
1072 func = (addr >> 12) & 0x7;
1073 slot = (addr >> 15) & 0x1f;
1074 bus = (addr >> 20) & 0xff;
1075 in = (dir == MEM_F_READ);
1078 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val);
1086 return (PCI_EMUL_ECFG_BASE);
1089 #define BUSIO_ROUNDUP 32
1090 #define BUSMEM_ROUNDUP (1024 * 1024)
1093 init_pci(struct vmctx *ctx)
1095 struct mem_range mr;
1096 struct pci_devemu *pde;
1098 struct slotinfo *si;
1099 struct funcinfo *fi;
1101 int bus, slot, func;
1104 pci_emul_iobase = PCI_EMUL_IOBASE;
1105 pci_emul_membase32 = vm_get_lowmem_limit(ctx);
1106 pci_emul_membase64 = PCI_EMUL_MEMBASE64;
1108 for (bus = 0; bus < MAXBUSES; bus++) {
1109 if ((bi = pci_businfo[bus]) == NULL)
1112 * Keep track of the i/o and memory resources allocated to
1115 bi->iobase = pci_emul_iobase;
1116 bi->membase32 = pci_emul_membase32;
1117 bi->membase64 = pci_emul_membase64;
1119 for (slot = 0; slot < MAXSLOTS; slot++) {
1120 si = &bi->slotinfo[slot];
1121 for (func = 0; func < MAXFUNCS; func++) {
1122 fi = &si->si_funcs[func];
1123 if (fi->fi_name == NULL)
1125 pde = pci_emul_finddev(fi->fi_name);
1126 assert(pde != NULL);
1127 error = pci_emul_init(ctx, pde, bus, slot,
1135 * Add some slop to the I/O and memory resources decoded by
1136 * this bus to give a guest some flexibility if it wants to
1137 * reprogram the BARs.
1139 pci_emul_iobase += BUSIO_ROUNDUP;
1140 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1141 bi->iolimit = pci_emul_iobase;
1143 pci_emul_membase32 += BUSMEM_ROUNDUP;
1144 pci_emul_membase32 = roundup2(pci_emul_membase32,
1146 bi->memlimit32 = pci_emul_membase32;
1148 pci_emul_membase64 += BUSMEM_ROUNDUP;
1149 pci_emul_membase64 = roundup2(pci_emul_membase64,
1151 bi->memlimit64 = pci_emul_membase64;
1155 * PCI backends are initialized before routing INTx interrupts
1156 * so that LPC devices are able to reserve ISA IRQs before
1157 * routing PIRQ pins.
1159 for (bus = 0; bus < MAXBUSES; bus++) {
1160 if ((bi = pci_businfo[bus]) == NULL)
1163 for (slot = 0; slot < MAXSLOTS; slot++) {
1164 si = &bi->slotinfo[slot];
1165 for (func = 0; func < MAXFUNCS; func++) {
1166 fi = &si->si_funcs[func];
1167 if (fi->fi_devi == NULL)
1169 pci_lintr_route(fi->fi_devi);
1176 * The guest physical memory map looks like the following:
1177 * [0, lowmem) guest system memory
1178 * [lowmem, lowmem_limit) memory hole (may be absent)
1179 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation)
1180 * [0xE0000000, 0xF0000000) PCI extended config window
1181 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
1182 * [4GB, 4GB + highmem)
1186 * Accesses to memory addresses that are not allocated to system
1187 * memory or PCI devices return 0xff's.
1189 lowmem = vm_get_lowmem_size(ctx);
1190 bzero(&mr, sizeof(struct mem_range));
1191 mr.name = "PCI hole";
1192 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1194 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1195 mr.handler = pci_emul_fallback_handler;
1196 error = register_mem_fallback(&mr);
1199 /* PCI extended config space */
1200 bzero(&mr, sizeof(struct mem_range));
1201 mr.name = "PCI ECFG";
1202 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1203 mr.base = PCI_EMUL_ECFG_BASE;
1204 mr.size = PCI_EMUL_ECFG_SIZE;
1205 mr.handler = pci_emul_ecfg_handler;
1206 error = register_mem(&mr);
1213 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1217 dsdt_line(" Package ()");
1219 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1220 dsdt_line(" 0x%02X,", pin - 1);
1221 dsdt_line(" Zero,");
1222 dsdt_line(" 0x%X", ioapic_irq);
1227 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1232 name = lpc_pirq_name(pirq_pin);
1235 dsdt_line(" Package ()");
1237 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1238 dsdt_line(" 0x%02X,", pin - 1);
1239 dsdt_line(" %s,", name);
1246 * A bhyve virtual machine has a flat PCI hierarchy with a root port
1247 * corresponding to each PCI bus.
1250 pci_bus_write_dsdt(int bus)
1253 struct slotinfo *si;
1254 struct pci_devinst *pi;
1255 int count, func, slot;
1258 * If there are no devices on this 'bus' then just return.
1260 if ((bi = pci_businfo[bus]) == NULL) {
1262 * Bus 0 is special because it decodes the I/O ports used
1263 * for PCI config space access even if there are no devices
1270 dsdt_line(" Device (PC%02X)", bus);
1272 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))");
1274 dsdt_line(" Method (_BBN, 0, NotSerialized)");
1276 dsdt_line(" Return (0x%08X)", bus);
1278 dsdt_line(" Name (_CRS, ResourceTemplate ()");
1280 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, "
1281 "MaxFixed, PosDecode,");
1282 dsdt_line(" 0x0000, // Granularity");
1283 dsdt_line(" 0x%04X, // Range Minimum", bus);
1284 dsdt_line(" 0x%04X, // Range Maximum", bus);
1285 dsdt_line(" 0x0000, // Translation Offset");
1286 dsdt_line(" 0x0001, // Length");
1291 dsdt_fixed_ioport(0xCF8, 8);
1294 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1295 "PosDecode, EntireRange,");
1296 dsdt_line(" 0x0000, // Granularity");
1297 dsdt_line(" 0x0000, // Range Minimum");
1298 dsdt_line(" 0x0CF7, // Range Maximum");
1299 dsdt_line(" 0x0000, // Translation Offset");
1300 dsdt_line(" 0x0CF8, // Length");
1301 dsdt_line(" ,, , TypeStatic)");
1303 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1304 "PosDecode, EntireRange,");
1305 dsdt_line(" 0x0000, // Granularity");
1306 dsdt_line(" 0x0D00, // Range Minimum");
1307 dsdt_line(" 0x%04X, // Range Maximum",
1308 PCI_EMUL_IOBASE - 1);
1309 dsdt_line(" 0x0000, // Translation Offset");
1310 dsdt_line(" 0x%04X, // Length",
1311 PCI_EMUL_IOBASE - 0x0D00);
1312 dsdt_line(" ,, , TypeStatic)");
1322 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1323 "PosDecode, EntireRange,");
1324 dsdt_line(" 0x0000, // Granularity");
1325 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase);
1326 dsdt_line(" 0x%04X, // Range Maximum",
1328 dsdt_line(" 0x0000, // Translation Offset");
1329 dsdt_line(" 0x%04X, // Length",
1330 bi->iolimit - bi->iobase);
1331 dsdt_line(" ,, , TypeStatic)");
1333 /* mmio window (32-bit) */
1334 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, "
1335 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1336 dsdt_line(" 0x00000000, // Granularity");
1337 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32);
1338 dsdt_line(" 0x%08X, // Range Maximum\n",
1339 bi->memlimit32 - 1);
1340 dsdt_line(" 0x00000000, // Translation Offset");
1341 dsdt_line(" 0x%08X, // Length\n",
1342 bi->memlimit32 - bi->membase32);
1343 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1345 /* mmio window (64-bit) */
1346 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, "
1347 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1348 dsdt_line(" 0x0000000000000000, // Granularity");
1349 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64);
1350 dsdt_line(" 0x%016lX, // Range Maximum\n",
1351 bi->memlimit64 - 1);
1352 dsdt_line(" 0x0000000000000000, // Translation Offset");
1353 dsdt_line(" 0x%016lX, // Length\n",
1354 bi->memlimit64 - bi->membase64);
1355 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1358 count = pci_count_lintr(bus);
1361 dsdt_line("Name (PPRT, Package ()");
1363 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1365 dsdt_line("Name (APRT, Package ()");
1367 pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1369 dsdt_line("Method (_PRT, 0, NotSerialized)");
1371 dsdt_line(" If (PICM)");
1373 dsdt_line(" Return (APRT)");
1377 dsdt_line(" Return (PPRT)");
1384 for (slot = 0; slot < MAXSLOTS; slot++) {
1385 si = &bi->slotinfo[slot];
1386 for (func = 0; func < MAXFUNCS; func++) {
1387 pi = si->si_funcs[func].fi_devi;
1388 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1389 pi->pi_d->pe_write_dsdt(pi);
1398 pci_write_dsdt(void)
1403 dsdt_line("Name (PICM, 0x00)");
1404 dsdt_line("Method (_PIC, 1, NotSerialized)");
1406 dsdt_line(" Store (Arg0, PICM)");
1409 dsdt_line("Scope (_SB)");
1411 for (bus = 0; bus < MAXBUSES; bus++)
1412 pci_bus_write_dsdt(bus);
1418 pci_bus_configured(int bus)
1420 assert(bus >= 0 && bus < MAXBUSES);
1421 return (pci_businfo[bus] != NULL);
1425 pci_msi_enabled(struct pci_devinst *pi)
1427 return (pi->pi_msi.enabled);
1431 pci_msi_maxmsgnum(struct pci_devinst *pi)
1433 if (pi->pi_msi.enabled)
1434 return (pi->pi_msi.maxmsgnum);
1440 pci_msix_enabled(struct pci_devinst *pi)
1443 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1447 pci_generate_msix(struct pci_devinst *pi, int index)
1449 struct msix_table_entry *mte;
1451 if (!pci_msix_enabled(pi))
1454 if (pi->pi_msix.function_mask)
1457 if (index >= pi->pi_msix.table_count)
1460 mte = &pi->pi_msix.table[index];
1461 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1462 /* XXX Set PBA bit if interrupt is disabled */
1463 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1468 pci_generate_msi(struct pci_devinst *pi, int index)
1471 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1472 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1473 pi->pi_msi.msg_data + index);
1478 pci_lintr_permitted(struct pci_devinst *pi)
1482 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1483 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1484 (cmd & PCIM_CMD_INTxDIS)));
1488 pci_lintr_request(struct pci_devinst *pi)
1491 struct slotinfo *si;
1492 int bestpin, bestcount, pin;
1494 bi = pci_businfo[pi->pi_bus];
1498 * Just allocate a pin from our slot. The pin will be
1499 * assigned IRQs later when interrupts are routed.
1501 si = &bi->slotinfo[pi->pi_slot];
1503 bestcount = si->si_intpins[0].ii_count;
1504 for (pin = 1; pin < 4; pin++) {
1505 if (si->si_intpins[pin].ii_count < bestcount) {
1507 bestcount = si->si_intpins[pin].ii_count;
1511 si->si_intpins[bestpin].ii_count++;
1512 pi->pi_lintr.pin = bestpin + 1;
1513 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1517 pci_lintr_route(struct pci_devinst *pi)
1520 struct intxinfo *ii;
1522 if (pi->pi_lintr.pin == 0)
1525 bi = pci_businfo[pi->pi_bus];
1527 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1530 * Attempt to allocate an I/O APIC pin for this intpin if one
1531 * is not yet assigned.
1533 if (ii->ii_ioapic_irq == 0)
1534 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi);
1535 assert(ii->ii_ioapic_irq > 0);
1538 * Attempt to allocate a PIRQ pin for this intpin if one is
1541 if (ii->ii_pirq_pin == 0)
1542 ii->ii_pirq_pin = pirq_alloc_pin(pi);
1543 assert(ii->ii_pirq_pin > 0);
1545 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1546 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1547 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1551 pci_lintr_assert(struct pci_devinst *pi)
1554 assert(pi->pi_lintr.pin > 0);
1556 pthread_mutex_lock(&pi->pi_lintr.lock);
1557 if (pi->pi_lintr.state == IDLE) {
1558 if (pci_lintr_permitted(pi)) {
1559 pi->pi_lintr.state = ASSERTED;
1562 pi->pi_lintr.state = PENDING;
1564 pthread_mutex_unlock(&pi->pi_lintr.lock);
1568 pci_lintr_deassert(struct pci_devinst *pi)
1571 assert(pi->pi_lintr.pin > 0);
1573 pthread_mutex_lock(&pi->pi_lintr.lock);
1574 if (pi->pi_lintr.state == ASSERTED) {
1575 pi->pi_lintr.state = IDLE;
1576 pci_irq_deassert(pi);
1577 } else if (pi->pi_lintr.state == PENDING)
1578 pi->pi_lintr.state = IDLE;
1579 pthread_mutex_unlock(&pi->pi_lintr.lock);
1583 pci_lintr_update(struct pci_devinst *pi)
1586 pthread_mutex_lock(&pi->pi_lintr.lock);
1587 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1588 pci_irq_deassert(pi);
1589 pi->pi_lintr.state = PENDING;
1590 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1591 pi->pi_lintr.state = ASSERTED;
1594 pthread_mutex_unlock(&pi->pi_lintr.lock);
1598 pci_count_lintr(int bus)
1600 int count, slot, pin;
1601 struct slotinfo *slotinfo;
1604 if (pci_businfo[bus] != NULL) {
1605 for (slot = 0; slot < MAXSLOTS; slot++) {
1606 slotinfo = &pci_businfo[bus]->slotinfo[slot];
1607 for (pin = 0; pin < 4; pin++) {
1608 if (slotinfo->si_intpins[pin].ii_count != 0)
1617 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
1620 struct slotinfo *si;
1621 struct intxinfo *ii;
1624 if ((bi = pci_businfo[bus]) == NULL)
1627 for (slot = 0; slot < MAXSLOTS; slot++) {
1628 si = &bi->slotinfo[slot];
1629 for (pin = 0; pin < 4; pin++) {
1630 ii = &si->si_intpins[pin];
1631 if (ii->ii_count != 0)
1632 cb(bus, slot, pin + 1, ii->ii_pirq_pin,
1633 ii->ii_ioapic_irq, arg);
1639 * Return 1 if the emulated device in 'slot' is a multi-function device.
1640 * Return 0 otherwise.
1643 pci_emul_is_mfdev(int bus, int slot)
1646 struct slotinfo *si;
1650 if ((bi = pci_businfo[bus]) != NULL) {
1651 si = &bi->slotinfo[slot];
1652 for (f = 0; f < MAXFUNCS; f++) {
1653 if (si->si_funcs[f].fi_devi != NULL) {
1658 return (numfuncs > 1);
1662 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1663 * whether or not is a multi-function being emulated in the pci 'slot'.
1666 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
1670 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1671 mfdev = pci_emul_is_mfdev(bus, slot);
1681 *rv &= ~(PCIM_MFDEV << 16);
1683 *rv |= (PCIM_MFDEV << 16);
1691 * Update device state in response to changes to the PCI command
1695 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old)
1698 uint16_t changed, new;
1700 new = pci_get_cfgdata16(pi, PCIR_COMMAND);
1701 changed = old ^ new;
1704 * If the MMIO or I/O address space decoding has changed then
1705 * register/unregister all BARs that decode that address space.
1707 for (i = 0; i <= PCI_BARMAX; i++) {
1708 switch (pi->pi_bar[i].type) {
1710 case PCIBAR_MEMHI64:
1713 /* I/O address space decoding changed? */
1714 if (changed & PCIM_CMD_PORTEN) {
1715 if (new & PCIM_CMD_PORTEN)
1716 register_bar(pi, i);
1718 unregister_bar(pi, i);
1723 /* MMIO address space decoding changed? */
1724 if (changed & PCIM_CMD_MEMEN) {
1725 if (new & PCIM_CMD_MEMEN)
1726 register_bar(pi, i);
1728 unregister_bar(pi, i);
1737 * If INTx has been unmasked and is pending, assert the
1740 pci_lintr_update(pi);
1744 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
1747 uint32_t cmd, old, readonly;
1749 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
1752 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3.
1754 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are
1755 * 'write 1 to clear'. However these bits are not set to '1' by
1756 * any device emulation so it is simpler to treat them as readonly.
1758 rshift = (coff & 0x3) * 8;
1759 readonly = 0xFFFFF880 >> rshift;
1761 old = CFGREAD(pi, coff, bytes);
1763 new |= (old & readonly);
1764 CFGWRITE(pi, coff, new, bytes); /* update config */
1766 pci_emul_cmd_changed(pi, cmd);
1770 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
1771 int coff, int bytes, uint32_t *eax)
1774 struct slotinfo *si;
1775 struct pci_devinst *pi;
1776 struct pci_devemu *pe;
1778 uint64_t addr, bar, mask;
1780 if ((bi = pci_businfo[bus]) != NULL) {
1781 si = &bi->slotinfo[slot];
1782 pi = si->si_funcs[func].fi_devi;
1787 * Just return if there is no device at this slot:func or if the
1788 * the guest is doing an un-aligned access.
1790 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
1791 (coff & (bytes - 1)) != 0) {
1798 * Ignore all writes beyond the standard config space and return all
1801 if (coff >= PCI_REGMAX + 1) {
1805 * Extended capabilities begin at offset 256 in config
1806 * space. Absence of extended capabilities is signaled
1807 * with all 0s in the extended capability header at
1810 if (coff <= PCI_REGMAX + 4)
1822 /* Let the device emulation override the default handler */
1823 if (pe->pe_cfgread != NULL) {
1824 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes,
1831 *eax = CFGREAD(pi, coff, bytes);
1833 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
1835 /* Let the device emulation override the default handler */
1836 if (pe->pe_cfgwrite != NULL &&
1837 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
1841 * Special handling for write to BAR registers
1843 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) {
1845 * Ignore writes to BAR registers that are not
1848 if (bytes != 4 || (coff & 0x3) != 0)
1850 idx = (coff - PCIR_BAR(0)) / 4;
1851 mask = ~(pi->pi_bar[idx].size - 1);
1852 switch (pi->pi_bar[idx].type) {
1854 pi->pi_bar[idx].addr = bar = 0;
1859 bar = addr | PCIM_BAR_IO_SPACE;
1861 * Register the new BAR value for interception
1863 if (addr != pi->pi_bar[idx].addr) {
1864 update_bar_address(pi, addr, idx,
1869 addr = bar = *eax & mask;
1870 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
1871 if (addr != pi->pi_bar[idx].addr) {
1872 update_bar_address(pi, addr, idx,
1877 addr = bar = *eax & mask;
1878 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
1879 PCIM_BAR_MEM_PREFETCH;
1880 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
1881 update_bar_address(pi, addr, idx,
1885 case PCIBAR_MEMHI64:
1886 mask = ~(pi->pi_bar[idx - 1].size - 1);
1887 addr = ((uint64_t)*eax << 32) & mask;
1889 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
1890 update_bar_address(pi, addr, idx - 1,
1897 pci_set_cfgdata32(pi, coff, bar);
1899 } else if (pci_emul_iscap(pi, coff)) {
1900 pci_emul_capwrite(pi, coff, bytes, *eax);
1901 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
1902 pci_emul_cmdsts_write(pi, coff, *eax, bytes);
1904 CFGWRITE(pi, coff, *eax, bytes);
1909 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
1912 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1913 uint32_t *eax, void *arg)
1919 *eax = (bytes == 2) ? 0xffff : 0xff;
1924 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
1930 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
1931 cfgoff = x & PCI_REGMAX;
1932 cfgfunc = (x >> 8) & PCI_FUNCMAX;
1933 cfgslot = (x >> 11) & PCI_SLOTMAX;
1934 cfgbus = (x >> 16) & PCI_BUSMAX;
1939 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
1942 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1943 uint32_t *eax, void *arg)
1947 assert(bytes == 1 || bytes == 2 || bytes == 4);
1949 coff = cfgoff + (port - CONF1_DATA_PORT);
1951 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
1954 /* Ignore accesses to cfgdata if not enabled by cfgaddr */
1961 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
1962 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
1963 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
1964 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
1966 #ifdef BHYVE_SNAPSHOT
1968 * Saves/restores PCI device emulated state. Returns 0 on success.
1971 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta)
1973 struct pci_devinst *pi;
1977 pi = meta->dev_data;
1979 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done);
1980 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done);
1981 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done);
1982 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done);
1984 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done);
1985 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done);
1986 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done);
1987 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done);
1988 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done);
1989 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done);
1990 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done);
1991 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done);
1992 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_page_offset, meta, ret, done);
1994 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata),
1997 for (i = 0; i < nitems(pi->pi_bar); i++) {
1998 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done);
1999 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done);
2000 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done);
2003 /* Restore MSI-X table. */
2004 for (i = 0; i < pi->pi_msix.table_count; i++) {
2005 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr,
2007 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data,
2009 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control,
2018 pci_find_slotted_dev(const char *dev_name, struct pci_devemu **pde,
2019 struct pci_devinst **pdi)
2022 struct slotinfo *si;
2023 struct funcinfo *fi;
2024 int bus, slot, func;
2026 assert(dev_name != NULL);
2027 assert(pde != NULL);
2028 assert(pdi != NULL);
2030 for (bus = 0; bus < MAXBUSES; bus++) {
2031 if ((bi = pci_businfo[bus]) == NULL)
2034 for (slot = 0; slot < MAXSLOTS; slot++) {
2035 si = &bi->slotinfo[slot];
2036 for (func = 0; func < MAXFUNCS; func++) {
2037 fi = &si->si_funcs[func];
2038 if (fi->fi_name == NULL)
2040 if (strcmp(dev_name, fi->fi_name))
2043 *pde = pci_emul_finddev(fi->fi_name);
2044 assert(*pde != NULL);
2056 pci_snapshot(struct vm_snapshot_meta *meta)
2058 struct pci_devemu *pde;
2059 struct pci_devinst *pdi;
2062 assert(meta->dev_name != NULL);
2064 ret = pci_find_slotted_dev(meta->dev_name, &pde, &pdi);
2066 fprintf(stderr, "%s: no such name: %s\r\n",
2067 __func__, meta->dev_name);
2068 memset(meta->buffer.buf_start, 0, meta->buffer.buf_size);
2072 meta->dev_data = pdi;
2074 if (pde->pe_snapshot == NULL) {
2075 fprintf(stderr, "%s: not implemented yet for: %s\r\n",
2076 __func__, meta->dev_name);
2080 ret = pci_snapshot_pci_dev(meta);
2082 fprintf(stderr, "%s: failed to snapshot pci dev\r\n",
2087 ret = (*pde->pe_snapshot)(meta);
2093 pci_pause(struct vmctx *ctx, const char *dev_name)
2095 struct pci_devemu *pde;
2096 struct pci_devinst *pdi;
2099 assert(dev_name != NULL);
2101 ret = pci_find_slotted_dev(dev_name, &pde, &pdi);
2104 * It is possible to call this function without
2105 * checking that the device is inserted first.
2107 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name);
2111 if (pde->pe_pause == NULL) {
2112 /* The pause/resume functionality is optional. */
2113 fprintf(stderr, "%s: not implemented for: %s\n",
2114 __func__, dev_name);
2118 return (*pde->pe_pause)(ctx, pdi);
2122 pci_resume(struct vmctx *ctx, const char *dev_name)
2124 struct pci_devemu *pde;
2125 struct pci_devinst *pdi;
2128 assert(dev_name != NULL);
2130 ret = pci_find_slotted_dev(dev_name, &pde, &pdi);
2133 * It is possible to call this function without
2134 * checking that the device is inserted first.
2136 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name);
2140 if (pde->pe_resume == NULL) {
2141 /* The pause/resume functionality is optional. */
2142 fprintf(stderr, "%s: not implemented for: %s\n",
2143 __func__, dev_name);
2147 return (*pde->pe_resume)(ctx, pdi);
2151 #define PCI_EMUL_TEST
2152 #ifdef PCI_EMUL_TEST
2154 * Define a dummy test device
2158 struct pci_emul_dsoftc {
2159 uint8_t ioregs[DIOSZ];
2160 uint8_t memregs[2][DMEMSZ];
2163 #define PCI_EMUL_MSI_MSGS 4
2164 #define PCI_EMUL_MSIX_MSGS 16
2167 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2170 struct pci_emul_dsoftc *sc;
2172 sc = calloc(1, sizeof(struct pci_emul_dsoftc));
2176 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
2177 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
2178 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
2180 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
2183 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
2186 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
2189 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
2196 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2197 uint64_t offset, int size, uint64_t value)
2200 struct pci_emul_dsoftc *sc = pi->pi_arg;
2203 if (offset + size > DIOSZ) {
2204 printf("diow: iow too large, offset %ld size %d\n",
2210 sc->ioregs[offset] = value & 0xff;
2211 } else if (size == 2) {
2212 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
2213 } else if (size == 4) {
2214 *(uint32_t *)&sc->ioregs[offset] = value;
2216 printf("diow: iow unknown size %d\n", size);
2220 * Special magic value to generate an interrupt
2222 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2223 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2225 if (value == 0xabcdef) {
2226 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2227 pci_generate_msi(pi, i);
2231 if (baridx == 1 || baridx == 2) {
2232 if (offset + size > DMEMSZ) {
2233 printf("diow: memw too large, offset %ld size %d\n",
2238 i = baridx - 1; /* 'memregs' index */
2241 sc->memregs[i][offset] = value;
2242 } else if (size == 2) {
2243 *(uint16_t *)&sc->memregs[i][offset] = value;
2244 } else if (size == 4) {
2245 *(uint32_t *)&sc->memregs[i][offset] = value;
2246 } else if (size == 8) {
2247 *(uint64_t *)&sc->memregs[i][offset] = value;
2249 printf("diow: memw unknown size %d\n", size);
2253 * magic interrupt ??
2257 if (baridx > 2 || baridx < 0) {
2258 printf("diow: unknown bar idx %d\n", baridx);
2263 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2264 uint64_t offset, int size)
2266 struct pci_emul_dsoftc *sc = pi->pi_arg;
2271 if (offset + size > DIOSZ) {
2272 printf("dior: ior too large, offset %ld size %d\n",
2279 value = sc->ioregs[offset];
2280 } else if (size == 2) {
2281 value = *(uint16_t *) &sc->ioregs[offset];
2282 } else if (size == 4) {
2283 value = *(uint32_t *) &sc->ioregs[offset];
2285 printf("dior: ior unknown size %d\n", size);
2289 if (baridx == 1 || baridx == 2) {
2290 if (offset + size > DMEMSZ) {
2291 printf("dior: memr too large, offset %ld size %d\n",
2296 i = baridx - 1; /* 'memregs' index */
2299 value = sc->memregs[i][offset];
2300 } else if (size == 2) {
2301 value = *(uint16_t *) &sc->memregs[i][offset];
2302 } else if (size == 4) {
2303 value = *(uint32_t *) &sc->memregs[i][offset];
2304 } else if (size == 8) {
2305 value = *(uint64_t *) &sc->memregs[i][offset];
2307 printf("dior: ior unknown size %d\n", size);
2312 if (baridx > 2 || baridx < 0) {
2313 printf("dior: unknown bar idx %d\n", baridx);
2320 #ifdef BHYVE_SNAPSHOT
2322 pci_emul_snapshot(struct vm_snapshot_meta *meta)
2329 struct pci_devemu pci_dummy = {
2331 .pe_init = pci_emul_dinit,
2332 .pe_barwrite = pci_emul_diow,
2333 .pe_barread = pci_emul_dior,
2334 #ifdef BHYVE_SNAPSHOT
2335 .pe_snapshot = pci_emul_snapshot,
2338 PCI_EMUL_SET(pci_dummy);
2340 #endif /* PCI_EMUL_TEST */