2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/linker_set.h>
50 #include <machine/vmm.h>
51 #include <machine/vmm_snapshot.h>
65 #define CONF1_ADDR_PORT 0x0cf8
66 #define CONF1_DATA_PORT 0x0cfc
68 #define CONF1_ENABLE 0x80000000ul
70 #define MAXBUSES (PCI_BUSMAX + 1)
71 #define MAXSLOTS (PCI_SLOTMAX + 1)
72 #define MAXFUNCS (PCI_FUNCMAX + 1)
74 #define GB (1024 * 1024 * 1024UL)
78 struct pci_devemu *fi_pde;
79 struct pci_devinst *fi_devi;
89 struct intxinfo si_intpins[4];
90 struct funcinfo si_funcs[MAXFUNCS];
94 uint16_t iobase, iolimit; /* I/O window */
95 uint32_t membase32, memlimit32; /* mmio window below 4GB */
96 uint64_t membase64, memlimit64; /* mmio window above 4GB */
97 struct slotinfo slotinfo[MAXSLOTS];
100 static struct businfo *pci_businfo[MAXBUSES];
102 SET_DECLARE(pci_devemu_set, struct pci_devemu);
104 static uint64_t pci_emul_iobase;
105 static uint8_t *pci_emul_rombase;
106 static uint64_t pci_emul_romoffset;
107 static uint8_t *pci_emul_romlim;
108 static uint64_t pci_emul_membase32;
109 static uint64_t pci_emul_membase64;
110 static uint64_t pci_emul_memlim64;
112 struct pci_bar_allocation {
113 TAILQ_ENTRY(pci_bar_allocation) chain;
114 struct pci_devinst *pdi;
116 enum pcibar_type type;
119 TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars = TAILQ_HEAD_INITIALIZER(
122 #define PCI_EMUL_IOBASE 0x2000
123 #define PCI_EMUL_IOLIMIT 0x10000
125 #define PCI_EMUL_ROMSIZE 0x10000000
127 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
128 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
129 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
132 * OVMF always uses 0xC0000000 as base address for 32 bit PCI MMIO. Don't
133 * change this address without changing it in OVMF.
135 #define PCI_EMUL_MEMBASE32 0xC0000000
136 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
137 #define PCI_EMUL_MEMSIZE64 (32*GB)
139 static struct pci_devemu *pci_emul_finddev(const char *name);
140 static void pci_lintr_route(struct pci_devinst *pi);
141 static void pci_lintr_update(struct pci_devinst *pi);
142 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
143 int func, int coff, int bytes, uint32_t *val);
146 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
150 pci_set_cfgdata8(pi, coff, val);
152 pci_set_cfgdata16(pi, coff, val);
154 pci_set_cfgdata32(pi, coff, val);
157 static __inline uint32_t
158 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
162 return (pci_get_cfgdata8(pi, coff));
164 return (pci_get_cfgdata16(pi, coff));
166 return (pci_get_cfgdata32(pi, coff));
170 is_pcir_bar(int coff)
172 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1));
176 is_pcir_bios(int coff)
178 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4);
186 * Slot options are in the form:
188 * <bus>:<slot>:<func>,<emul>[,<config>]
189 * <slot>[:<func>],<emul>[,<config>]
193 * emul is a string describing the type of PCI device e.g. virtio-net
194 * config is an optional string, depending on the device, that can be
195 * used for configuration.
201 pci_parse_slot_usage(char *aopt)
204 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt);
208 * Helper function to parse a list of comma-separated options where
209 * each option is formatted as "name[=value]". If no value is
210 * provided, the option is treated as a boolean and is given a value
214 pci_parse_legacy_config(nvlist_t *nvl, const char *opt)
216 char *config, *name, *tofree, *value;
221 config = tofree = strdup(opt);
222 while ((name = strsep(&config, ",")) != NULL) {
223 value = strchr(name, '=');
227 set_config_value_node(nvl, name, value);
229 set_config_bool_node(nvl, name, true);
236 * PCI device configuration is stored in MIBs that encode the device's
239 * pci.<bus>.<slot>.<func>
241 * Where "bus", "slot", and "func" are all decimal values without
242 * leading zeroes. Each valid device must have a "device" node which
243 * identifies the driver model of the device.
245 * Device backends can provide a parser for the "config" string. If
246 * a custom parser is not provided, pci_parse_legacy_config() is used
247 * to parse the string.
250 pci_parse_slot(char *opt)
252 char node_name[sizeof("pci.XXX.XX.X")];
253 struct pci_devemu *pde;
254 char *emul, *config, *str, *cp;
255 int error, bnum, snum, fnum;
261 emul = config = NULL;
262 if ((cp = strchr(str, ',')) != NULL) {
265 if ((cp = strchr(emul, ',')) != NULL) {
270 pci_parse_slot_usage(opt);
274 /* <bus>:<slot>:<func> */
275 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
278 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
281 if (sscanf(str, "%d", &snum) != 1) {
287 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
288 fnum < 0 || fnum >= MAXFUNCS) {
289 pci_parse_slot_usage(opt);
293 pde = pci_emul_finddev(emul);
295 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum,
300 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum,
302 nvl = find_config_node(node_name);
304 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum,
308 nvl = create_config_node(node_name);
309 if (pde->pe_alias != NULL)
310 set_config_value_node(nvl, "device", pde->pe_alias);
312 set_config_value_node(nvl, "device", pde->pe_emu);
314 if (pde->pe_legacy_config != NULL)
315 error = pde->pe_legacy_config(nvl, config);
317 error = pci_parse_legacy_config(nvl, config);
324 pci_print_supported_devices()
326 struct pci_devemu **pdpp, *pdp;
328 SET_FOREACH(pdpp, pci_devemu_set) {
330 printf("%s\n", pdp->pe_emu);
335 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
338 if (offset < pi->pi_msix.pba_offset)
341 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
349 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
352 int msix_entry_offset;
356 /* support only 4 or 8 byte writes */
357 if (size != 4 && size != 8)
361 * Return if table index is beyond what device supports
363 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
364 if (tab_index >= pi->pi_msix.table_count)
367 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
369 /* support only aligned writes */
370 if ((msix_entry_offset % size) != 0)
373 dest = (char *)(pi->pi_msix.table + tab_index);
374 dest += msix_entry_offset;
377 *((uint32_t *)dest) = value;
379 *((uint64_t *)dest) = value;
385 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
388 int msix_entry_offset;
390 uint64_t retval = ~0;
393 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
394 * table but we also allow 1 byte access to accommodate reads from
397 if (size != 1 && size != 4 && size != 8)
400 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
402 /* support only aligned reads */
403 if ((msix_entry_offset % size) != 0) {
407 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
409 if (tab_index < pi->pi_msix.table_count) {
410 /* valid MSI-X Table access */
411 dest = (char *)(pi->pi_msix.table + tab_index);
412 dest += msix_entry_offset;
415 retval = *((uint8_t *)dest);
417 retval = *((uint32_t *)dest);
419 retval = *((uint64_t *)dest);
420 } else if (pci_valid_pba_offset(pi, offset)) {
421 /* return 0 for PBA access */
429 pci_msix_table_bar(struct pci_devinst *pi)
432 if (pi->pi_msix.table != NULL)
433 return (pi->pi_msix.table_bar);
439 pci_msix_pba_bar(struct pci_devinst *pi)
442 if (pi->pi_msix.table != NULL)
443 return (pi->pi_msix.pba_bar);
449 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
450 uint32_t *eax, void *arg)
452 struct pci_devinst *pdi = arg;
453 struct pci_devemu *pe = pdi->pi_d;
457 for (i = 0; i <= PCI_BARMAX; i++) {
458 if (pdi->pi_bar[i].type == PCIBAR_IO &&
459 port >= pdi->pi_bar[i].addr &&
460 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
461 offset = port - pdi->pi_bar[i].addr;
463 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
466 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
475 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
476 int size, uint64_t *val, void *arg1, long arg2)
478 struct pci_devinst *pdi = arg1;
479 struct pci_devemu *pe = pdi->pi_d;
481 int bidx = (int) arg2;
483 assert(bidx <= PCI_BARMAX);
484 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
485 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
486 assert(addr >= pdi->pi_bar[bidx].addr &&
487 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
489 offset = addr - pdi->pi_bar[bidx].addr;
491 if (dir == MEM_F_WRITE) {
493 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
494 4, *val & 0xffffffff);
495 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
498 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
503 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
505 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
506 offset + 4, 4) << 32;
508 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
518 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
523 assert((size & (size - 1)) == 0); /* must be a power of 2 */
525 base = roundup2(*baseptr, size);
527 if (base + size <= limit) {
529 *baseptr = base + size;
536 * Register (or unregister) the MMIO or I/O region associated with the BAR
537 * register 'idx' of an emulated pci device.
540 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
542 struct pci_devemu *pe;
544 struct inout_port iop;
548 switch (pi->pi_bar[idx].type) {
550 bzero(&iop, sizeof(struct inout_port));
551 iop.name = pi->pi_name;
552 iop.port = pi->pi_bar[idx].addr;
553 iop.size = pi->pi_bar[idx].size;
555 iop.flags = IOPORT_F_INOUT;
556 iop.handler = pci_emul_io_handler;
558 error = register_inout(&iop);
560 error = unregister_inout(&iop);
561 if (pe->pe_baraddr != NULL)
562 (*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration,
563 pi->pi_bar[idx].addr);
567 bzero(&mr, sizeof(struct mem_range));
568 mr.name = pi->pi_name;
569 mr.base = pi->pi_bar[idx].addr;
570 mr.size = pi->pi_bar[idx].size;
573 mr.handler = pci_emul_mem_handler;
576 error = register_mem(&mr);
578 error = unregister_mem(&mr);
579 if (pe->pe_baraddr != NULL)
580 (*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration,
581 pi->pi_bar[idx].addr);
585 if (pe->pe_baraddr != NULL)
586 (*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration,
587 pi->pi_bar[idx].addr);
597 unregister_bar(struct pci_devinst *pi, int idx)
600 modify_bar_registration(pi, idx, 0);
604 register_bar(struct pci_devinst *pi, int idx)
607 modify_bar_registration(pi, idx, 1);
610 /* Is the ROM enabled for the emulated pci device? */
612 romen(struct pci_devinst *pi)
614 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) ==
618 /* Are we decoding i/o port accesses for the emulated pci device? */
620 porten(struct pci_devinst *pi)
624 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
626 return (cmd & PCIM_CMD_PORTEN);
629 /* Are we decoding memory accesses for the emulated pci device? */
631 memen(struct pci_devinst *pi)
635 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
637 return (cmd & PCIM_CMD_MEMEN);
641 * Update the MMIO or I/O address that is decoded by the BAR register.
643 * If the pci device has enabled the address space decoding then intercept
644 * the address range decoded by the BAR register.
647 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
651 if (pi->pi_bar[idx].type == PCIBAR_IO)
657 unregister_bar(pi, idx);
662 pi->pi_bar[idx].addr = addr;
665 pi->pi_bar[idx].addr &= ~0xffffffffUL;
666 pi->pi_bar[idx].addr |= addr;
669 pi->pi_bar[idx].addr &= 0xffffffff;
670 pi->pi_bar[idx].addr |= addr;
677 register_bar(pi, idx);
681 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
684 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX));
685 assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX));
687 if ((size & (size - 1)) != 0)
688 size = 1UL << flsl(size); /* round up to a power of 2 */
690 /* Enforce minimum BAR sizes required by the PCI standard */
691 if (type == PCIBAR_IO) {
694 } else if (type == PCIBAR_ROM) {
695 if (size < ~PCIM_BIOS_ADDR_MASK + 1)
696 size = ~PCIM_BIOS_ADDR_MASK + 1;
703 * To reduce fragmentation of the MMIO space, we allocate the BARs by
704 * size. Therefore, don't allocate the BAR yet. We create a list of all
705 * BAR allocation which is sorted by BAR size. When all PCI devices are
706 * initialized, we will assign an address to the BARs.
709 /* create a new list entry */
710 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar));
711 memset(new_bar, 0, sizeof(*new_bar));
714 new_bar->type = type;
715 new_bar->size = size;
718 * Search for a BAR which size is lower than the size of our newly
721 struct pci_bar_allocation *bar = NULL;
722 TAILQ_FOREACH(bar, &pci_bars, chain) {
723 if (bar->size < size) {
730 * Either the list is empty or new BAR is the smallest BAR of
731 * the list. Append it to the end of our list.
733 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain);
736 * The found BAR is smaller than our new BAR. For that reason,
737 * insert our new BAR before the found BAR.
739 TAILQ_INSERT_BEFORE(bar, new_bar, chain);
743 * pci_passthru devices synchronize their physical and virtual command
744 * register on init. For that reason, the virtual cmd reg should be
745 * updated as early as possible.
750 enbit = PCIM_CMD_PORTEN;
754 enbit = PCIM_CMD_MEMEN;
761 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND);
762 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit);
768 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx,
769 const enum pcibar_type type, const uint64_t size)
772 uint64_t *baseptr, limit, addr, mask, lobits, bar;
777 addr = mask = lobits = 0;
780 baseptr = &pci_emul_iobase;
781 limit = PCI_EMUL_IOLIMIT;
782 mask = PCIM_BAR_IO_BASE;
783 lobits = PCIM_BAR_IO_SPACE;
788 * Some drivers do not work well if the 64-bit BAR is allocated
789 * above 4GB. Allow for this by allocating small requests under
790 * 4GB unless then allocation size is larger than some arbitrary
791 * number (128MB currently).
793 if (size > 128 * 1024 * 1024) {
794 baseptr = &pci_emul_membase64;
795 limit = pci_emul_memlim64;
796 mask = PCIM_BAR_MEM_BASE;
797 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
798 PCIM_BAR_MEM_PREFETCH;
800 baseptr = &pci_emul_membase32;
801 limit = PCI_EMUL_MEMLIMIT32;
802 mask = PCIM_BAR_MEM_BASE;
803 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
807 baseptr = &pci_emul_membase32;
808 limit = PCI_EMUL_MEMLIMIT32;
809 mask = PCIM_BAR_MEM_BASE;
810 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
813 /* do not claim memory for ROM. OVMF will do it for us. */
816 mask = PCIM_BIOS_ADDR_MASK;
820 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
824 if (baseptr != NULL) {
825 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
830 pdi->pi_bar[idx].type = type;
831 pdi->pi_bar[idx].addr = addr;
832 pdi->pi_bar[idx].size = size;
834 * passthru devices are using same lobits as physical device they set
837 if (pdi->pi_bar[idx].lobits != 0) {
838 lobits = pdi->pi_bar[idx].lobits;
840 pdi->pi_bar[idx].lobits = lobits;
843 /* Initialize the BAR register in config space */
844 bar = (addr & mask) | lobits;
845 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
847 if (type == PCIBAR_MEM64) {
848 assert(idx + 1 <= PCI_BARMAX);
849 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
850 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
853 if (type != PCIBAR_ROM) {
854 register_bar(pdi, idx);
861 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
864 /* allocate ROM space once on first call */
865 if (pci_emul_rombase == 0) {
866 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM,
867 "pcirom", PCI_EMUL_ROMSIZE);
868 if (pci_emul_rombase == MAP_FAILED) {
869 warnx("%s: failed to create rom segment", __func__);
872 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE;
873 pci_emul_romoffset = 0;
876 /* ROM size should be a power of 2 and greater than 2 KB */
877 const uint64_t rom_size = MAX(1UL << flsl(size),
878 ~PCIM_BIOS_ADDR_MASK + 1);
880 /* check if ROM fits into ROM space */
881 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) {
882 warnx("%s: no space left in rom segment:", __func__);
883 warnx("%16lu bytes left",
884 PCI_EMUL_ROMSIZE - pci_emul_romoffset);
885 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus,
886 pdi->pi_slot, pdi->pi_func);
890 /* allocate ROM BAR */
891 const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM,
897 *addr = pci_emul_rombase + pci_emul_romoffset;
899 /* save offset into ROM Space */
900 pdi->pi_romoffset = pci_emul_romoffset;
902 /* increase offset for next ROM */
903 pci_emul_romoffset += rom_size;
908 #define CAP_START_OFFSET 0x40
910 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
912 int i, capoff, reallen;
917 reallen = roundup2(caplen, 4); /* dword aligned */
919 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
920 if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
921 capoff = CAP_START_OFFSET;
923 capoff = pi->pi_capend + 1;
925 /* Check if we have enough space */
926 if (capoff + reallen > PCI_REGMAX + 1)
929 /* Set the previous capability pointer */
930 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
931 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
932 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
934 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
936 /* Copy the capability */
937 for (i = 0; i < caplen; i++)
938 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
940 /* Set the next capability pointer */
941 pci_set_cfgdata8(pi, capoff + 1, 0);
943 pi->pi_prevcap = capoff;
944 pi->pi_capend = capoff + reallen - 1;
948 static struct pci_devemu *
949 pci_emul_finddev(const char *name)
951 struct pci_devemu **pdpp, *pdp;
953 SET_FOREACH(pdpp, pci_devemu_set) {
955 if (!strcmp(pdp->pe_emu, name)) {
964 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
965 int func, struct funcinfo *fi)
967 struct pci_devinst *pdi;
970 pdi = calloc(1, sizeof(struct pci_devinst));
976 pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
977 pdi->pi_lintr.pin = 0;
978 pdi->pi_lintr.state = IDLE;
979 pdi->pi_lintr.pirq_pin = 0;
980 pdi->pi_lintr.ioapic_irq = 0;
982 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
984 /* Disable legacy interrupts */
985 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
986 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
988 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN);
990 err = (*pde->pe_init)(ctx, pdi, fi->fi_config);
1000 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
1004 /* Number of msi messages must be a power of 2 between 1 and 32 */
1005 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
1006 mmc = ffs(msgnum) - 1;
1008 bzero(msicap, sizeof(struct msicap));
1009 msicap->capid = PCIY_MSI;
1010 msicap->nextptr = nextptr;
1011 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
1015 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
1017 struct msicap msicap;
1019 pci_populate_msicap(&msicap, msgnum, 0);
1021 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
1025 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
1026 uint32_t msix_tab_size)
1029 assert(msix_tab_size % 4096 == 0);
1031 bzero(msixcap, sizeof(struct msixcap));
1032 msixcap->capid = PCIY_MSIX;
1035 * Message Control Register, all fields set to
1036 * zero except for the Table Size.
1037 * Note: Table size N is encoded as N-1
1039 msixcap->msgctrl = msgnum - 1;
1043 * - MSI-X table start at offset 0
1044 * - PBA table starts at a 4K aligned offset after the MSI-X table
1046 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
1047 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
1051 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
1055 assert(table_entries > 0);
1056 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
1058 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
1059 pi->pi_msix.table = calloc(1, table_size);
1061 /* set mask bit of vector control register */
1062 for (i = 0; i < table_entries; i++)
1063 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
1067 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
1070 struct msixcap msixcap;
1072 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
1073 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
1075 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
1077 /* Align table size to nearest 4K */
1078 tab_size = roundup2(tab_size, 4096);
1080 pi->pi_msix.table_bar = barnum;
1081 pi->pi_msix.pba_bar = barnum;
1082 pi->pi_msix.table_offset = 0;
1083 pi->pi_msix.table_count = msgnum;
1084 pi->pi_msix.pba_offset = tab_size;
1085 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
1087 pci_msix_table_init(pi, msgnum);
1089 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
1091 /* allocate memory for MSI-X Table and PBA */
1092 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
1093 tab_size + pi->pi_msix.pba_size);
1095 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
1100 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1101 int bytes, uint32_t val)
1103 uint16_t msgctrl, rwmask;
1106 off = offset - capoff;
1107 /* Message Control Register */
1108 if (off == 2 && bytes == 2) {
1109 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
1110 msgctrl = pci_get_cfgdata16(pi, offset);
1112 msgctrl |= val & rwmask;
1115 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
1116 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
1117 pci_lintr_update(pi);
1120 CFGWRITE(pi, offset, val, bytes);
1124 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1125 int bytes, uint32_t val)
1127 uint16_t msgctrl, rwmask, msgdata, mme;
1131 * If guest is writing to the message control register make sure
1132 * we do not overwrite read-only fields.
1134 if ((offset - capoff) == 2 && bytes == 2) {
1135 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
1136 msgctrl = pci_get_cfgdata16(pi, offset);
1138 msgctrl |= val & rwmask;
1141 CFGWRITE(pi, offset, val, bytes);
1143 msgctrl = pci_get_cfgdata16(pi, capoff + 2);
1144 addrlo = pci_get_cfgdata32(pi, capoff + 4);
1145 if (msgctrl & PCIM_MSICTRL_64BIT)
1146 msgdata = pci_get_cfgdata16(pi, capoff + 12);
1148 msgdata = pci_get_cfgdata16(pi, capoff + 8);
1150 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
1151 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
1152 if (pi->pi_msi.enabled) {
1153 pi->pi_msi.addr = addrlo;
1154 pi->pi_msi.msg_data = msgdata;
1155 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
1157 pi->pi_msi.maxmsgnum = 0;
1159 pci_lintr_update(pi);
1163 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1164 int bytes, uint32_t val)
1167 /* XXX don't write to the readonly parts */
1168 CFGWRITE(pi, offset, val, bytes);
1171 #define PCIECAP_VERSION 0x2
1173 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
1176 struct pciecap pciecap;
1178 bzero(&pciecap, sizeof(pciecap));
1181 * Use the integrated endpoint type for endpoints on a root complex bus.
1183 * NB: bhyve currently only supports a single PCI bus that is the root
1184 * complex bus, so all endpoints are integrated.
1186 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0))
1187 type = PCIEM_TYPE_ROOT_INT_EP;
1189 pciecap.capid = PCIY_EXPRESS;
1190 pciecap.pcie_capabilities = PCIECAP_VERSION | type;
1191 if (type != PCIEM_TYPE_ROOT_INT_EP) {
1192 pciecap.link_capabilities = 0x411; /* gen1, x1 */
1193 pciecap.link_status = 0x11; /* gen1, x1 */
1196 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
1201 * This function assumes that 'coff' is in the capabilities region of the
1202 * config space. A capoff parameter of zero will force a search for the
1206 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val,
1207 uint8_t capoff, int capid)
1211 /* Do not allow un-aligned writes */
1212 if ((offset & (bytes - 1)) != 0)
1216 /* Find the capability that we want to update */
1217 capoff = CAP_START_OFFSET;
1219 nextoff = pci_get_cfgdata8(pi, capoff + 1);
1222 if (offset >= capoff && offset < nextoff)
1227 assert(offset >= capoff);
1228 capid = pci_get_cfgdata8(pi, capoff);
1232 * Capability ID and Next Capability Pointer are readonly.
1233 * However, some o/s's do 4-byte writes that include these.
1234 * For this case, trim the write back to 2 bytes and adjust
1237 if (offset == capoff || offset == capoff + 1) {
1238 if (offset == capoff && bytes == 4) {
1248 msicap_cfgwrite(pi, capoff, offset, bytes, val);
1251 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1254 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1262 pci_emul_iscap(struct pci_devinst *pi, int offset)
1266 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1267 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1268 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1275 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1276 int size, uint64_t *val, void *arg1, long arg2)
1279 * Ignore writes; return 0xff's for reads. The mem read code
1280 * will take care of truncating to the correct size.
1282 if (dir == MEM_F_READ) {
1283 *val = 0xffffffffffffffff;
1290 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1291 int bytes, uint64_t *val, void *arg1, long arg2)
1293 int bus, slot, func, coff, in;
1295 coff = addr & 0xfff;
1296 func = (addr >> 12) & 0x7;
1297 slot = (addr >> 15) & 0x1f;
1298 bus = (addr >> 20) & 0xff;
1299 in = (dir == MEM_F_READ);
1302 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val);
1310 return (PCI_EMUL_ECFG_BASE);
1313 #define BUSIO_ROUNDUP 32
1314 #define BUSMEM32_ROUNDUP (1024 * 1024)
1315 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024)
1318 init_pci(struct vmctx *ctx)
1320 char node_name[sizeof("pci.XXX.XX.X")];
1321 struct mem_range mr;
1322 struct pci_devemu *pde;
1324 struct slotinfo *si;
1325 struct funcinfo *fi;
1329 int bus, slot, func;
1332 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32)
1333 errx(EX_OSERR, "Invalid lowmem limit");
1335 pci_emul_iobase = PCI_EMUL_IOBASE;
1336 pci_emul_membase32 = PCI_EMUL_MEMBASE32;
1338 pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx);
1339 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64);
1340 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64;
1342 for (bus = 0; bus < MAXBUSES; bus++) {
1343 snprintf(node_name, sizeof(node_name), "pci.%d", bus);
1344 nvl = find_config_node(node_name);
1347 pci_businfo[bus] = calloc(1, sizeof(struct businfo));
1348 bi = pci_businfo[bus];
1351 * Keep track of the i/o and memory resources allocated to
1354 bi->iobase = pci_emul_iobase;
1355 bi->membase32 = pci_emul_membase32;
1356 bi->membase64 = pci_emul_membase64;
1358 /* first run: init devices */
1359 for (slot = 0; slot < MAXSLOTS; slot++) {
1360 si = &bi->slotinfo[slot];
1361 for (func = 0; func < MAXFUNCS; func++) {
1362 fi = &si->si_funcs[func];
1363 snprintf(node_name, sizeof(node_name),
1364 "pci.%d.%d.%d", bus, slot, func);
1365 nvl = find_config_node(node_name);
1369 fi->fi_config = nvl;
1370 emul = get_config_value_node(nvl, "device");
1372 EPRINTLN("pci slot %d:%d:%d: missing "
1373 "\"device\" value", bus, slot, func);
1376 pde = pci_emul_finddev(emul);
1378 EPRINTLN("pci slot %d:%d:%d: unknown "
1379 "device \"%s\"", bus, slot, func,
1383 if (pde->pe_alias != NULL) {
1384 EPRINTLN("pci slot %d:%d:%d: legacy "
1385 "device \"%s\", use \"%s\" instead",
1386 bus, slot, func, emul,
1391 error = pci_emul_init(ctx, pde, bus, slot,
1398 /* second run: assign BARs and free list */
1399 struct pci_bar_allocation *bar;
1400 struct pci_bar_allocation *bar_tmp;
1401 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) {
1402 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type,
1406 TAILQ_INIT(&pci_bars);
1409 * Add some slop to the I/O and memory resources decoded by
1410 * this bus to give a guest some flexibility if it wants to
1411 * reprogram the BARs.
1413 pci_emul_iobase += BUSIO_ROUNDUP;
1414 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1415 bi->iolimit = pci_emul_iobase;
1417 pci_emul_membase32 += BUSMEM32_ROUNDUP;
1418 pci_emul_membase32 = roundup2(pci_emul_membase32,
1420 bi->memlimit32 = pci_emul_membase32;
1422 pci_emul_membase64 += BUSMEM64_ROUNDUP;
1423 pci_emul_membase64 = roundup2(pci_emul_membase64,
1425 bi->memlimit64 = pci_emul_membase64;
1429 * PCI backends are initialized before routing INTx interrupts
1430 * so that LPC devices are able to reserve ISA IRQs before
1431 * routing PIRQ pins.
1433 for (bus = 0; bus < MAXBUSES; bus++) {
1434 if ((bi = pci_businfo[bus]) == NULL)
1437 for (slot = 0; slot < MAXSLOTS; slot++) {
1438 si = &bi->slotinfo[slot];
1439 for (func = 0; func < MAXFUNCS; func++) {
1440 fi = &si->si_funcs[func];
1441 if (fi->fi_devi == NULL)
1443 pci_lintr_route(fi->fi_devi);
1450 * The guest physical memory map looks like the following:
1451 * [0, lowmem) guest system memory
1452 * [lowmem, 0xC0000000) memory hole (may be absent)
1453 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation)
1454 * [0xE0000000, 0xF0000000) PCI extended config window
1455 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
1456 * [4GB, 4GB + highmem)
1460 * Accesses to memory addresses that are not allocated to system
1461 * memory or PCI devices return 0xff's.
1463 lowmem = vm_get_lowmem_size(ctx);
1464 bzero(&mr, sizeof(struct mem_range));
1465 mr.name = "PCI hole";
1466 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1468 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1469 mr.handler = pci_emul_fallback_handler;
1470 error = register_mem_fallback(&mr);
1473 /* PCI extended config space */
1474 bzero(&mr, sizeof(struct mem_range));
1475 mr.name = "PCI ECFG";
1476 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1477 mr.base = PCI_EMUL_ECFG_BASE;
1478 mr.size = PCI_EMUL_ECFG_SIZE;
1479 mr.handler = pci_emul_ecfg_handler;
1480 error = register_mem(&mr);
1487 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1491 dsdt_line(" Package ()");
1493 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1494 dsdt_line(" 0x%02X,", pin - 1);
1495 dsdt_line(" Zero,");
1496 dsdt_line(" 0x%X", ioapic_irq);
1501 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1506 name = lpc_pirq_name(pirq_pin);
1509 dsdt_line(" Package ()");
1511 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1512 dsdt_line(" 0x%02X,", pin - 1);
1513 dsdt_line(" %s,", name);
1520 * A bhyve virtual machine has a flat PCI hierarchy with a root port
1521 * corresponding to each PCI bus.
1524 pci_bus_write_dsdt(int bus)
1527 struct slotinfo *si;
1528 struct pci_devinst *pi;
1529 int count, func, slot;
1532 * If there are no devices on this 'bus' then just return.
1534 if ((bi = pci_businfo[bus]) == NULL) {
1536 * Bus 0 is special because it decodes the I/O ports used
1537 * for PCI config space access even if there are no devices
1544 dsdt_line(" Device (PC%02X)", bus);
1546 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))");
1548 dsdt_line(" Method (_BBN, 0, NotSerialized)");
1550 dsdt_line(" Return (0x%08X)", bus);
1552 dsdt_line(" Name (_CRS, ResourceTemplate ()");
1554 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, "
1555 "MaxFixed, PosDecode,");
1556 dsdt_line(" 0x0000, // Granularity");
1557 dsdt_line(" 0x%04X, // Range Minimum", bus);
1558 dsdt_line(" 0x%04X, // Range Maximum", bus);
1559 dsdt_line(" 0x0000, // Translation Offset");
1560 dsdt_line(" 0x0001, // Length");
1565 dsdt_fixed_ioport(0xCF8, 8);
1568 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1569 "PosDecode, EntireRange,");
1570 dsdt_line(" 0x0000, // Granularity");
1571 dsdt_line(" 0x0000, // Range Minimum");
1572 dsdt_line(" 0x0CF7, // Range Maximum");
1573 dsdt_line(" 0x0000, // Translation Offset");
1574 dsdt_line(" 0x0CF8, // Length");
1575 dsdt_line(" ,, , TypeStatic)");
1577 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1578 "PosDecode, EntireRange,");
1579 dsdt_line(" 0x0000, // Granularity");
1580 dsdt_line(" 0x0D00, // Range Minimum");
1581 dsdt_line(" 0x%04X, // Range Maximum",
1582 PCI_EMUL_IOBASE - 1);
1583 dsdt_line(" 0x0000, // Translation Offset");
1584 dsdt_line(" 0x%04X, // Length",
1585 PCI_EMUL_IOBASE - 0x0D00);
1586 dsdt_line(" ,, , TypeStatic)");
1596 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1597 "PosDecode, EntireRange,");
1598 dsdt_line(" 0x0000, // Granularity");
1599 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase);
1600 dsdt_line(" 0x%04X, // Range Maximum",
1602 dsdt_line(" 0x0000, // Translation Offset");
1603 dsdt_line(" 0x%04X, // Length",
1604 bi->iolimit - bi->iobase);
1605 dsdt_line(" ,, , TypeStatic)");
1607 /* mmio window (32-bit) */
1608 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, "
1609 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1610 dsdt_line(" 0x00000000, // Granularity");
1611 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32);
1612 dsdt_line(" 0x%08X, // Range Maximum\n",
1613 bi->memlimit32 - 1);
1614 dsdt_line(" 0x00000000, // Translation Offset");
1615 dsdt_line(" 0x%08X, // Length\n",
1616 bi->memlimit32 - bi->membase32);
1617 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1619 /* mmio window (64-bit) */
1620 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, "
1621 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1622 dsdt_line(" 0x0000000000000000, // Granularity");
1623 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64);
1624 dsdt_line(" 0x%016lX, // Range Maximum\n",
1625 bi->memlimit64 - 1);
1626 dsdt_line(" 0x0000000000000000, // Translation Offset");
1627 dsdt_line(" 0x%016lX, // Length\n",
1628 bi->memlimit64 - bi->membase64);
1629 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1632 count = pci_count_lintr(bus);
1635 dsdt_line("Name (PPRT, Package ()");
1637 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1639 dsdt_line("Name (APRT, Package ()");
1641 pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1643 dsdt_line("Method (_PRT, 0, NotSerialized)");
1645 dsdt_line(" If (PICM)");
1647 dsdt_line(" Return (APRT)");
1651 dsdt_line(" Return (PPRT)");
1658 for (slot = 0; slot < MAXSLOTS; slot++) {
1659 si = &bi->slotinfo[slot];
1660 for (func = 0; func < MAXFUNCS; func++) {
1661 pi = si->si_funcs[func].fi_devi;
1662 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1663 pi->pi_d->pe_write_dsdt(pi);
1672 pci_write_dsdt(void)
1677 dsdt_line("Name (PICM, 0x00)");
1678 dsdt_line("Method (_PIC, 1, NotSerialized)");
1680 dsdt_line(" Store (Arg0, PICM)");
1683 dsdt_line("Scope (_SB)");
1685 for (bus = 0; bus < MAXBUSES; bus++)
1686 pci_bus_write_dsdt(bus);
1692 pci_bus_configured(int bus)
1694 assert(bus >= 0 && bus < MAXBUSES);
1695 return (pci_businfo[bus] != NULL);
1699 pci_msi_enabled(struct pci_devinst *pi)
1701 return (pi->pi_msi.enabled);
1705 pci_msi_maxmsgnum(struct pci_devinst *pi)
1707 if (pi->pi_msi.enabled)
1708 return (pi->pi_msi.maxmsgnum);
1714 pci_msix_enabled(struct pci_devinst *pi)
1717 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1721 pci_generate_msix(struct pci_devinst *pi, int index)
1723 struct msix_table_entry *mte;
1725 if (!pci_msix_enabled(pi))
1728 if (pi->pi_msix.function_mask)
1731 if (index >= pi->pi_msix.table_count)
1734 mte = &pi->pi_msix.table[index];
1735 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1736 /* XXX Set PBA bit if interrupt is disabled */
1737 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1742 pci_generate_msi(struct pci_devinst *pi, int index)
1745 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1746 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1747 pi->pi_msi.msg_data + index);
1752 pci_lintr_permitted(struct pci_devinst *pi)
1756 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1757 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1758 (cmd & PCIM_CMD_INTxDIS)));
1762 pci_lintr_request(struct pci_devinst *pi)
1765 struct slotinfo *si;
1766 int bestpin, bestcount, pin;
1768 bi = pci_businfo[pi->pi_bus];
1772 * Just allocate a pin from our slot. The pin will be
1773 * assigned IRQs later when interrupts are routed.
1775 si = &bi->slotinfo[pi->pi_slot];
1777 bestcount = si->si_intpins[0].ii_count;
1778 for (pin = 1; pin < 4; pin++) {
1779 if (si->si_intpins[pin].ii_count < bestcount) {
1781 bestcount = si->si_intpins[pin].ii_count;
1785 si->si_intpins[bestpin].ii_count++;
1786 pi->pi_lintr.pin = bestpin + 1;
1787 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1791 pci_lintr_route(struct pci_devinst *pi)
1794 struct intxinfo *ii;
1796 if (pi->pi_lintr.pin == 0)
1799 bi = pci_businfo[pi->pi_bus];
1801 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1804 * Attempt to allocate an I/O APIC pin for this intpin if one
1805 * is not yet assigned.
1807 if (ii->ii_ioapic_irq == 0)
1808 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi);
1809 assert(ii->ii_ioapic_irq > 0);
1812 * Attempt to allocate a PIRQ pin for this intpin if one is
1815 if (ii->ii_pirq_pin == 0)
1816 ii->ii_pirq_pin = pirq_alloc_pin(pi);
1817 assert(ii->ii_pirq_pin > 0);
1819 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1820 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1821 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1825 pci_lintr_assert(struct pci_devinst *pi)
1828 assert(pi->pi_lintr.pin > 0);
1830 pthread_mutex_lock(&pi->pi_lintr.lock);
1831 if (pi->pi_lintr.state == IDLE) {
1832 if (pci_lintr_permitted(pi)) {
1833 pi->pi_lintr.state = ASSERTED;
1836 pi->pi_lintr.state = PENDING;
1838 pthread_mutex_unlock(&pi->pi_lintr.lock);
1842 pci_lintr_deassert(struct pci_devinst *pi)
1845 assert(pi->pi_lintr.pin > 0);
1847 pthread_mutex_lock(&pi->pi_lintr.lock);
1848 if (pi->pi_lintr.state == ASSERTED) {
1849 pi->pi_lintr.state = IDLE;
1850 pci_irq_deassert(pi);
1851 } else if (pi->pi_lintr.state == PENDING)
1852 pi->pi_lintr.state = IDLE;
1853 pthread_mutex_unlock(&pi->pi_lintr.lock);
1857 pci_lintr_update(struct pci_devinst *pi)
1860 pthread_mutex_lock(&pi->pi_lintr.lock);
1861 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1862 pci_irq_deassert(pi);
1863 pi->pi_lintr.state = PENDING;
1864 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1865 pi->pi_lintr.state = ASSERTED;
1868 pthread_mutex_unlock(&pi->pi_lintr.lock);
1872 pci_count_lintr(int bus)
1874 int count, slot, pin;
1875 struct slotinfo *slotinfo;
1878 if (pci_businfo[bus] != NULL) {
1879 for (slot = 0; slot < MAXSLOTS; slot++) {
1880 slotinfo = &pci_businfo[bus]->slotinfo[slot];
1881 for (pin = 0; pin < 4; pin++) {
1882 if (slotinfo->si_intpins[pin].ii_count != 0)
1891 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
1894 struct slotinfo *si;
1895 struct intxinfo *ii;
1898 if ((bi = pci_businfo[bus]) == NULL)
1901 for (slot = 0; slot < MAXSLOTS; slot++) {
1902 si = &bi->slotinfo[slot];
1903 for (pin = 0; pin < 4; pin++) {
1904 ii = &si->si_intpins[pin];
1905 if (ii->ii_count != 0)
1906 cb(bus, slot, pin + 1, ii->ii_pirq_pin,
1907 ii->ii_ioapic_irq, arg);
1913 * Return 1 if the emulated device in 'slot' is a multi-function device.
1914 * Return 0 otherwise.
1917 pci_emul_is_mfdev(int bus, int slot)
1920 struct slotinfo *si;
1924 if ((bi = pci_businfo[bus]) != NULL) {
1925 si = &bi->slotinfo[slot];
1926 for (f = 0; f < MAXFUNCS; f++) {
1927 if (si->si_funcs[f].fi_devi != NULL) {
1932 return (numfuncs > 1);
1936 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1937 * whether or not is a multi-function being emulated in the pci 'slot'.
1940 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
1944 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1945 mfdev = pci_emul_is_mfdev(bus, slot);
1955 *rv &= ~(PCIM_MFDEV << 16);
1957 *rv |= (PCIM_MFDEV << 16);
1965 * Update device state in response to changes to the PCI command
1969 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old)
1972 uint16_t changed, new;
1974 new = pci_get_cfgdata16(pi, PCIR_COMMAND);
1975 changed = old ^ new;
1978 * If the MMIO or I/O address space decoding has changed then
1979 * register/unregister all BARs that decode that address space.
1981 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) {
1982 switch (pi->pi_bar[i].type) {
1984 case PCIBAR_MEMHI64:
1987 /* I/O address space decoding changed? */
1988 if (changed & PCIM_CMD_PORTEN) {
1989 if (new & PCIM_CMD_PORTEN)
1990 register_bar(pi, i);
1992 unregister_bar(pi, i);
1996 /* skip (un-)register of ROM if it disabled */
2002 /* MMIO address space decoding changed? */
2003 if (changed & PCIM_CMD_MEMEN) {
2004 if (new & PCIM_CMD_MEMEN)
2005 register_bar(pi, i);
2007 unregister_bar(pi, i);
2016 * If INTx has been unmasked and is pending, assert the
2019 pci_lintr_update(pi);
2023 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
2026 uint32_t cmd, old, readonly;
2028 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
2031 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3.
2033 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are
2034 * 'write 1 to clear'. However these bits are not set to '1' by
2035 * any device emulation so it is simpler to treat them as readonly.
2037 rshift = (coff & 0x3) * 8;
2038 readonly = 0xFFFFF880 >> rshift;
2040 old = CFGREAD(pi, coff, bytes);
2042 new |= (old & readonly);
2043 CFGWRITE(pi, coff, new, bytes); /* update config */
2045 pci_emul_cmd_changed(pi, cmd);
2049 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
2050 int coff, int bytes, uint32_t *eax)
2053 struct slotinfo *si;
2054 struct pci_devinst *pi;
2055 struct pci_devemu *pe;
2057 uint64_t addr, bar, mask;
2059 if ((bi = pci_businfo[bus]) != NULL) {
2060 si = &bi->slotinfo[slot];
2061 pi = si->si_funcs[func].fi_devi;
2066 * Just return if there is no device at this slot:func or if the
2067 * the guest is doing an un-aligned access.
2069 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
2070 (coff & (bytes - 1)) != 0) {
2077 * Ignore all writes beyond the standard config space and return all
2080 if (coff >= PCI_REGMAX + 1) {
2084 * Extended capabilities begin at offset 256 in config
2085 * space. Absence of extended capabilities is signaled
2086 * with all 0s in the extended capability header at
2089 if (coff <= PCI_REGMAX + 4)
2101 /* Let the device emulation override the default handler */
2102 if (pe->pe_cfgread != NULL) {
2103 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes,
2110 *eax = CFGREAD(pi, coff, bytes);
2112 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
2114 /* Let the device emulation override the default handler */
2115 if (pe->pe_cfgwrite != NULL &&
2116 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
2120 * Special handling for write to BAR and ROM registers
2122 if (is_pcir_bar(coff) || is_pcir_bios(coff)) {
2124 * Ignore writes to BAR registers that are not
2127 if (bytes != 4 || (coff & 0x3) != 0)
2130 if (is_pcir_bar(coff)) {
2131 idx = (coff - PCIR_BAR(0)) / 4;
2132 } else if (is_pcir_bios(coff)) {
2135 errx(4, "%s: invalid BAR offset %d", __func__,
2139 mask = ~(pi->pi_bar[idx].size - 1);
2140 switch (pi->pi_bar[idx].type) {
2142 pi->pi_bar[idx].addr = bar = 0;
2147 bar = addr | pi->pi_bar[idx].lobits;
2149 * Register the new BAR value for interception
2151 if (addr != pi->pi_bar[idx].addr) {
2152 update_bar_address(pi, addr, idx,
2157 addr = bar = *eax & mask;
2158 bar |= pi->pi_bar[idx].lobits;
2159 if (addr != pi->pi_bar[idx].addr) {
2160 update_bar_address(pi, addr, idx,
2165 addr = bar = *eax & mask;
2166 bar |= pi->pi_bar[idx].lobits;
2167 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
2168 update_bar_address(pi, addr, idx,
2172 case PCIBAR_MEMHI64:
2173 mask = ~(pi->pi_bar[idx - 1].size - 1);
2174 addr = ((uint64_t)*eax << 32) & mask;
2176 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
2177 update_bar_address(pi, addr, idx - 1,
2182 addr = bar = *eax & mask;
2183 if (memen(pi) && romen(pi)) {
2184 unregister_bar(pi, idx);
2186 pi->pi_bar[idx].addr = addr;
2187 pi->pi_bar[idx].lobits = *eax &
2189 /* romen could have changed it value */
2190 if (memen(pi) && romen(pi)) {
2191 register_bar(pi, idx);
2193 bar |= pi->pi_bar[idx].lobits;
2198 pci_set_cfgdata32(pi, coff, bar);
2200 } else if (pci_emul_iscap(pi, coff)) {
2201 pci_emul_capwrite(pi, coff, bytes, *eax, 0, 0);
2202 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
2203 pci_emul_cmdsts_write(pi, coff, *eax, bytes);
2205 CFGWRITE(pi, coff, *eax, bytes);
2210 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
2213 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
2214 uint32_t *eax, void *arg)
2220 *eax = (bytes == 2) ? 0xffff : 0xff;
2225 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
2231 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
2232 cfgoff = (x & PCI_REGMAX) & ~0x03;
2233 cfgfunc = (x >> 8) & PCI_FUNCMAX;
2234 cfgslot = (x >> 11) & PCI_SLOTMAX;
2235 cfgbus = (x >> 16) & PCI_BUSMAX;
2240 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
2243 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
2244 uint32_t *eax, void *arg)
2248 assert(bytes == 1 || bytes == 2 || bytes == 4);
2250 coff = cfgoff + (port - CONF1_DATA_PORT);
2252 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
2255 /* Ignore accesses to cfgdata if not enabled by cfgaddr */
2262 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
2263 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
2264 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
2265 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
2267 #ifdef BHYVE_SNAPSHOT
2269 * Saves/restores PCI device emulated state. Returns 0 on success.
2272 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta)
2274 struct pci_devinst *pi;
2278 pi = meta->dev_data;
2280 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done);
2281 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done);
2282 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done);
2283 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done);
2285 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done);
2286 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done);
2287 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done);
2288 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done);
2289 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done);
2290 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done);
2291 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done);
2292 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done);
2294 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata),
2297 for (i = 0; i < nitems(pi->pi_bar); i++) {
2298 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done);
2299 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done);
2300 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done);
2303 /* Restore MSI-X table. */
2304 for (i = 0; i < pi->pi_msix.table_count; i++) {
2305 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr,
2307 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data,
2309 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control,
2318 pci_find_slotted_dev(const char *dev_name, struct pci_devemu **pde,
2319 struct pci_devinst **pdi)
2322 struct slotinfo *si;
2323 struct funcinfo *fi;
2324 int bus, slot, func;
2326 assert(dev_name != NULL);
2327 assert(pde != NULL);
2328 assert(pdi != NULL);
2330 for (bus = 0; bus < MAXBUSES; bus++) {
2331 if ((bi = pci_businfo[bus]) == NULL)
2334 for (slot = 0; slot < MAXSLOTS; slot++) {
2335 si = &bi->slotinfo[slot];
2336 for (func = 0; func < MAXFUNCS; func++) {
2337 fi = &si->si_funcs[func];
2338 if (fi->fi_pde == NULL)
2340 if (strcmp(dev_name, fi->fi_pde->pe_emu) != 0)
2354 pci_snapshot(struct vm_snapshot_meta *meta)
2356 struct pci_devemu *pde;
2357 struct pci_devinst *pdi;
2360 assert(meta->dev_name != NULL);
2362 ret = pci_find_slotted_dev(meta->dev_name, &pde, &pdi);
2364 fprintf(stderr, "%s: no such name: %s\r\n",
2365 __func__, meta->dev_name);
2366 memset(meta->buffer.buf_start, 0, meta->buffer.buf_size);
2370 meta->dev_data = pdi;
2372 if (pde->pe_snapshot == NULL) {
2373 fprintf(stderr, "%s: not implemented yet for: %s\r\n",
2374 __func__, meta->dev_name);
2378 ret = pci_snapshot_pci_dev(meta);
2380 fprintf(stderr, "%s: failed to snapshot pci dev\r\n",
2385 ret = (*pde->pe_snapshot)(meta);
2391 pci_pause(struct vmctx *ctx, const char *dev_name)
2393 struct pci_devemu *pde;
2394 struct pci_devinst *pdi;
2397 assert(dev_name != NULL);
2399 ret = pci_find_slotted_dev(dev_name, &pde, &pdi);
2402 * It is possible to call this function without
2403 * checking that the device is inserted first.
2405 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name);
2409 if (pde->pe_pause == NULL) {
2410 /* The pause/resume functionality is optional. */
2411 fprintf(stderr, "%s: not implemented for: %s\n",
2412 __func__, dev_name);
2416 return (*pde->pe_pause)(ctx, pdi);
2420 pci_resume(struct vmctx *ctx, const char *dev_name)
2422 struct pci_devemu *pde;
2423 struct pci_devinst *pdi;
2426 assert(dev_name != NULL);
2428 ret = pci_find_slotted_dev(dev_name, &pde, &pdi);
2431 * It is possible to call this function without
2432 * checking that the device is inserted first.
2434 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name);
2438 if (pde->pe_resume == NULL) {
2439 /* The pause/resume functionality is optional. */
2440 fprintf(stderr, "%s: not implemented for: %s\n",
2441 __func__, dev_name);
2445 return (*pde->pe_resume)(ctx, pdi);
2449 #define PCI_EMUL_TEST
2450 #ifdef PCI_EMUL_TEST
2452 * Define a dummy test device
2456 struct pci_emul_dsoftc {
2457 uint8_t ioregs[DIOSZ];
2458 uint8_t memregs[2][DMEMSZ];
2461 #define PCI_EMUL_MSI_MSGS 4
2462 #define PCI_EMUL_MSIX_MSGS 16
2465 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
2468 struct pci_emul_dsoftc *sc;
2470 sc = calloc(1, sizeof(struct pci_emul_dsoftc));
2474 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
2475 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
2476 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
2478 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
2481 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
2484 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
2487 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
2494 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2495 uint64_t offset, int size, uint64_t value)
2498 struct pci_emul_dsoftc *sc = pi->pi_arg;
2501 if (offset + size > DIOSZ) {
2502 printf("diow: iow too large, offset %ld size %d\n",
2508 sc->ioregs[offset] = value & 0xff;
2509 } else if (size == 2) {
2510 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
2511 } else if (size == 4) {
2512 *(uint32_t *)&sc->ioregs[offset] = value;
2514 printf("diow: iow unknown size %d\n", size);
2518 * Special magic value to generate an interrupt
2520 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2521 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2523 if (value == 0xabcdef) {
2524 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2525 pci_generate_msi(pi, i);
2529 if (baridx == 1 || baridx == 2) {
2530 if (offset + size > DMEMSZ) {
2531 printf("diow: memw too large, offset %ld size %d\n",
2536 i = baridx - 1; /* 'memregs' index */
2539 sc->memregs[i][offset] = value;
2540 } else if (size == 2) {
2541 *(uint16_t *)&sc->memregs[i][offset] = value;
2542 } else if (size == 4) {
2543 *(uint32_t *)&sc->memregs[i][offset] = value;
2544 } else if (size == 8) {
2545 *(uint64_t *)&sc->memregs[i][offset] = value;
2547 printf("diow: memw unknown size %d\n", size);
2551 * magic interrupt ??
2555 if (baridx > 2 || baridx < 0) {
2556 printf("diow: unknown bar idx %d\n", baridx);
2561 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2562 uint64_t offset, int size)
2564 struct pci_emul_dsoftc *sc = pi->pi_arg;
2569 if (offset + size > DIOSZ) {
2570 printf("dior: ior too large, offset %ld size %d\n",
2577 value = sc->ioregs[offset];
2578 } else if (size == 2) {
2579 value = *(uint16_t *) &sc->ioregs[offset];
2580 } else if (size == 4) {
2581 value = *(uint32_t *) &sc->ioregs[offset];
2583 printf("dior: ior unknown size %d\n", size);
2587 if (baridx == 1 || baridx == 2) {
2588 if (offset + size > DMEMSZ) {
2589 printf("dior: memr too large, offset %ld size %d\n",
2594 i = baridx - 1; /* 'memregs' index */
2597 value = sc->memregs[i][offset];
2598 } else if (size == 2) {
2599 value = *(uint16_t *) &sc->memregs[i][offset];
2600 } else if (size == 4) {
2601 value = *(uint32_t *) &sc->memregs[i][offset];
2602 } else if (size == 8) {
2603 value = *(uint64_t *) &sc->memregs[i][offset];
2605 printf("dior: ior unknown size %d\n", size);
2610 if (baridx > 2 || baridx < 0) {
2611 printf("dior: unknown bar idx %d\n", baridx);
2618 #ifdef BHYVE_SNAPSHOT
2620 pci_emul_snapshot(struct vm_snapshot_meta *meta)
2627 struct pci_devemu pci_dummy = {
2629 .pe_init = pci_emul_dinit,
2630 .pe_barwrite = pci_emul_diow,
2631 .pe_barread = pci_emul_dior,
2632 #ifdef BHYVE_SNAPSHOT
2633 .pe_snapshot = pci_emul_snapshot,
2636 PCI_EMUL_SET(pci_dummy);
2638 #endif /* PCI_EMUL_TEST */