2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
42 #include <machine/vmm.h>
49 #define CONF1_ADDR_PORT 0x0cf8
50 #define CONF1_DATA_PORT 0x0cfc
52 #define CFGWRITE(pi,off,val,b) \
55 pci_set_cfgdata8((pi),(off),(val)); \
56 } else if ((b) == 2) { \
57 pci_set_cfgdata16((pi),(off),(val)); \
59 pci_set_cfgdata32((pi),(off),(val)); \
65 static struct slotinfo {
68 struct pci_devinst *si_devi;
73 } pci_slotinfo[MAXSLOTS];
77 * struct used to build an in-core OEM table to supply device names
80 static struct mptable_pci_devnames {
81 #define MPT_HDR_BASE 0
82 #define MPT_HDR_NAME 2
87 #define MPT_NTAP_SIG \
88 ((uint32_t)(('P' << 24) | ('A' << 16) | ('T' << 8) | 'N'))
91 struct mptable_pci_slotinfo {
93 uint16_t mds_phys_slot;
100 uint8_t mds_suffix[4];
101 uint8_t mds_prefix[4];
102 uint32_t mds_rsvd[3];
103 } md_slotinfo[MAXSLOTS];
106 SET_DECLARE(pci_devemu_set, struct pci_devemu);
108 static uint64_t pci_emul_iobase;
109 static uint64_t pci_emul_membase32;
110 static uint64_t pci_emul_membase64;
112 #define PCI_EMUL_IOBASE 0x2000
113 #define PCI_EMUL_IOLIMIT 0x10000
115 #define PCI_EMUL_MEMBASE32 (lomem_sz)
116 #define PCI_EMUL_MEMLIMIT32 0xE0000000 /* 3.5GB */
118 #define PCI_EMUL_MEMBASE64 0xD000000000UL
119 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
121 static int pci_emul_devices;
122 static int devname_elems;
129 * Slot options are in the form:
131 * <slot>,<emul>[,<config>]
134 * emul is a string describing the type of PCI device e.g. virtio-net
135 * config is an optional string, depending on the device, that can be
136 * used for configuration.
142 pci_parse_slot_usage(char *aopt)
144 printf("Invalid PCI slot info field \"%s\"\n", aopt);
149 pci_parse_slot(char *opt)
151 char *slot, *emul, *config;
155 str = cpy = strdup(opt);
158 slot = strsep(&str, ",");
159 emul = strsep(&str, ",");
161 config = strsep(&str, ",");
165 pci_parse_slot_usage(cpy);
171 if (snum < 0 || snum >= MAXSLOTS) {
172 pci_parse_slot_usage(cpy);
174 pci_slotinfo[snum].si_name = emul;
175 pci_slotinfo[snum].si_param = config;
182 * PCI MPTable names are of the form:
184 * <slot>,[prefix]<digit><suffix>
186 * .. with <prefix> an alphabetic char, <digit> a 1 or 2-digit string,
187 * and <suffix> a single char.
198 * Note that this is NetApp-specific, but is ignored on other o/s's.
201 pci_parse_name_usage(char *aopt)
203 printf("Invalid PCI slot name field \"%s\"\n", aopt);
207 pci_parse_name(char *opt)
219 slotend = strchr(opt, ',');
222 * A comma must be present, and can't be the first character
223 * or no slot would be present. Also, the slot number can't be
224 * more than 2 characters.
226 if (slotend == NULL || slotend == opt || (slotend - opt > 2)) {
227 pci_parse_name_usage(opt);
231 for (i = 0; i < (slotend - opt); i++) {
238 if (snum < 0 || snum >= MAXSLOTS) {
239 pci_parse_name_usage(opt);
243 namestr = slotend + 1;
245 if (strlen(namestr) > 3) {
246 pci_parse_name_usage(opt);
250 if (isalpha(*namestr)) {
254 if (!isdigit(*namestr)) {
255 pci_parse_name_usage(opt);
257 pslot = *namestr++ - '0';
258 if (isnumber(*namestr)) {
259 pslot = 10*pslot + *namestr++ - '0';
262 if (isalpha(*namestr) && *(namestr + 1) == 0) {
264 pci_slotinfo[snum].si_titled = 1;
265 pci_slotinfo[snum].si_pslot = pslot;
266 pci_slotinfo[snum].si_prefix = prefix;
267 pci_slotinfo[snum].si_suffix = suffix;
270 pci_parse_name_usage(opt);
276 pci_add_mptable_name(struct slotinfo *si)
278 struct mptable_pci_slotinfo *ms;
281 * If naming information has been supplied for this slot, populate
282 * the next available mptable OEM entry
285 ms = &pci_devnames.md_slotinfo[devname_elems];
287 ms->mds_type = MPT_HDR_NAME;
288 ms->mds_phys_slot = si->si_pslot;
289 ms->mds_bus = si->si_devi->pi_bus;
290 ms->mds_slot = si->si_devi->pi_slot;
291 ms->mds_func = si->si_devi->pi_func;
292 ms->mds_vid = pci_get_cfgdata16(si->si_devi, PCIR_VENDOR);
293 ms->mds_did = pci_get_cfgdata16(si->si_devi, PCIR_DEVICE);
294 ms->mds_suffix[0] = si->si_suffix;
295 ms->mds_prefix[0] = si->si_prefix;
302 pci_finish_mptable_names(void)
307 pci_devnames.md_hdrtype = MPT_HDR_BASE;
308 pci_devnames.md_entries = devname_elems;
309 pci_devnames.md_cksum = 0; /* XXX */
310 pci_devnames.md_sig = MPT_NTAP_SIG;
312 size = (uintptr_t)&pci_devnames.md_slotinfo[devname_elems] -
313 (uintptr_t)&pci_devnames;
315 fbsdrun_add_oemtbl(&pci_devnames, size);
320 pci_emul_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
321 uint32_t *eax, void *arg)
323 struct pci_devinst *pdi = arg;
324 struct pci_devemu *pe = pdi->pi_d;
327 for (i = 0; i <= PCI_BARMAX; i++) {
328 if (pdi->pi_bar[i].type == PCIBAR_IO &&
329 port >= pdi->pi_bar[i].addr &&
330 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
331 offset = port - pdi->pi_bar[i].addr;
333 *eax = (*pe->pe_ior)(pdi, i, offset, bytes);
335 (*pe->pe_iow)(pdi, i, offset, bytes, *eax);
343 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
348 assert((size & (size - 1)) == 0); /* must be a power of 2 */
350 base = roundup2(*baseptr, size);
352 if (base + size <= limit) {
354 *baseptr = base + size;
361 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
362 enum pcibar_type type, uint64_t size)
365 uint64_t *baseptr, limit, addr, mask, lobits, bar;
366 struct inout_port iop;
368 assert(idx >= 0 && idx <= PCI_BARMAX);
370 if ((size & (size - 1)) != 0)
371 size = 1UL << flsl(size); /* round up to a power of 2 */
376 addr = mask = lobits = 0;
379 baseptr = &pci_emul_iobase;
380 limit = PCI_EMUL_IOLIMIT;
381 mask = PCIM_BAR_IO_BASE;
382 lobits = PCIM_BAR_IO_SPACE;
387 * Some drivers do not work well if the 64-bit BAR is allocated
388 * above 4GB. Allow for this by allocating small requests under
389 * 4GB unless then allocation size is larger than some arbitrary
390 * number (32MB currently).
392 if (size > 32 * 1024 * 1024) {
394 * XXX special case for device requiring peer-peer DMA
396 if (size == 0x100000000UL)
399 baseptr = &pci_emul_membase64;
400 limit = PCI_EMUL_MEMLIMIT64;
401 mask = PCIM_BAR_MEM_BASE;
402 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
403 PCIM_BAR_MEM_PREFETCH;
408 baseptr = &pci_emul_membase32;
409 limit = PCI_EMUL_MEMLIMIT32;
410 mask = PCIM_BAR_MEM_BASE;
411 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
414 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
418 if (baseptr != NULL) {
419 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
424 pdi->pi_bar[idx].type = type;
425 pdi->pi_bar[idx].addr = addr;
426 pdi->pi_bar[idx].size = size;
428 /* Initialize the BAR register in config space */
429 bar = (addr & mask) | lobits;
430 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
432 if (type == PCIBAR_MEM64) {
433 assert(idx + 1 <= PCI_BARMAX);
434 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
435 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
438 /* add a handler to intercept accesses to the I/O bar */
439 if (type == PCIBAR_IO) {
440 iop.name = pdi->pi_name;
441 iop.flags = IOPORT_F_INOUT;
442 iop.handler = pci_emul_handler;
445 for (i = 0; i < size; i++) {
447 register_inout(&iop);
454 #define CAP_START_OFFSET 0x40
456 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
458 int i, capoff, capid, reallen;
461 static u_char endofcap[4] = {
462 PCIY_RESERVED, 0, 0, 0
465 assert(caplen > 0 && capdata[0] != PCIY_RESERVED);
467 reallen = roundup2(caplen, 4); /* dword aligned */
469 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
470 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
471 capoff = CAP_START_OFFSET;
472 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
473 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
475 capoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR);
477 assert((capoff & 0x3) == 0);
478 capid = pci_get_cfgdata8(pi, capoff);
479 if (capid == PCIY_RESERVED)
481 capoff = pci_get_cfgdata8(pi, capoff + 1);
485 /* Check if we have enough space */
486 if (capoff + reallen + sizeof(endofcap) > PCI_REGMAX + 1)
489 /* Copy the capability */
490 for (i = 0; i < caplen; i++)
491 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
493 /* Set the next capability pointer */
494 pci_set_cfgdata8(pi, capoff + 1, capoff + reallen);
496 /* Copy of the reserved capability which serves as the end marker */
497 for (i = 0; i < sizeof(endofcap); i++)
498 pci_set_cfgdata8(pi, capoff + reallen + i, endofcap[i]);
503 static struct pci_devemu *
504 pci_emul_finddev(char *name)
506 struct pci_devemu **pdpp, *pdp;
508 SET_FOREACH(pdpp, pci_devemu_set) {
510 if (!strcmp(pdp->pe_emu, name)) {
519 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int slot, char *params)
521 struct pci_devinst *pdi;
522 pdi = malloc(sizeof(struct pci_devinst));
523 bzero(pdi, sizeof(*pdi));
530 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
532 /* Disable legacy interrupts */
533 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
534 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
536 pci_set_cfgdata8(pdi, PCIR_COMMAND,
537 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
539 if ((*pde->pe_init)(ctx, pdi, params) != 0) {
543 pci_slotinfo[slot].si_devi = pdi;
548 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
552 CTASSERT(sizeof(struct msicap) == 14);
554 /* Number of msi messages must be a power of 2 between 1 and 32 */
555 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
556 mmc = ffs(msgnum) - 1;
558 bzero(msicap, sizeof(struct msicap));
559 msicap->capid = PCIY_MSI;
560 msicap->nextptr = nextptr;
561 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
565 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
567 struct msicap msicap;
569 pci_populate_msicap(&msicap, msgnum, 0);
571 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
575 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
576 int bytes, uint32_t val)
578 uint16_t msgctrl, rwmask, msgdata, mme;
582 * If guest is writing to the message control register make sure
583 * we do not overwrite read-only fields.
585 if ((offset - capoff) == 2 && bytes == 2) {
586 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
587 msgctrl = pci_get_cfgdata16(pi, offset);
589 msgctrl |= val & rwmask;
592 addrlo = pci_get_cfgdata32(pi, capoff + 4);
593 if (msgctrl & PCIM_MSICTRL_64BIT)
594 msgdata = pci_get_cfgdata16(pi, capoff + 12);
596 msgdata = pci_get_cfgdata16(pi, capoff + 8);
599 * XXX check delivery mode, destination mode etc
601 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
602 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
603 if (pi->pi_msi.enabled) {
604 pi->pi_msi.cpu = (addrlo >> 12) & 0xff;
605 pi->pi_msi.vector = msgdata & 0xff;
606 pi->pi_msi.msgnum = 1 << (mme >> 4);
609 pi->pi_msi.vector = 0;
610 pi->pi_msi.msgnum = 0;
614 CFGWRITE(pi, offset, val, bytes);
618 * This function assumes that 'coff' is in the capabilities region of the
622 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val)
625 uint8_t capoff, nextoff;
627 /* Do not allow un-aligned writes */
628 if ((offset & (bytes - 1)) != 0)
631 /* Find the capability that we want to update */
632 capoff = CAP_START_OFFSET;
634 capid = pci_get_cfgdata8(pi, capoff);
635 if (capid == PCIY_RESERVED)
638 nextoff = pci_get_cfgdata8(pi, capoff + 1);
639 if (offset >= capoff && offset < nextoff)
644 assert(offset >= capoff);
647 * Capability ID and Next Capability Pointer are readonly
649 if (offset == capoff || offset == capoff + 1)
654 msicap_cfgwrite(pi, capoff, offset, bytes, val);
662 pci_emul_iscap(struct pci_devinst *pi, int offset)
666 uint8_t capid, lastoff;
669 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
670 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
671 lastoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR);
673 assert((lastoff & 0x3) == 0);
674 capid = pci_get_cfgdata8(pi, lastoff);
675 if (capid == PCIY_RESERVED)
677 lastoff = pci_get_cfgdata8(pi, lastoff + 1);
679 if (offset >= CAP_START_OFFSET && offset <= lastoff)
686 init_pci(struct vmctx *ctx)
688 struct pci_devemu *pde;
692 pci_emul_iobase = PCI_EMUL_IOBASE;
693 pci_emul_membase32 = PCI_EMUL_MEMBASE32;
694 pci_emul_membase64 = PCI_EMUL_MEMBASE64;
698 for (i = 0; i < MAXSLOTS; i++, si++) {
699 if (si->si_name != NULL) {
700 pde = pci_emul_finddev(si->si_name);
702 pci_emul_init(ctx, pde, i, si->si_param);
703 pci_add_mptable_name(si);
707 pci_finish_mptable_names();
711 pci_msi_enabled(struct pci_devinst *pi)
713 return (pi->pi_msi.enabled);
717 pci_msi_msgnum(struct pci_devinst *pi)
719 if (pi->pi_msi.enabled)
720 return (pi->pi_msi.msgnum);
726 pci_generate_msi(struct pci_devinst *pi, int msg)
729 if (pci_msi_enabled(pi) && msg < pci_msi_msgnum(pi)) {
730 vm_lapic_irq(pi->pi_vmctx,
732 pi->pi_msi.vector + msg);
736 static int cfgbus, cfgslot, cfgfunc, cfgoff;
739 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
740 uint32_t *eax, void *arg)
750 cfgoff = x & PCI_REGMAX;
751 cfgfunc = (x >> 8) & PCI_FUNCMAX;
752 cfgslot = (x >> 11) & PCI_SLOTMAX;
753 cfgbus = (x >> 16) & PCI_BUSMAX;
757 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_OUT, pci_emul_cfgaddr);
760 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
761 uint32_t *eax, void *arg)
763 struct pci_devinst *pi;
764 struct pci_devemu *pe;
768 assert(bytes == 1 || bytes == 2 || bytes == 4);
770 pi = pci_slotinfo[cfgslot].si_devi;
771 coff = cfgoff + (port - CONF1_DATA_PORT);
774 printf("pcicfg-%s from 0x%0x of %d bytes (%d/%d/%d)\n\r",
775 in ? "read" : "write", coff, bytes, cfgbus, cfgslot, cfgfunc);
778 if (pi == NULL || cfgfunc != 0) {
790 /* Let the device emulation override the default handler */
791 if (pe->pe_cfgread != NULL &&
792 (*pe->pe_cfgread)(ctx, vcpu, pi, coff, bytes, eax) == 0)
796 *eax = pci_get_cfgdata8(pi, coff);
798 *eax = pci_get_cfgdata16(pi, coff);
800 *eax = pci_get_cfgdata32(pi, coff);
802 /* Let the device emulation override the default handler */
803 if (pe->pe_cfgwrite != NULL &&
804 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
808 * Special handling for write to BAR registers
810 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) {
812 * Ignore writes to BAR registers that are not
815 if (bytes != 4 || (coff & 0x3) != 0)
817 idx = (coff - PCIR_BAR(0)) / 4;
818 switch (pi->pi_bar[idx].type) {
823 mask = ~(pi->pi_bar[idx].size - 1);
824 mask &= PCIM_BAR_IO_BASE;
825 bar = (*eax & mask) | PCIM_BAR_IO_SPACE;
828 mask = ~(pi->pi_bar[idx].size - 1);
829 mask &= PCIM_BAR_MEM_BASE;
831 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
834 mask = ~(pi->pi_bar[idx].size - 1);
835 mask &= PCIM_BAR_MEM_BASE;
837 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
838 PCIM_BAR_MEM_PREFETCH;
841 mask = ~(pi->pi_bar[idx - 1].size - 1);
842 mask &= PCIM_BAR_MEM_BASE;
843 bar = ((uint64_t)*eax << 32) & mask;
849 pci_set_cfgdata32(pi, coff, bar);
850 } else if (pci_emul_iscap(pi, coff)) {
851 pci_emul_capwrite(pi, coff, bytes, *eax);
853 CFGWRITE(pi, coff, *eax, bytes);
860 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
861 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
862 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
863 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
866 * I/O ports to configure PCI IRQ routing. We ignore all writes to it.
869 pci_irq_port_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
870 uint32_t *eax, void *arg)
875 INOUT_PORT(pci_irq, 0xC00, IOPORT_F_OUT, pci_irq_port_handler);
876 INOUT_PORT(pci_irq, 0xC01, IOPORT_F_OUT, pci_irq_port_handler);
878 #define PCI_EMUL_TEST
881 * Define a dummy test device
884 struct pci_emul_dsoftc {
885 uint8_t regs[DREGSZ];
888 #define PCI_EMUL_MSGS 4
891 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
894 struct pci_emul_dsoftc *sc;
896 sc = malloc(sizeof(struct pci_emul_dsoftc));
897 memset(sc, 0, sizeof(struct pci_emul_dsoftc));
901 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
902 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
903 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
905 error = pci_emul_alloc_bar(pi, 0, 0, PCIBAR_IO, DREGSZ);
908 error = pci_emul_add_msicap(pi, PCI_EMUL_MSGS);
915 pci_emul_diow(struct pci_devinst *pi, int baridx, int offset, int size,
919 struct pci_emul_dsoftc *sc = pi->pi_arg;
921 if (offset + size > DREGSZ) {
922 printf("diow: too large, offset %d size %d\n", offset, size);
927 sc->regs[offset] = value & 0xff;
928 } else if (size == 2) {
929 *(uint16_t *)&sc->regs[offset] = value & 0xffff;
931 *(uint32_t *)&sc->regs[offset] = value;
935 * Special magic value to generate an interrupt
937 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
938 pci_generate_msi(pi, value % pci_msi_msgnum(pi));
940 if (value == 0xabcdef) {
941 for (i = 0; i < pci_msi_msgnum(pi); i++)
942 pci_generate_msi(pi, i);
947 pci_emul_dior(struct pci_devinst *pi, int baridx, int offset, int size)
949 struct pci_emul_dsoftc *sc = pi->pi_arg;
952 if (offset + size > DREGSZ) {
953 printf("dior: too large, offset %d size %d\n", offset, size);
958 value = sc->regs[offset];
959 } else if (size == 2) {
960 value = *(uint16_t *) &sc->regs[offset];
962 value = *(uint32_t *) &sc->regs[offset];
968 struct pci_devemu pci_dummy = {
970 .pe_init = pci_emul_dinit,
971 .pe_iow = pci_emul_diow,
972 .pe_ior = pci_emul_dior
974 PCI_EMUL_SET(pci_dummy);
976 #endif /* PCI_EMUL_TEST */