2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/types.h>
33 #include <sys/queue.h>
34 #include <sys/kernel.h>
36 #include <sys/pciio.h>
37 #include <sys/_pthreadtypes.h>
39 #include <dev/pci/pcireg.h>
43 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
44 #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1)
45 #define PCI_ROM_IDX (PCI_BARMAX + 1)
50 struct vm_snapshot_meta;
53 const char *pe_emu; /* Name of device emulation */
55 /* instance creation */
56 int (*pe_init)(struct pci_devinst *, nvlist_t *);
57 int (*pe_legacy_config)(nvlist_t *, const char *);
60 /* ACPI DSDT enumeration */
61 void (*pe_write_dsdt)(struct pci_devinst *);
63 /* config space read/write callbacks */
64 int (*pe_cfgwrite)(struct pci_devinst *pi, int offset,
65 int bytes, uint32_t val);
66 int (*pe_cfgread)(struct pci_devinst *pi, int offset,
67 int bytes, uint32_t *retval);
69 /* BAR read/write callbacks */
70 void (*pe_barwrite)(struct pci_devinst *pi, int baridx,
71 uint64_t offset, int size, uint64_t value);
72 uint64_t (*pe_barread)(struct pci_devinst *pi, int baridx,
73 uint64_t offset, int size);
75 void (*pe_baraddr)(struct pci_devinst *pi,
76 int baridx, int enabled, uint64_t address);
78 /* Save/restore device state */
79 int (*pe_snapshot)(struct vm_snapshot_meta *meta);
80 int (*pe_pause)(struct pci_devinst *pi);
81 int (*pe_resume)(struct pci_devinst *pi);
84 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x)
96 enum pcibar_type type; /* io or memory */
104 struct msix_table_entry {
107 uint32_t vector_control;
111 * In case the structure is modified to hold extra information, use a define
112 * for the size that should be emulated.
114 #define MSIX_TABLE_ENTRY_SIZE 16
115 #define MAX_MSIX_TABLE_ENTRIES 2048
116 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8)
125 struct pci_devemu *pi_d;
126 struct vmctx *pi_vmctx;
127 uint8_t pi_bus, pi_slot, pi_func;
128 char pi_name[PI_NAMESZ];
135 enum lintr_stat state;
138 pthread_mutex_t lock;
152 uint32_t table_offset;
157 struct msix_table_entry *table; /* allocated at runtime */
158 uint8_t *mapped_addr;
162 void *pi_arg; /* devemu-private data */
164 u_char pi_cfgdata[PCI_REGMAX + 1];
165 /* ROM is handled like a BAR */
166 struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1];
167 uint64_t pi_romoffset;
178 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
184 uint32_t table_info; /* bar index and offset within it */
185 uint32_t pba_info; /* bar index and offset within it */
187 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
192 uint16_t pcie_capabilities;
194 uint32_t dev_capabilities; /* all devices */
195 uint16_t dev_control;
198 uint32_t link_capabilities; /* devices with links */
199 uint16_t link_control;
200 uint16_t link_status;
202 uint32_t slot_capabilities; /* ports with slots */
203 uint16_t slot_control;
204 uint16_t slot_status;
206 uint16_t root_control; /* root ports */
207 uint16_t root_capabilities;
208 uint32_t root_status;
210 uint32_t dev_capabilities2; /* all devices */
211 uint16_t dev_control2;
212 uint16_t dev_status2;
214 uint32_t link_capabilities2; /* devices with links */
215 uint16_t link_control2;
216 uint16_t link_status2;
218 uint32_t slot_capabilities2; /* ports with slots */
219 uint16_t slot_control2;
220 uint16_t slot_status2;
222 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
224 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
225 int ioapic_irq, void *arg);
227 int init_pci(struct vmctx *ctx);
228 void pci_callback(void);
229 uint32_t pci_config_read_reg(const struct pcisel *host_sel, nvlist_t *nvl,
230 uint32_t reg, uint8_t size, uint32_t def);
231 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
232 enum pcibar_type type, uint64_t size);
233 int pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
235 int pci_emul_add_boot_device(struct pci_devinst *const pi,
236 const int bootindex);
237 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
238 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
239 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes,
240 uint32_t val, uint8_t capoff, int capid);
241 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old);
242 void pci_generate_msi(struct pci_devinst *pi, int msgnum);
243 void pci_generate_msix(struct pci_devinst *pi, int msgnum);
244 void pci_lintr_assert(struct pci_devinst *pi);
245 void pci_lintr_deassert(struct pci_devinst *pi);
246 void pci_lintr_request(struct pci_devinst *pi);
247 int pci_msi_enabled(struct pci_devinst *pi);
248 int pci_msix_enabled(struct pci_devinst *pi);
249 int pci_msix_table_bar(struct pci_devinst *pi);
250 int pci_msix_pba_bar(struct pci_devinst *pi);
251 int pci_msi_maxmsgnum(struct pci_devinst *pi);
252 int pci_parse_legacy_config(nvlist_t *nvl, const char *opt);
253 int pci_parse_slot(char *opt);
254 void pci_print_supported_devices(void);
255 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
256 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
257 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
259 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
260 int pci_count_lintr(int bus);
261 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
262 void pci_write_dsdt(void);
263 uint64_t pci_ecfg_base(void);
264 int pci_bus_configured(int bus);
265 #ifdef BHYVE_SNAPSHOT
266 struct pci_devinst *pci_next(const struct pci_devinst *cursor);
267 int pci_snapshot(struct vm_snapshot_meta *meta);
268 int pci_pause(struct pci_devinst *pdi);
269 int pci_resume(struct pci_devinst *pdi);
273 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
275 assert(offset <= PCI_REGMAX);
276 *(uint8_t *)(pi->pi_cfgdata + offset) = val;
280 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
282 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
283 *(uint16_t *)(pi->pi_cfgdata + offset) = val;
287 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
289 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
290 *(uint32_t *)(pi->pi_cfgdata + offset) = val;
293 static __inline uint8_t
294 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
296 assert(offset <= PCI_REGMAX);
297 return (*(uint8_t *)(pi->pi_cfgdata + offset));
300 static __inline uint16_t
301 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
303 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
304 return (*(uint16_t *)(pi->pi_cfgdata + offset));
307 static __inline uint32_t
308 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
310 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
311 return (*(uint32_t *)(pi->pi_cfgdata + offset));
314 #endif /* _PCI_EMUL_H_ */