2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include <sys/types.h>
35 #include <sys/queue.h>
36 #include <sys/kernel.h>
37 #include <sys/_pthreadtypes.h>
39 #include <dev/pci/pcireg.h>
43 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
50 char *pe_emu; /* Name of device emulation */
52 /* instance creation */
53 int (*pe_init)(struct vmctx *, struct pci_devinst *,
56 /* ACPI DSDT enumeration */
57 void (*pe_write_dsdt)(struct pci_devinst *);
59 /* config space read/write callbacks */
60 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu,
61 struct pci_devinst *pi, int offset,
62 int bytes, uint32_t val);
63 int (*pe_cfgread)(struct vmctx *ctx, int vcpu,
64 struct pci_devinst *pi, int offset,
65 int bytes, uint32_t *retval);
67 /* BAR read/write callbacks */
68 void (*pe_barwrite)(struct vmctx *ctx, int vcpu,
69 struct pci_devinst *pi, int baridx,
70 uint64_t offset, int size, uint64_t value);
71 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu,
72 struct pci_devinst *pi, int baridx,
73 uint64_t offset, int size);
75 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x);
86 enum pcibar_type type; /* io or memory */
93 struct msix_table_entry {
96 uint32_t vector_control;
100 * In case the structure is modified to hold extra information, use a define
101 * for the size that should be emulated.
103 #define MSIX_TABLE_ENTRY_SIZE 16
104 #define MAX_MSIX_TABLE_ENTRIES 2048
105 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8)
114 struct pci_devemu *pi_d;
115 struct vmctx *pi_vmctx;
116 uint8_t pi_bus, pi_slot, pi_func;
117 char pi_name[PI_NAMESZ];
124 enum lintr_stat state;
127 pthread_mutex_t lock;
141 uint32_t table_offset;
146 struct msix_table_entry *table; /* allocated at runtime */
151 void *pi_arg; /* devemu-private data */
153 u_char pi_cfgdata[PCI_REGMAX + 1];
154 struct pcibar pi_bar[PCI_BARMAX + 1];
165 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
171 uint32_t table_info; /* bar index and offset within it */
172 uint32_t pba_info; /* bar index and offset within it */
174 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
179 uint16_t pcie_capabilities;
181 uint32_t dev_capabilities; /* all devices */
182 uint16_t dev_control;
185 uint32_t link_capabilities; /* devices with links */
186 uint16_t link_control;
187 uint16_t link_status;
189 uint32_t slot_capabilities; /* ports with slots */
190 uint16_t slot_control;
191 uint16_t slot_status;
193 uint16_t root_control; /* root ports */
194 uint16_t root_capabilities;
195 uint32_t root_status;
197 uint32_t dev_capabilities2; /* all devices */
198 uint16_t dev_control2;
199 uint16_t dev_status2;
201 uint32_t link_capabilities2; /* devices with links */
202 uint16_t link_control2;
203 uint16_t link_status2;
205 uint32_t slot_capabilities2; /* ports with slots */
206 uint16_t slot_control2;
207 uint16_t slot_status2;
209 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
211 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
212 int ioapic_irq, void *arg);
214 int init_pci(struct vmctx *ctx);
215 void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
216 int bytes, uint32_t val);
217 void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
218 int bytes, uint32_t val);
219 void pci_callback(void);
220 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
221 enum pcibar_type type, uint64_t size);
222 int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
223 uint64_t hostbase, enum pcibar_type type, uint64_t size);
224 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
225 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
226 void pci_generate_msi(struct pci_devinst *pi, int msgnum);
227 void pci_generate_msix(struct pci_devinst *pi, int msgnum);
228 void pci_lintr_assert(struct pci_devinst *pi);
229 void pci_lintr_deassert(struct pci_devinst *pi);
230 void pci_lintr_request(struct pci_devinst *pi);
231 int pci_msi_enabled(struct pci_devinst *pi);
232 int pci_msix_enabled(struct pci_devinst *pi);
233 int pci_msix_table_bar(struct pci_devinst *pi);
234 int pci_msix_pba_bar(struct pci_devinst *pi);
235 int pci_msi_maxmsgnum(struct pci_devinst *pi);
236 int pci_parse_slot(char *opt);
237 void pci_print_supported_devices();
238 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
239 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
240 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
242 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
243 int pci_count_lintr(int bus);
244 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
245 void pci_write_dsdt(void);
246 uint64_t pci_ecfg_base(void);
247 int pci_bus_configured(int bus);
250 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
252 assert(offset <= PCI_REGMAX);
253 *(uint8_t *)(pi->pi_cfgdata + offset) = val;
257 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
259 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
260 *(uint16_t *)(pi->pi_cfgdata + offset) = val;
264 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
266 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
267 *(uint32_t *)(pi->pi_cfgdata + offset) = val;
270 static __inline uint8_t
271 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
273 assert(offset <= PCI_REGMAX);
274 return (*(uint8_t *)(pi->pi_cfgdata + offset));
277 static __inline uint16_t
278 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
280 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
281 return (*(uint16_t *)(pi->pi_cfgdata + offset));
284 static __inline uint32_t
285 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
287 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
288 return (*(uint32_t *)(pi->pi_cfgdata + offset));
291 #endif /* _PCI_EMUL_H_ */