2 * Copyright (c) 2011 NetApp, Inc.
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6 * modification, are permitted provided that the following conditions
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14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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32 #include <sys/types.h>
33 #include <sys/queue.h>
34 #include <sys/kernel.h>
36 #include <dev/pci/pcireg.h>
40 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
41 #define PCIY_RESERVED 0x00
48 char *pe_emu; /* Name of device emulation */
50 /* instance creation */
51 int (*pe_init)(struct vmctx *, struct pci_devinst *,
54 /* config space read/write callbacks */
55 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu,
56 struct pci_devinst *pi, int offset,
57 int bytes, uint32_t val);
58 int (*pe_cfgread)(struct vmctx *ctx, int vcpu,
59 struct pci_devinst *pi, int offset,
60 int bytes, uint32_t *retval);
62 /* BAR read/write callbacks */
63 void (*pe_barwrite)(struct vmctx *ctx, int vcpu,
64 struct pci_devinst *pi, int baridx,
65 uint64_t offset, int size, uint64_t value);
66 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu,
67 struct pci_devinst *pi, int baridx,
68 uint64_t offset, int size);
70 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x);
81 enum pcibar_type type; /* io or memory */
88 struct msix_table_entry {
91 uint32_t vector_control;
95 * In case the structure is modified to hold extra information, use a define
96 * for the size that should be emulated.
98 #define MSIX_TABLE_ENTRY_SIZE 16
99 #define MAX_MSIX_TABLE_ENTRIES 2048
100 #define PBA_TABLE_ENTRY_SIZE 8
103 struct pci_devemu *pi_d;
104 struct vmctx *pi_vmctx;
105 uint8_t pi_bus, pi_slot, pi_func;
106 uint8_t pi_lintr_pin;
107 char pi_name[PI_NAMESZ];
126 struct msix_table_entry *table; /* allocated at runtime */
129 void *pi_arg; /* devemu-private data */
131 u_char pi_cfgdata[PCI_REGMAX + 1];
132 struct pcibar pi_bar[PCI_BARMAX + 1];
148 uint32_t table_info; /* bar index and offset within it */
149 uint32_t pba_info; /* bar index and offset within it */
155 uint16_t pcie_capabilities;
157 uint32_t dev_capabilities; /* all devices */
158 uint16_t dev_control;
161 uint32_t link_capabilities; /* devices with links */
162 uint16_t link_control;
163 uint16_t link_status;
165 uint32_t slot_capabilities; /* ports with slots */
166 uint16_t slot_control;
167 uint16_t slot_status;
169 uint16_t root_control; /* root ports */
170 uint16_t root_capabilities;
171 uint32_t root_status;
173 uint32_t dev_capabilities2; /* all devices */
174 uint16_t dev_control2;
175 uint16_t dev_status2;
177 uint32_t link_capabilities2; /* devices with links */
178 uint16_t link_control2;
179 uint16_t link_status2;
181 uint32_t slot_capabilities2; /* ports with slots */
182 uint16_t slot_control2;
183 uint16_t slot_status2;
186 void init_pci(struct vmctx *ctx);
187 void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
188 int bytes, uint32_t val);
189 void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
190 int bytes, uint32_t val);
191 void pci_callback(void);
192 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
193 enum pcibar_type type, uint64_t size);
194 int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
195 uint64_t hostbase, enum pcibar_type type, uint64_t size);
196 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
197 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
198 int pci_is_legacy(struct pci_devinst *pi);
199 void pci_generate_msi(struct pci_devinst *pi, int msgnum);
200 void pci_generate_msix(struct pci_devinst *pi, int msgnum);
201 void pci_lintr_assert(struct pci_devinst *pi);
202 void pci_lintr_deassert(struct pci_devinst *pi);
203 int pci_lintr_request(struct pci_devinst *pi, int ivec);
204 int pci_msi_enabled(struct pci_devinst *pi);
205 int pci_msix_enabled(struct pci_devinst *pi);
206 int pci_msix_table_bar(struct pci_devinst *pi);
207 int pci_msix_pba_bar(struct pci_devinst *pi);
208 int pci_msi_msgnum(struct pci_devinst *pi);
209 int pci_parse_slot(char *opt, int legacy);
210 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
211 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
212 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
214 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
217 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
219 assert(offset <= PCI_REGMAX);
220 *(uint8_t *)(pi->pi_cfgdata + offset) = val;
224 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
226 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
227 *(uint16_t *)(pi->pi_cfgdata + offset) = val;
231 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
233 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
234 *(uint32_t *)(pi->pi_cfgdata + offset) = val;
237 static __inline uint8_t
238 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
240 assert(offset <= PCI_REGMAX);
241 return (*(uint8_t *)(pi->pi_cfgdata + offset));
244 static __inline uint16_t
245 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
247 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
248 return (*(uint16_t *)(pi->pi_cfgdata + offset));
251 static __inline uint32_t
252 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
254 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
255 return (*(uint32_t *)(pi->pi_cfgdata + offset));
258 #endif /* _PCI_EMUL_H_ */