2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015 Nahanni Systems, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/types.h>
37 #include <machine/vmm.h>
38 #include <machine/vmm_snapshot.h>
59 * bhyve Framebuffer device emulation.
60 * BAR0 points to the current mode information.
61 * BAR1 is the 32-bit framebuffer address.
63 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
66 static int fbuf_debug = 1;
68 #define DEBUG_VERBOSE 4
69 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params
73 #define MB (1024 * 1024UL)
77 #define FB_SIZE (16*MB)
82 #define COLS_DEFAULT 1024
83 #define ROWS_DEFAULT 768
88 struct pci_fbuf_softc {
89 struct pci_devinst *fsc_pi;
96 uint8_t reserved[116];
112 struct bhyvegc_image *gc_image;
115 static struct pci_fbuf_softc *fbuf_sc;
117 #define PCI_FBUF_MSI_MSGS 4
120 pci_fbuf_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
121 int baridx, uint64_t offset, int size, uint64_t value)
123 struct pci_fbuf_softc *sc;
130 DPRINTF(DEBUG_VERBOSE,
131 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx",
132 offset, size, value));
134 if (offset + size > DMEMSZ) {
135 printf("fbuf: write too large, offset %ld size %d\n",
140 p = (uint8_t *)&sc->memregs + offset;
147 *(uint16_t *)p = value;
150 *(uint32_t *)p = value;
153 *(uint64_t *)p = value;
156 printf("fbuf: write unknown size %d\n", size);
160 if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
161 sc->memregs.height == 0) {
162 DPRINTF(DEBUG_INFO, ("switching to VGA mode"));
163 sc->gc_image->vgamode = 1;
166 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
167 sc->memregs.height != 0) {
168 DPRINTF(DEBUG_INFO, ("switching to VESA mode"));
169 sc->gc_image->vgamode = 0;
174 pci_fbuf_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
175 int baridx, uint64_t offset, int size)
177 struct pci_fbuf_softc *sc;
186 if (offset + size > DMEMSZ) {
187 printf("fbuf: read too large, offset %ld size %d\n",
192 p = (uint8_t *)&sc->memregs + offset;
199 value = *(uint16_t *)p;
202 value = *(uint32_t *)p;
205 value = *(uint64_t *)p;
208 printf("fbuf: read unknown size %d\n", size);
212 DPRINTF(DEBUG_VERBOSE,
213 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx",
214 offset, size, value));
220 pci_fbuf_baraddr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
221 int enabled, uint64_t address)
223 struct pci_fbuf_softc *sc;
231 if (vm_munmap_memseg(ctx, sc->fbaddr, FB_SIZE) != 0)
232 EPRINTLN("pci_fbuf: munmap_memseg failed");
235 prot = PROT_READ | PROT_WRITE;
236 if (vm_mmap_memseg(ctx, address, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0)
237 EPRINTLN("pci_fbuf: mmap_memseg failed");
238 sc->fbaddr = address;
244 pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl)
249 sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false);
251 /* Prefer "rfb" to "tcp". */
252 value = get_config_value_node(nvl, "rfb");
254 value = get_config_value_node(nvl, "tcp");
257 * IPv4 -- host-ip:port
258 * IPv6 -- [host-ip%zone]:port
259 * XXX for now port is mandatory for IPv4.
261 if (value[0] == '[') {
262 cp = strchr(value + 1, ']');
263 if (cp == NULL || cp == value + 1) {
264 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
268 sc->rfb_host = strndup(value + 1, cp - (value + 1));
274 "fbuf: Missing port number: \"%s\"",
278 sc->rfb_port = atoi(cp);
279 } else if (*cp != '\0') {
280 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
285 cp = strchr(value, ':');
287 sc->rfb_port = atoi(value);
289 sc->rfb_host = strndup(value, cp - value);
293 "fbuf: Missing port number: \"%s\"",
297 sc->rfb_port = atoi(cp);
302 value = get_config_value_node(nvl, "vga");
304 if (strcmp(value, "off") == 0) {
306 } else if (strcmp(value, "io") == 0) {
309 } else if (strcmp(value, "on") == 0) {
313 EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value);
318 value = get_config_value_node(nvl, "w");
320 sc->memregs.width = atoi(value);
321 if (sc->memregs.width > COLS_MAX) {
322 EPRINTLN("fbuf: width %d too large", sc->memregs.width);
325 if (sc->memregs.width == 0)
326 sc->memregs.width = 1920;
329 value = get_config_value_node(nvl, "h");
331 sc->memregs.height = atoi(value);
332 if (sc->memregs.height > ROWS_MAX) {
333 EPRINTLN("fbuf: height %d too large",
337 if (sc->memregs.height == 0)
338 sc->memregs.height = 1080;
341 value = get_config_value_node(nvl, "password");
343 sc->rfb_password = strdup(value);
349 extern void vga_render(struct bhyvegc *gc, void *arg);
352 pci_fbuf_render(struct bhyvegc *gc, void *arg)
354 struct pci_fbuf_softc *sc;
358 if (sc->vga_full && sc->gc_image->vgamode) {
359 /* TODO: mode switching to vga and vesa should use the special
360 * EFI-bhyve protocol port.
362 vga_render(gc, sc->vgasc);
365 if (sc->gc_width != sc->memregs.width ||
366 sc->gc_height != sc->memregs.height) {
367 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
368 sc->gc_width = sc->memregs.width;
369 sc->gc_height = sc->memregs.height;
376 pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
379 struct pci_fbuf_softc *sc;
381 if (fbuf_sc != NULL) {
382 EPRINTLN("Only one frame buffer device is allowed.");
386 sc = calloc(1, sizeof(struct pci_fbuf_softc));
390 /* initialize config space */
391 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
392 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
393 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
394 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
396 sc->fb_base = vm_create_devmem(
397 ctx, VM_FRAMEBUFFER, "framebuffer", FB_SIZE);
398 if (sc->fb_base == MAP_FAILED) {
403 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
406 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
409 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
412 sc->memregs.fbsize = FB_SIZE;
413 sc->memregs.width = COLS_DEFAULT;
414 sc->memregs.height = ROWS_DEFAULT;
415 sc->memregs.depth = 32;
422 error = pci_fbuf_parse_config(sc, nvl);
426 /* XXX until VGA rendering is enabled */
427 if (sc->vga_full != 0) {
428 EPRINTLN("pci_fbuf: VGA rendering not enabled");
432 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]",
433 sc->fb_base, FB_SIZE));
435 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
436 console_fb_register(pci_fbuf_render, sc);
439 sc->vgasc = vga_init(!sc->vga_full);
440 sc->gc_image = console_get_image();
444 memset((void *)sc->fb_base, 0, FB_SIZE);
446 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password);
454 #ifdef BHYVE_SNAPSHOT
456 pci_fbuf_snapshot(struct vm_snapshot_meta *meta)
460 SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err);
467 static const struct pci_devemu pci_fbuf = {
469 .pe_init = pci_fbuf_init,
470 .pe_barwrite = pci_fbuf_write,
471 .pe_barread = pci_fbuf_read,
472 .pe_baraddr = pci_fbuf_baraddr,
473 #ifdef BHYVE_SNAPSHOT
474 .pe_snapshot = pci_fbuf_snapshot,
477 PCI_EMUL_SET(pci_fbuf);