2 * Copyright (c) 2015 Nahanni Systems, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/types.h>
35 #include <machine/vmm.h>
54 * bhyve Framebuffer device emulation.
55 * BAR0 points to the current mode information.
56 * BAR1 is the 32-bit framebuffer address.
58 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
61 static int fbuf_debug = 1;
63 #define DEBUG_VERBOSE 4
64 #define DPRINTF(level, params) if (level <= fbuf_debug) printf params
68 #define MB (1024 * 1024UL)
72 #define FB_SIZE (16*MB)
77 #define COLS_DEFAULT 1024
78 #define ROWS_DEFAULT 768
83 struct pci_fbuf_softc {
84 struct pci_devinst *fsc_pi;
91 uint8_t reserved[116];
106 struct bhyvegc_image *gc_image;
109 static struct pci_fbuf_softc *fbuf_sc;
111 #define PCI_FBUF_MSI_MSGS 4
114 pci_fbuf_usage(char *opt)
117 fprintf(stderr, "Invalid fbuf emulation \"%s\"\r\n", opt);
118 fprintf(stderr, "fbuf: {wait,}{vga=on|io|off,}rfb=<ip>:port\r\n");
122 pci_fbuf_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
123 int baridx, uint64_t offset, int size, uint64_t value)
125 struct pci_fbuf_softc *sc;
132 DPRINTF(DEBUG_VERBOSE,
133 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx\n",
134 offset, size, value));
136 if (offset + size > DMEMSZ) {
137 printf("fbuf: write too large, offset %ld size %d\n",
142 p = (uint8_t *)&sc->memregs + offset;
149 *(uint16_t *)p = value;
152 *(uint32_t *)p = value;
155 *(uint64_t *)p = value;
158 printf("fbuf: write unknown size %d\n", size);
162 if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
163 sc->memregs.height == 0) {
164 DPRINTF(DEBUG_INFO, ("switching to VGA mode\r\n"));
165 sc->gc_image->vgamode = 1;
168 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
169 sc->memregs.height != 0) {
170 DPRINTF(DEBUG_INFO, ("switching to VESA mode\r\n"));
171 sc->gc_image->vgamode = 0;
176 pci_fbuf_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
177 int baridx, uint64_t offset, int size)
179 struct pci_fbuf_softc *sc;
188 if (offset + size > DMEMSZ) {
189 printf("fbuf: read too large, offset %ld size %d\n",
194 p = (uint8_t *)&sc->memregs + offset;
201 value = *(uint16_t *)p;
204 value = *(uint32_t *)p;
207 value = *(uint64_t *)p;
210 printf("fbuf: read unknown size %d\n", size);
214 DPRINTF(DEBUG_VERBOSE,
215 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx\n",
216 offset, size, value));
222 pci_fbuf_parse_opts(struct pci_fbuf_softc *sc, char *opts)
224 char *uopts, *xopts, *config;
229 uopts = strdup(opts);
230 for (xopts = strtok(uopts, ",");
232 xopts = strtok(NULL, ",")) {
233 if (strcmp(xopts, "wait") == 0) {
238 if ((config = strchr(xopts, '=')) == NULL) {
239 pci_fbuf_usage(xopts);
246 DPRINTF(DEBUG_VERBOSE, ("pci_fbuf option %s = %s\r\n",
249 if (!strcmp(xopts, "tcp") || !strcmp(xopts, "rfb")) {
250 /* parse host-ip:port */
251 tmpstr = strsep(&config, ":");
253 sc->rfb_port = atoi(tmpstr);
255 sc->rfb_port = atoi(config);
256 sc->rfb_host = tmpstr;
258 } else if (!strcmp(xopts, "vga")) {
259 if (!strcmp(config, "off")) {
261 } else if (!strcmp(config, "io")) {
264 } else if (!strcmp(config, "on")) {
268 pci_fbuf_usage(opts);
272 } else if (!strcmp(xopts, "w")) {
273 sc->memregs.width = atoi(config);
274 if (sc->memregs.width > COLS_MAX) {
275 pci_fbuf_usage(xopts);
278 } else if (sc->memregs.width == 0)
279 sc->memregs.width = 1920;
280 } else if (!strcmp(xopts, "h")) {
281 sc->memregs.height = atoi(config);
282 if (sc->memregs.height > ROWS_MAX) {
283 pci_fbuf_usage(xopts);
286 } else if (sc->memregs.height == 0)
287 sc->memregs.height = 1080;
290 pci_fbuf_usage(xopts);
301 extern void vga_render(struct bhyvegc *gc, void *arg);
304 pci_fbuf_render(struct bhyvegc *gc, void *arg)
306 struct pci_fbuf_softc *sc;
310 if (sc->vga_full && sc->gc_image->vgamode) {
311 /* TODO: mode switching to vga and vesa should use the special
312 * EFI-bhyve protocol port.
314 vga_render(gc, sc->vgasc);
317 if (sc->gc_width != sc->memregs.width ||
318 sc->gc_height != sc->memregs.height) {
319 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
320 sc->gc_width = sc->memregs.width;
321 sc->gc_height = sc->memregs.height;
328 pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
331 struct pci_fbuf_softc *sc;
333 if (fbuf_sc != NULL) {
334 fprintf(stderr, "Only one frame buffer device is allowed.\n");
338 sc = calloc(1, sizeof(struct pci_fbuf_softc));
342 /* initialize config space */
343 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
344 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
345 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
346 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
348 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
351 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
354 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
357 sc->fbaddr = pi->pi_bar[1].addr;
358 sc->memregs.fbsize = FB_SIZE;
359 sc->memregs.width = COLS_DEFAULT;
360 sc->memregs.height = ROWS_DEFAULT;
361 sc->memregs.depth = 32;
368 error = pci_fbuf_parse_opts(sc, opts);
372 /* XXX until VGA rendering is enabled */
373 if (sc->vga_full != 0) {
374 fprintf(stderr, "pci_fbuf: VGA rendering not enabled");
378 sc->fb_base = vm_create_devmem(ctx, VM_FRAMEBUFFER, "framebuffer", FB_SIZE);
379 if (sc->fb_base == MAP_FAILED) {
383 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]\r\n",
384 sc->fb_base, FB_SIZE));
387 * Map the framebuffer into the guest address space.
388 * XXX This may fail if the BAR is different than a prior
389 * run. In this case flag the error. This will be fixed
390 * when a change_memseg api is available.
392 prot = PROT_READ | PROT_WRITE;
393 if (vm_mmap_memseg(ctx, sc->fbaddr, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0) {
394 fprintf(stderr, "pci_fbuf: mapseg failed - try deleting VM and restarting\n");
399 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
400 console_fb_register(pci_fbuf_render, sc);
403 sc->vgasc = vga_init(!sc->vga_full);
404 sc->gc_image = console_get_image();
408 memset((void *)sc->fb_base, 0, FB_SIZE);
410 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait);
418 struct pci_devemu pci_fbuf = {
420 .pe_init = pci_fbuf_init,
421 .pe_barwrite = pci_fbuf_write,
422 .pe_barread = pci_fbuf_read
424 PCI_EMUL_SET(pci_fbuf);