2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015 Nahanni Systems, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/types.h>
37 #include <machine/vmm.h>
57 * bhyve Framebuffer device emulation.
58 * BAR0 points to the current mode information.
59 * BAR1 is the 32-bit framebuffer address.
61 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
64 static int fbuf_debug = 1;
66 #define DEBUG_VERBOSE 4
67 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params
71 #define MB (1024 * 1024UL)
75 #define FB_SIZE (16*MB)
80 #define COLS_DEFAULT 1024
81 #define ROWS_DEFAULT 768
86 struct pci_fbuf_softc {
87 struct pci_devinst *fsc_pi;
94 uint8_t reserved[116];
110 struct bhyvegc_image *gc_image;
113 static struct pci_fbuf_softc *fbuf_sc;
115 #define PCI_FBUF_MSI_MSGS 4
118 pci_fbuf_usage(char *opt)
121 EPRINTLN("Invalid fbuf emulation option \"%s\"", opt);
122 EPRINTLN("fbuf: {wait,}{vga=on|io|off,}rfb=<ip>:port"
123 "{,w=width}{,h=height}");
127 pci_fbuf_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
128 int baridx, uint64_t offset, int size, uint64_t value)
130 struct pci_fbuf_softc *sc;
137 DPRINTF(DEBUG_VERBOSE,
138 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx\n",
139 offset, size, value));
141 if (offset + size > DMEMSZ) {
142 printf("fbuf: write too large, offset %ld size %d\n",
147 p = (uint8_t *)&sc->memregs + offset;
154 *(uint16_t *)p = value;
157 *(uint32_t *)p = value;
160 *(uint64_t *)p = value;
163 printf("fbuf: write unknown size %d\n", size);
167 if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
168 sc->memregs.height == 0) {
169 DPRINTF(DEBUG_INFO, ("switching to VGA mode"));
170 sc->gc_image->vgamode = 1;
173 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
174 sc->memregs.height != 0) {
175 DPRINTF(DEBUG_INFO, ("switching to VESA mode"));
176 sc->gc_image->vgamode = 0;
181 pci_fbuf_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
182 int baridx, uint64_t offset, int size)
184 struct pci_fbuf_softc *sc;
193 if (offset + size > DMEMSZ) {
194 printf("fbuf: read too large, offset %ld size %d\n",
199 p = (uint8_t *)&sc->memregs + offset;
206 value = *(uint16_t *)p;
209 value = *(uint32_t *)p;
212 value = *(uint64_t *)p;
215 printf("fbuf: read unknown size %d\n", size);
219 DPRINTF(DEBUG_VERBOSE,
220 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx\n",
221 offset, size, value));
227 pci_fbuf_parse_opts(struct pci_fbuf_softc *sc, char *opts)
229 char *uopts, *xopts, *config;
234 uopts = strdup(opts);
235 for (xopts = strtok(uopts, ",");
237 xopts = strtok(NULL, ",")) {
238 if (strcmp(xopts, "wait") == 0) {
243 if ((config = strchr(xopts, '=')) == NULL) {
244 pci_fbuf_usage(xopts);
251 DPRINTF(DEBUG_VERBOSE, ("pci_fbuf option %s = %s",
254 if (!strcmp(xopts, "tcp") || !strcmp(xopts, "rfb")) {
256 * IPv4 -- host-ip:port
257 * IPv6 -- [host-ip%zone]:port
258 * XXX for now port is mandatory.
260 tmpstr = strsep(&config, "]");
262 if (tmpstr[0] == '[')
264 sc->rfb_host = tmpstr;
265 if (config[0] == ':')
268 pci_fbuf_usage(xopts);
272 sc->rfb_port = atoi(config);
275 tmpstr = strsep(&config, ":");
277 sc->rfb_port = atoi(tmpstr);
279 sc->rfb_port = atoi(config);
280 sc->rfb_host = tmpstr;
283 } else if (!strcmp(xopts, "vga")) {
284 if (!strcmp(config, "off")) {
286 } else if (!strcmp(config, "io")) {
289 } else if (!strcmp(config, "on")) {
293 pci_fbuf_usage(xopts);
297 } else if (!strcmp(xopts, "w")) {
298 sc->memregs.width = atoi(config);
299 if (sc->memregs.width > COLS_MAX) {
300 pci_fbuf_usage(xopts);
303 } else if (sc->memregs.width == 0)
304 sc->memregs.width = 1920;
305 } else if (!strcmp(xopts, "h")) {
306 sc->memregs.height = atoi(config);
307 if (sc->memregs.height > ROWS_MAX) {
308 pci_fbuf_usage(xopts);
311 } else if (sc->memregs.height == 0)
312 sc->memregs.height = 1080;
313 } else if (!strcmp(xopts, "password")) {
314 sc->rfb_password = config;
316 pci_fbuf_usage(xopts);
327 extern void vga_render(struct bhyvegc *gc, void *arg);
330 pci_fbuf_render(struct bhyvegc *gc, void *arg)
332 struct pci_fbuf_softc *sc;
336 if (sc->vga_full && sc->gc_image->vgamode) {
337 /* TODO: mode switching to vga and vesa should use the special
338 * EFI-bhyve protocol port.
340 vga_render(gc, sc->vgasc);
343 if (sc->gc_width != sc->memregs.width ||
344 sc->gc_height != sc->memregs.height) {
345 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
346 sc->gc_width = sc->memregs.width;
347 sc->gc_height = sc->memregs.height;
354 pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
357 struct pci_fbuf_softc *sc;
359 if (fbuf_sc != NULL) {
360 EPRINTLN("Only one frame buffer device is allowed.");
364 sc = calloc(1, sizeof(struct pci_fbuf_softc));
368 /* initialize config space */
369 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
370 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
371 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
372 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
374 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
377 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
380 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
383 sc->fbaddr = pi->pi_bar[1].addr;
384 sc->memregs.fbsize = FB_SIZE;
385 sc->memregs.width = COLS_DEFAULT;
386 sc->memregs.height = ROWS_DEFAULT;
387 sc->memregs.depth = 32;
394 error = pci_fbuf_parse_opts(sc, opts);
398 /* XXX until VGA rendering is enabled */
399 if (sc->vga_full != 0) {
400 EPRINTLN("pci_fbuf: VGA rendering not enabled");
404 sc->fb_base = vm_create_devmem(ctx, VM_FRAMEBUFFER, "framebuffer", FB_SIZE);
405 if (sc->fb_base == MAP_FAILED) {
409 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]",
410 sc->fb_base, FB_SIZE));
413 * Map the framebuffer into the guest address space.
414 * XXX This may fail if the BAR is different than a prior
415 * run. In this case flag the error. This will be fixed
416 * when a change_memseg api is available.
418 prot = PROT_READ | PROT_WRITE;
419 if (vm_mmap_memseg(ctx, sc->fbaddr, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0) {
420 EPRINTLN("pci_fbuf: mapseg failed - try deleting VM and restarting");
425 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
426 console_fb_register(pci_fbuf_render, sc);
429 sc->vgasc = vga_init(!sc->vga_full);
430 sc->gc_image = console_get_image();
434 memset((void *)sc->fb_base, 0, FB_SIZE);
436 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password);
444 struct pci_devemu pci_fbuf = {
446 .pe_init = pci_fbuf_init,
447 .pe_barwrite = pci_fbuf_write,
448 .pe_barread = pci_fbuf_read
450 PCI_EMUL_SET(pci_fbuf);