2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015 Nahanni Systems, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/types.h>
32 #include <machine/vmm.h>
33 #include <machine/vmm_snapshot.h>
51 #include "amd64/vga.h"
55 * bhyve Framebuffer device emulation.
56 * BAR0 points to the current mode information.
57 * BAR1 is the 32-bit framebuffer address.
59 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
62 static int fbuf_debug = 1;
64 #define DEBUG_VERBOSE 4
65 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params
69 #define MB (1024 * 1024UL)
73 #define FB_SIZE (32*MB)
78 #define COLS_DEFAULT 1024
79 #define ROWS_DEFAULT 768
84 struct pci_fbuf_softc {
85 struct pci_devinst *fsc_pi;
92 uint8_t reserved[116];
108 struct bhyvegc_image *gc_image;
111 static struct pci_fbuf_softc *fbuf_sc;
113 #define PCI_FBUF_MSI_MSGS 4
116 pci_fbuf_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
119 struct pci_fbuf_softc *sc;
126 DPRINTF(DEBUG_VERBOSE,
127 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx",
128 offset, size, value));
130 if (offset + size > DMEMSZ) {
131 printf("fbuf: write too large, offset %ld size %d\n",
136 p = (uint8_t *)&sc->memregs + offset;
143 *(uint16_t *)p = value;
146 *(uint32_t *)p = value;
149 *(uint64_t *)p = value;
152 printf("fbuf: write unknown size %d\n", size);
156 if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
157 sc->memregs.height == 0) {
158 DPRINTF(DEBUG_INFO, ("switching to VGA mode"));
159 sc->gc_image->vgamode = 1;
162 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
163 sc->memregs.height != 0) {
164 DPRINTF(DEBUG_INFO, ("switching to VESA mode"));
165 sc->gc_image->vgamode = 0;
170 pci_fbuf_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
172 struct pci_fbuf_softc *sc;
181 if (offset + size > DMEMSZ) {
182 printf("fbuf: read too large, offset %ld size %d\n",
187 p = (uint8_t *)&sc->memregs + offset;
194 value = *(uint16_t *)p;
197 value = *(uint32_t *)p;
200 value = *(uint64_t *)p;
203 printf("fbuf: read unknown size %d\n", size);
207 DPRINTF(DEBUG_VERBOSE,
208 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx",
209 offset, size, value));
215 pci_fbuf_baraddr(struct pci_devinst *pi, int baridx, int enabled,
218 struct pci_fbuf_softc *sc;
226 if (vm_munmap_memseg(pi->pi_vmctx, sc->fbaddr, FB_SIZE) != 0)
227 EPRINTLN("pci_fbuf: munmap_memseg failed");
230 prot = PROT_READ | PROT_WRITE;
231 if (vm_mmap_memseg(pi->pi_vmctx, address, VM_FRAMEBUFFER, 0,
233 EPRINTLN("pci_fbuf: mmap_memseg failed");
234 sc->fbaddr = address;
240 pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl)
245 sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false);
247 /* Prefer "rfb" to "tcp". */
248 value = get_config_value_node(nvl, "rfb");
250 value = get_config_value_node(nvl, "tcp");
253 * IPv4 -- host-ip:port
254 * IPv6 -- [host-ip%zone]:port
255 * XXX for now port is mandatory for IPv4.
257 if (value[0] == '[') {
258 cp = strchr(value + 1, ']');
259 if (cp == NULL || cp == value + 1) {
260 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
264 sc->rfb_host = strndup(value + 1, cp - (value + 1));
270 "fbuf: Missing port number: \"%s\"",
274 sc->rfb_port = atoi(cp);
275 } else if (*cp != '\0') {
276 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
281 cp = strchr(value, ':');
283 sc->rfb_port = atoi(value);
285 sc->rfb_host = strndup(value, cp - value);
289 "fbuf: Missing port number: \"%s\"",
293 sc->rfb_port = atoi(cp);
298 value = get_config_value_node(nvl, "vga");
300 if (strcmp(value, "off") == 0) {
302 } else if (strcmp(value, "io") == 0) {
305 } else if (strcmp(value, "on") == 0) {
309 EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value);
314 value = get_config_value_node(nvl, "w");
316 sc->memregs.width = atoi(value);
317 if (sc->memregs.width > COLS_MAX) {
318 EPRINTLN("fbuf: width %d too large", sc->memregs.width);
321 if (sc->memregs.width == 0)
322 sc->memregs.width = 1920;
325 value = get_config_value_node(nvl, "h");
327 sc->memregs.height = atoi(value);
328 if (sc->memregs.height > ROWS_MAX) {
329 EPRINTLN("fbuf: height %d too large",
333 if (sc->memregs.height == 0)
334 sc->memregs.height = 1080;
337 value = get_config_value_node(nvl, "password");
339 sc->rfb_password = strdup(value);
345 pci_fbuf_render(struct bhyvegc *gc, void *arg)
347 struct pci_fbuf_softc *sc;
351 if (sc->vga_full && sc->gc_image->vgamode) {
352 /* TODO: mode switching to vga and vesa should use the special
353 * EFI-bhyve protocol port.
355 vga_render(gc, sc->vgasc);
358 if (sc->gc_width != sc->memregs.width ||
359 sc->gc_height != sc->memregs.height) {
360 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
361 sc->gc_width = sc->memregs.width;
362 sc->gc_height = sc->memregs.height;
367 pci_fbuf_init(struct pci_devinst *pi, nvlist_t *nvl)
370 struct pci_fbuf_softc *sc;
372 if (fbuf_sc != NULL) {
373 EPRINTLN("Only one frame buffer device is allowed.");
377 sc = calloc(1, sizeof(struct pci_fbuf_softc));
381 /* initialize config space */
382 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
383 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
384 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
385 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
387 sc->fb_base = vm_create_devmem(pi->pi_vmctx, VM_FRAMEBUFFER,
388 "framebuffer", FB_SIZE);
389 if (sc->fb_base == MAP_FAILED) {
394 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
397 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
400 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
403 sc->memregs.fbsize = FB_SIZE;
404 sc->memregs.width = COLS_DEFAULT;
405 sc->memregs.height = ROWS_DEFAULT;
406 sc->memregs.depth = 32;
413 error = pci_fbuf_parse_config(sc, nvl);
417 /* XXX until VGA rendering is enabled */
418 if (sc->vga_full != 0) {
419 EPRINTLN("pci_fbuf: VGA rendering not enabled");
423 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]",
424 sc->fb_base, FB_SIZE));
426 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
427 console_fb_register(pci_fbuf_render, sc);
430 sc->vgasc = vga_init(!sc->vga_full);
431 sc->gc_image = console_get_image();
435 memset((void *)sc->fb_base, 0, FB_SIZE);
437 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password);
445 #ifdef BHYVE_SNAPSHOT
447 pci_fbuf_snapshot(struct vm_snapshot_meta *meta)
451 SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err);
458 static const struct pci_devemu pci_fbuf = {
460 .pe_init = pci_fbuf_init,
461 .pe_barwrite = pci_fbuf_write,
462 .pe_barread = pci_fbuf_read,
463 .pe_baraddr = pci_fbuf_baraddr,
464 #ifdef BHYVE_SNAPSHOT
465 .pe_snapshot = pci_fbuf_snapshot,
468 PCI_EMUL_SET(pci_fbuf);