2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015 Nahanni Systems, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/types.h>
37 #include <machine/vmm.h>
38 #include <machine/vmm_snapshot.h>
59 * bhyve Framebuffer device emulation.
60 * BAR0 points to the current mode information.
61 * BAR1 is the 32-bit framebuffer address.
63 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
66 static int fbuf_debug = 1;
68 #define DEBUG_VERBOSE 4
69 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params
73 #define MB (1024 * 1024UL)
77 #define FB_SIZE (16*MB)
82 #define COLS_DEFAULT 1024
83 #define ROWS_DEFAULT 768
88 struct pci_fbuf_softc {
89 struct pci_devinst *fsc_pi;
96 uint8_t reserved[116];
112 struct bhyvegc_image *gc_image;
115 static struct pci_fbuf_softc *fbuf_sc;
117 #define PCI_FBUF_MSI_MSGS 4
120 pci_fbuf_write(struct vmctx *ctx __unused,
121 struct pci_devinst *pi, int baridx, uint64_t offset, int size,
124 struct pci_fbuf_softc *sc;
131 DPRINTF(DEBUG_VERBOSE,
132 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx",
133 offset, size, value));
135 if (offset + size > DMEMSZ) {
136 printf("fbuf: write too large, offset %ld size %d\n",
141 p = (uint8_t *)&sc->memregs + offset;
148 *(uint16_t *)p = value;
151 *(uint32_t *)p = value;
154 *(uint64_t *)p = value;
157 printf("fbuf: write unknown size %d\n", size);
161 if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
162 sc->memregs.height == 0) {
163 DPRINTF(DEBUG_INFO, ("switching to VGA mode"));
164 sc->gc_image->vgamode = 1;
167 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
168 sc->memregs.height != 0) {
169 DPRINTF(DEBUG_INFO, ("switching to VESA mode"));
170 sc->gc_image->vgamode = 0;
175 pci_fbuf_read(struct vmctx *ctx __unused,
176 struct pci_devinst *pi, int baridx, uint64_t offset, int size)
178 struct pci_fbuf_softc *sc;
187 if (offset + size > DMEMSZ) {
188 printf("fbuf: read too large, offset %ld size %d\n",
193 p = (uint8_t *)&sc->memregs + offset;
200 value = *(uint16_t *)p;
203 value = *(uint32_t *)p;
206 value = *(uint64_t *)p;
209 printf("fbuf: read unknown size %d\n", size);
213 DPRINTF(DEBUG_VERBOSE,
214 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx",
215 offset, size, value));
221 pci_fbuf_baraddr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
222 int enabled, uint64_t address)
224 struct pci_fbuf_softc *sc;
232 if (vm_munmap_memseg(ctx, sc->fbaddr, FB_SIZE) != 0)
233 EPRINTLN("pci_fbuf: munmap_memseg failed");
236 prot = PROT_READ | PROT_WRITE;
237 if (vm_mmap_memseg(ctx, address, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0)
238 EPRINTLN("pci_fbuf: mmap_memseg failed");
239 sc->fbaddr = address;
245 pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl)
250 sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false);
252 /* Prefer "rfb" to "tcp". */
253 value = get_config_value_node(nvl, "rfb");
255 value = get_config_value_node(nvl, "tcp");
258 * IPv4 -- host-ip:port
259 * IPv6 -- [host-ip%zone]:port
260 * XXX for now port is mandatory for IPv4.
262 if (value[0] == '[') {
263 cp = strchr(value + 1, ']');
264 if (cp == NULL || cp == value + 1) {
265 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
269 sc->rfb_host = strndup(value + 1, cp - (value + 1));
275 "fbuf: Missing port number: \"%s\"",
279 sc->rfb_port = atoi(cp);
280 } else if (*cp != '\0') {
281 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
286 cp = strchr(value, ':');
288 sc->rfb_port = atoi(value);
290 sc->rfb_host = strndup(value, cp - value);
294 "fbuf: Missing port number: \"%s\"",
298 sc->rfb_port = atoi(cp);
303 value = get_config_value_node(nvl, "vga");
305 if (strcmp(value, "off") == 0) {
307 } else if (strcmp(value, "io") == 0) {
310 } else if (strcmp(value, "on") == 0) {
314 EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value);
319 value = get_config_value_node(nvl, "w");
321 sc->memregs.width = atoi(value);
322 if (sc->memregs.width > COLS_MAX) {
323 EPRINTLN("fbuf: width %d too large", sc->memregs.width);
326 if (sc->memregs.width == 0)
327 sc->memregs.width = 1920;
330 value = get_config_value_node(nvl, "h");
332 sc->memregs.height = atoi(value);
333 if (sc->memregs.height > ROWS_MAX) {
334 EPRINTLN("fbuf: height %d too large",
338 if (sc->memregs.height == 0)
339 sc->memregs.height = 1080;
342 value = get_config_value_node(nvl, "password");
344 sc->rfb_password = strdup(value);
350 pci_fbuf_render(struct bhyvegc *gc, void *arg)
352 struct pci_fbuf_softc *sc;
356 if (sc->vga_full && sc->gc_image->vgamode) {
357 /* TODO: mode switching to vga and vesa should use the special
358 * EFI-bhyve protocol port.
360 vga_render(gc, sc->vgasc);
363 if (sc->gc_width != sc->memregs.width ||
364 sc->gc_height != sc->memregs.height) {
365 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
366 sc->gc_width = sc->memregs.width;
367 sc->gc_height = sc->memregs.height;
374 pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
377 struct pci_fbuf_softc *sc;
379 if (fbuf_sc != NULL) {
380 EPRINTLN("Only one frame buffer device is allowed.");
384 sc = calloc(1, sizeof(struct pci_fbuf_softc));
388 /* initialize config space */
389 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
390 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
391 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
392 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
394 sc->fb_base = vm_create_devmem(
395 ctx, VM_FRAMEBUFFER, "framebuffer", FB_SIZE);
396 if (sc->fb_base == MAP_FAILED) {
401 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
404 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
407 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
410 sc->memregs.fbsize = FB_SIZE;
411 sc->memregs.width = COLS_DEFAULT;
412 sc->memregs.height = ROWS_DEFAULT;
413 sc->memregs.depth = 32;
420 error = pci_fbuf_parse_config(sc, nvl);
424 /* XXX until VGA rendering is enabled */
425 if (sc->vga_full != 0) {
426 EPRINTLN("pci_fbuf: VGA rendering not enabled");
430 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]",
431 sc->fb_base, FB_SIZE));
433 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
434 console_fb_register(pci_fbuf_render, sc);
437 sc->vgasc = vga_init(!sc->vga_full);
438 sc->gc_image = console_get_image();
442 memset((void *)sc->fb_base, 0, FB_SIZE);
444 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password);
452 #ifdef BHYVE_SNAPSHOT
454 pci_fbuf_snapshot(struct vm_snapshot_meta *meta)
458 SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err);
465 static const struct pci_devemu pci_fbuf = {
467 .pe_init = pci_fbuf_init,
468 .pe_barwrite = pci_fbuf_write,
469 .pe_barread = pci_fbuf_read,
470 .pe_baraddr = pci_fbuf_baraddr,
471 #ifdef BHYVE_SNAPSHOT
472 .pe_snapshot = pci_fbuf_snapshot,
475 PCI_EMUL_SET(pci_fbuf);