2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015 Nahanni Systems, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/types.h>
37 #include <machine/vmm.h>
38 #include <machine/vmm_snapshot.h>
58 * bhyve Framebuffer device emulation.
59 * BAR0 points to the current mode information.
60 * BAR1 is the 32-bit framebuffer address.
62 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
65 static int fbuf_debug = 1;
67 #define DEBUG_VERBOSE 4
68 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params
72 #define MB (1024 * 1024UL)
76 #define FB_SIZE (16*MB)
81 #define COLS_DEFAULT 1024
82 #define ROWS_DEFAULT 768
87 struct pci_fbuf_softc {
88 struct pci_devinst *fsc_pi;
95 uint8_t reserved[116];
111 struct bhyvegc_image *gc_image;
114 static struct pci_fbuf_softc *fbuf_sc;
116 #define PCI_FBUF_MSI_MSGS 4
119 pci_fbuf_usage(char *opt)
122 EPRINTLN("Invalid fbuf emulation option \"%s\"", opt);
123 EPRINTLN("fbuf: {wait,}{vga=on|io|off,}rfb=<ip>:port"
124 "{,w=width}{,h=height}");
128 pci_fbuf_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
129 int baridx, uint64_t offset, int size, uint64_t value)
131 struct pci_fbuf_softc *sc;
138 DPRINTF(DEBUG_VERBOSE,
139 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx",
140 offset, size, value));
142 if (offset + size > DMEMSZ) {
143 printf("fbuf: write too large, offset %ld size %d\n",
148 p = (uint8_t *)&sc->memregs + offset;
155 *(uint16_t *)p = value;
158 *(uint32_t *)p = value;
161 *(uint64_t *)p = value;
164 printf("fbuf: write unknown size %d\n", size);
168 if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
169 sc->memregs.height == 0) {
170 DPRINTF(DEBUG_INFO, ("switching to VGA mode"));
171 sc->gc_image->vgamode = 1;
174 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
175 sc->memregs.height != 0) {
176 DPRINTF(DEBUG_INFO, ("switching to VESA mode"));
177 sc->gc_image->vgamode = 0;
182 pci_fbuf_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
183 int baridx, uint64_t offset, int size)
185 struct pci_fbuf_softc *sc;
194 if (offset + size > DMEMSZ) {
195 printf("fbuf: read too large, offset %ld size %d\n",
200 p = (uint8_t *)&sc->memregs + offset;
207 value = *(uint16_t *)p;
210 value = *(uint32_t *)p;
213 value = *(uint64_t *)p;
216 printf("fbuf: read unknown size %d\n", size);
220 DPRINTF(DEBUG_VERBOSE,
221 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx",
222 offset, size, value));
228 pci_fbuf_parse_opts(struct pci_fbuf_softc *sc, char *opts)
230 char *uopts, *uoptsbak, *xopts, *config;
235 uoptsbak = uopts = strdup(opts);
236 while ((xopts = strsep(&uopts, ",")) != NULL) {
237 if (strcmp(xopts, "wait") == 0) {
242 if ((config = strchr(xopts, '=')) == NULL) {
243 pci_fbuf_usage(xopts);
250 DPRINTF(DEBUG_VERBOSE, ("pci_fbuf option %s = %s",
253 if (!strcmp(xopts, "tcp") || !strcmp(xopts, "rfb")) {
255 * IPv4 -- host-ip:port
256 * IPv6 -- [host-ip%zone]:port
257 * XXX for now port is mandatory.
259 tmpstr = strsep(&config, "]");
261 if (tmpstr[0] == '[')
263 sc->rfb_host = strdup(tmpstr);
264 if (config[0] == ':')
267 pci_fbuf_usage(xopts);
271 sc->rfb_port = atoi(config);
274 tmpstr = strsep(&config, ":");
276 sc->rfb_port = atoi(tmpstr);
278 sc->rfb_port = atoi(config);
279 sc->rfb_host = strdup(tmpstr);
282 } else if (!strcmp(xopts, "vga")) {
283 if (!strcmp(config, "off")) {
285 } else if (!strcmp(config, "io")) {
288 } else if (!strcmp(config, "on")) {
292 pci_fbuf_usage(xopts);
296 } else if (!strcmp(xopts, "w")) {
297 sc->memregs.width = atoi(config);
298 if (sc->memregs.width > COLS_MAX) {
299 pci_fbuf_usage(xopts);
302 } else if (sc->memregs.width == 0)
303 sc->memregs.width = 1920;
304 } else if (!strcmp(xopts, "h")) {
305 sc->memregs.height = atoi(config);
306 if (sc->memregs.height > ROWS_MAX) {
307 pci_fbuf_usage(xopts);
310 } else if (sc->memregs.height == 0)
311 sc->memregs.height = 1080;
312 } else if (!strcmp(xopts, "password")) {
313 sc->rfb_password = strdup(config);
315 pci_fbuf_usage(xopts);
327 extern void vga_render(struct bhyvegc *gc, void *arg);
330 pci_fbuf_render(struct bhyvegc *gc, void *arg)
332 struct pci_fbuf_softc *sc;
336 if (sc->vga_full && sc->gc_image->vgamode) {
337 /* TODO: mode switching to vga and vesa should use the special
338 * EFI-bhyve protocol port.
340 vga_render(gc, sc->vgasc);
343 if (sc->gc_width != sc->memregs.width ||
344 sc->gc_height != sc->memregs.height) {
345 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
346 sc->gc_width = sc->memregs.width;
347 sc->gc_height = sc->memregs.height;
354 pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
357 struct pci_fbuf_softc *sc;
359 if (fbuf_sc != NULL) {
360 EPRINTLN("Only one frame buffer device is allowed.");
364 sc = calloc(1, sizeof(struct pci_fbuf_softc));
368 /* initialize config space */
369 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
370 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
371 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
372 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
374 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
377 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
380 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
383 sc->fbaddr = pi->pi_bar[1].addr;
384 sc->memregs.fbsize = FB_SIZE;
385 sc->memregs.width = COLS_DEFAULT;
386 sc->memregs.height = ROWS_DEFAULT;
387 sc->memregs.depth = 32;
394 error = pci_fbuf_parse_opts(sc, opts);
398 /* XXX until VGA rendering is enabled */
399 if (sc->vga_full != 0) {
400 EPRINTLN("pci_fbuf: VGA rendering not enabled");
404 sc->fb_base = vm_create_devmem(ctx, VM_FRAMEBUFFER, "framebuffer", FB_SIZE);
405 if (sc->fb_base == MAP_FAILED) {
409 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]",
410 sc->fb_base, FB_SIZE));
413 * Map the framebuffer into the guest address space.
414 * XXX This may fail if the BAR is different than a prior
415 * run. In this case flag the error. This will be fixed
416 * when a change_memseg api is available.
418 prot = PROT_READ | PROT_WRITE;
419 if (vm_mmap_memseg(ctx, sc->fbaddr, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0) {
420 EPRINTLN("pci_fbuf: mapseg failed - try deleting VM and restarting");
425 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
426 console_fb_register(pci_fbuf_render, sc);
429 sc->vgasc = vga_init(!sc->vga_full);
430 sc->gc_image = console_get_image();
434 memset((void *)sc->fb_base, 0, FB_SIZE);
436 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password);
444 #ifdef BHYVE_SNAPSHOT
446 pci_fbuf_snapshot(struct vm_snapshot_meta *meta)
450 SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err);
457 struct pci_devemu pci_fbuf = {
459 .pe_init = pci_fbuf_init,
460 .pe_barwrite = pci_fbuf_write,
461 .pe_barread = pci_fbuf_read,
462 #ifdef BHYVE_SNAPSHOT
463 .pe_snapshot = pci_fbuf_snapshot,
466 PCI_EMUL_SET(pci_fbuf);