2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2016 Alex Teaca <iateaca@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
43 #define PCIR_HDCTL 0x40
44 #define INTEL_VENDORID 0x8086
45 #define HDA_INTEL_82801G 0x27d8
47 #define HDA_IOSS_NO 0x08
48 #define HDA_OSS_NO 0x04
49 #define HDA_ISS_NO 0x04
50 #define HDA_CODEC_MAX 0x0f
51 #define HDA_LAST_OFFSET \
52 (0x2084 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
53 #define HDA_CORB_ENTRY_LEN 0x04
54 #define HDA_RIRB_ENTRY_LEN 0x08
55 #define HDA_BDL_ENTRY_LEN 0x10
56 #define HDA_DMA_PIB_ENTRY_LEN 0x08
57 #define HDA_STREAM_TAGS_CNT 0x10
58 #define HDA_STREAM_REGS_BASE 0x80
59 #define HDA_STREAM_REGS_LEN 0x20
61 #define HDA_DMA_ACCESS_LEN (sizeof(uint32_t))
62 #define HDA_BDL_MAX_LEN 0x0100
64 #define HDAC_SDSTS_FIFORDY (1 << 5)
66 #define HDA_RIRBSTS_IRQ_MASK (HDAC_RIRBSTS_RINTFL | HDAC_RIRBSTS_RIRBOIS)
67 #define HDA_STATESTS_IRQ_MASK ((1 << HDA_CODEC_MAX) - 1)
68 #define HDA_SDSTS_IRQ_MASK \
69 (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS)
77 typedef void (*hda_set_reg_handler)(struct hda_softc *sc, uint32_t offset,
87 struct hda_bdle_desc {
93 struct hda_codec_cmd_ctl {
102 struct hda_stream_desc {
107 /* bp is the no. of bytes transferred in the current bdle */
109 /* be is the no. of bdles transferred in the bdl */
113 struct hda_bdle_desc bdl[HDA_BDL_MAX_LEN];
117 struct pci_devinst *pci_dev;
118 uint32_t regs[HDA_LAST_OFFSET];
122 uint64_t wall_clock_start;
124 struct hda_codec_cmd_ctl corb;
125 struct hda_codec_cmd_ctl rirb;
128 struct hda_codec_inst *codecs[HDA_CODEC_MAX];
130 /* Base Address of the DMA Position Buffer */
133 struct hda_stream_desc streams[HDA_IOSS_NO];
134 /* 2 tables for output and input */
135 uint8_t stream_map[2][HDA_STREAM_TAGS_CNT];
139 * HDA module function declarations
141 static inline void hda_set_reg_by_offset(struct hda_softc *sc, uint32_t offset,
143 static inline uint32_t hda_get_reg_by_offset(struct hda_softc *sc,
145 static inline void hda_set_field_by_offset(struct hda_softc *sc,
146 uint32_t offset, uint32_t mask, uint32_t value);
148 static struct hda_softc *hda_init(nvlist_t *nvl);
149 static void hda_update_intr(struct hda_softc *sc);
150 static void hda_response_interrupt(struct hda_softc *sc);
151 static int hda_codec_constructor(struct hda_softc *sc,
152 struct hda_codec_class *codec, const char *play, const char *rec);
153 static struct hda_codec_class *hda_find_codec_class(const char *name);
155 static int hda_send_command(struct hda_softc *sc, uint32_t verb);
156 static int hda_notify_codecs(struct hda_softc *sc, uint8_t run,
157 uint8_t stream, uint8_t dir);
158 static void hda_reset(struct hda_softc *sc);
159 static void hda_reset_regs(struct hda_softc *sc);
160 static void hda_stream_reset(struct hda_softc *sc, uint8_t stream_ind);
161 static int hda_stream_start(struct hda_softc *sc, uint8_t stream_ind);
162 static int hda_stream_stop(struct hda_softc *sc, uint8_t stream_ind);
163 static uint32_t hda_read(struct hda_softc *sc, uint32_t offset);
164 static int hda_write(struct hda_softc *sc, uint32_t offset, uint8_t size,
167 static inline void hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl *p);
168 static int hda_corb_start(struct hda_softc *sc);
169 static int hda_corb_run(struct hda_softc *sc);
170 static int hda_rirb_start(struct hda_softc *sc);
172 static void *hda_dma_get_vaddr(struct hda_softc *sc, uint64_t dma_paddr,
174 static void hda_dma_st_dword(void *dma_vaddr, uint32_t data);
175 static uint32_t hda_dma_ld_dword(void *dma_vaddr);
177 static inline uint8_t hda_get_stream_by_offsets(uint32_t offset,
179 static inline uint32_t hda_get_offset_stream(uint8_t stream_ind);
181 static void hda_set_gctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
182 static void hda_set_statests(struct hda_softc *sc, uint32_t offset,
184 static void hda_set_corbwp(struct hda_softc *sc, uint32_t offset, uint32_t old);
185 static void hda_set_corbctl(struct hda_softc *sc, uint32_t offset,
187 static void hda_set_rirbctl(struct hda_softc *sc, uint32_t offset,
189 static void hda_set_rirbsts(struct hda_softc *sc, uint32_t offset,
191 static void hda_set_dpiblbase(struct hda_softc *sc, uint32_t offset,
193 static void hda_set_sdctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
194 static void hda_set_sdctl2(struct hda_softc *sc, uint32_t offset, uint32_t old);
195 static void hda_set_sdsts(struct hda_softc *sc, uint32_t offset, uint32_t old);
197 static int hda_signal_state_change(struct hda_codec_inst *hci);
198 static int hda_response(struct hda_codec_inst *hci, uint32_t response,
200 static int hda_transfer(struct hda_codec_inst *hci, uint8_t stream,
201 uint8_t dir, uint8_t *buf, size_t count);
203 static void hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib);
204 static uint64_t hda_get_clock_ns(void);
207 * PCI HDA function declarations
209 static int pci_hda_init(struct pci_devinst *pi, nvlist_t *nvl);
210 static void pci_hda_write(struct pci_devinst *pi, int baridx, uint64_t offset,
211 int size, uint64_t value);
212 static uint64_t pci_hda_read(struct pci_devinst *pi, int baridx,
213 uint64_t offset, int size);
218 static const hda_set_reg_handler hda_set_reg_table[] = {
219 [HDAC_GCTL] = hda_set_gctl,
220 [HDAC_STATESTS] = hda_set_statests,
221 [HDAC_CORBWP] = hda_set_corbwp,
222 [HDAC_CORBCTL] = hda_set_corbctl,
223 [HDAC_RIRBCTL] = hda_set_rirbctl,
224 [HDAC_RIRBSTS] = hda_set_rirbsts,
225 [HDAC_DPIBLBASE] = hda_set_dpiblbase,
227 #define HDAC_ISTREAM(n, iss, oss) \
228 [_HDAC_ISDCTL(n, iss, oss)] = hda_set_sdctl, \
229 [_HDAC_ISDCTL(n, iss, oss) + 2] = hda_set_sdctl2, \
230 [_HDAC_ISDSTS(n, iss, oss)] = hda_set_sdsts, \
232 #define HDAC_OSTREAM(n, iss, oss) \
233 [_HDAC_OSDCTL(n, iss, oss)] = hda_set_sdctl, \
234 [_HDAC_OSDCTL(n, iss, oss) + 2] = hda_set_sdctl2, \
235 [_HDAC_OSDSTS(n, iss, oss)] = hda_set_sdsts, \
237 HDAC_ISTREAM(0, HDA_ISS_NO, HDA_OSS_NO)
238 HDAC_ISTREAM(1, HDA_ISS_NO, HDA_OSS_NO)
239 HDAC_ISTREAM(2, HDA_ISS_NO, HDA_OSS_NO)
240 HDAC_ISTREAM(3, HDA_ISS_NO, HDA_OSS_NO)
242 HDAC_OSTREAM(0, HDA_ISS_NO, HDA_OSS_NO)
243 HDAC_OSTREAM(1, HDA_ISS_NO, HDA_OSS_NO)
244 HDAC_OSTREAM(2, HDA_ISS_NO, HDA_OSS_NO)
245 HDAC_OSTREAM(3, HDA_ISS_NO, HDA_OSS_NO)
248 static const uint16_t hda_corb_sizes[] = {
249 [HDAC_CORBSIZE_CORBSIZE_2] = 2,
250 [HDAC_CORBSIZE_CORBSIZE_16] = 16,
251 [HDAC_CORBSIZE_CORBSIZE_256] = 256,
252 [HDAC_CORBSIZE_CORBSIZE_MASK] = 0,
255 static const uint16_t hda_rirb_sizes[] = {
256 [HDAC_RIRBSIZE_RIRBSIZE_2] = 2,
257 [HDAC_RIRBSIZE_RIRBSIZE_16] = 16,
258 [HDAC_RIRBSIZE_RIRBSIZE_256] = 256,
259 [HDAC_RIRBSIZE_RIRBSIZE_MASK] = 0,
262 static const struct hda_ops hops = {
263 .signal = hda_signal_state_change,
264 .response = hda_response,
265 .transfer = hda_transfer,
268 static const struct pci_devemu pci_de_hda = {
270 .pe_init = pci_hda_init,
271 .pe_barwrite = pci_hda_write,
272 .pe_barread = pci_hda_read
274 PCI_EMUL_SET(pci_de_hda);
276 SET_DECLARE(hda_codec_class_set, struct hda_codec_class);
283 * HDA module function definitions
287 hda_set_reg_by_offset(struct hda_softc *sc, uint32_t offset, uint32_t value)
289 assert(offset < HDA_LAST_OFFSET);
290 sc->regs[offset] = value;
293 static inline uint32_t
294 hda_get_reg_by_offset(struct hda_softc *sc, uint32_t offset)
296 assert(offset < HDA_LAST_OFFSET);
297 return sc->regs[offset];
301 hda_set_field_by_offset(struct hda_softc *sc, uint32_t offset,
302 uint32_t mask, uint32_t value)
304 uint32_t reg_value = 0;
306 reg_value = hda_get_reg_by_offset(sc, offset);
309 reg_value |= (value & mask);
311 hda_set_reg_by_offset(sc, offset, reg_value);
314 static struct hda_softc *
315 hda_init(nvlist_t *nvl)
317 struct hda_softc *sc = NULL;
318 struct hda_codec_class *codec = NULL;
325 dbg = fopen("/tmp/bhyve_hda.log", "w+");
328 sc = calloc(1, sizeof(*sc));
335 * TODO search all configured codecs
336 * For now we play with one single codec
338 codec = hda_find_codec_class("hda_codec");
340 value = get_config_value_node(nvl, "play");
344 play = strdup(value);
345 value = get_config_value_node(nvl, "rec");
350 DPRINTF("play: %s rec: %s", play, rec);
351 if (play != NULL || rec != NULL) {
352 err = hda_codec_constructor(sc, codec, play, rec);
363 hda_update_intr(struct hda_softc *sc)
365 struct pci_devinst *pi = sc->pci_dev;
366 uint32_t intctl = hda_get_reg_by_offset(sc, HDAC_INTCTL);
369 uint32_t rirbsts = 0;
371 uint32_t statests = 0;
375 /* update the CIS bits */
376 rirbsts = hda_get_reg_by_offset(sc, HDAC_RIRBSTS);
377 if (rirbsts & (HDAC_RIRBSTS_RINTFL | HDAC_RIRBSTS_RIRBOIS))
378 intsts |= HDAC_INTSTS_CIS;
380 wakeen = hda_get_reg_by_offset(sc, HDAC_WAKEEN);
381 statests = hda_get_reg_by_offset(sc, HDAC_STATESTS);
382 if (statests & wakeen)
383 intsts |= HDAC_INTSTS_CIS;
385 /* update the SIS bits */
386 for (i = 0; i < HDA_IOSS_NO; i++) {
387 off = hda_get_offset_stream(i);
388 sdsts = hda_get_reg_by_offset(sc, off + HDAC_SDSTS);
389 if (sdsts & HDAC_SDSTS_BCIS)
393 /* update the GIS bit */
395 intsts |= HDAC_INTSTS_GIS;
397 hda_set_reg_by_offset(sc, HDAC_INTSTS, intsts);
399 if ((intctl & HDAC_INTCTL_GIE) && ((intsts & \
400 ~HDAC_INTSTS_GIS) & intctl)) {
402 pci_lintr_assert(pi);
407 pci_lintr_deassert(pi);
414 hda_response_interrupt(struct hda_softc *sc)
416 uint8_t rirbctl = hda_get_reg_by_offset(sc, HDAC_RIRBCTL);
418 if ((rirbctl & HDAC_RIRBCTL_RINTCTL) && sc->rirb_cnt) {
420 hda_set_field_by_offset(sc, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL,
421 HDAC_RIRBSTS_RINTFL);
427 hda_codec_constructor(struct hda_softc *sc, struct hda_codec_class *codec,
428 const char *play, const char *rec)
430 struct hda_codec_inst *hci = NULL;
432 if (sc->codecs_no >= HDA_CODEC_MAX)
435 hci = calloc(1, sizeof(struct hda_codec_inst));
441 hci->cad = sc->codecs_no;
444 sc->codecs[sc->codecs_no++] = hci;
447 DPRINTF("This codec does not implement the init function");
451 return (codec->init(hci, play, rec));
454 static struct hda_codec_class *
455 hda_find_codec_class(const char *name)
457 struct hda_codec_class **pdpp = NULL, *pdp = NULL;
459 SET_FOREACH(pdpp, hda_codec_class_set) {
461 if (!strcmp(pdp->name, name)) {
470 hda_send_command(struct hda_softc *sc, uint32_t verb)
472 struct hda_codec_inst *hci = NULL;
473 struct hda_codec_class *codec = NULL;
474 uint8_t cad = (verb >> HDA_CMD_CAD_SHIFT) & 0x0f;
476 if (cad >= sc->codecs_no)
479 DPRINTF("cad: 0x%x verb: 0x%x", cad, verb);
481 hci = sc->codecs[cad];
487 if (!codec->command) {
488 DPRINTF("This codec does not implement the command function");
492 return (codec->command(hci, verb));
496 hda_notify_codecs(struct hda_softc *sc, uint8_t run, uint8_t stream,
499 struct hda_codec_inst *hci = NULL;
500 struct hda_codec_class *codec = NULL;
504 /* Notify each codec */
505 for (i = 0; i < sc->codecs_no; i++) {
513 err = codec->notify(hci, run, stream, dir);
519 return (i == sc->codecs_no ? (-1) : 0);
523 hda_reset(struct hda_softc *sc)
526 struct hda_codec_inst *hci = NULL;
527 struct hda_codec_class *codec = NULL;
531 /* Reset each codec */
532 for (i = 0; i < sc->codecs_no; i++) {
543 sc->wall_clock_start = hda_get_clock_ns();
547 hda_reset_regs(struct hda_softc *sc)
552 DPRINTF("Reset the HDA controller registers ...");
554 memset(sc->regs, 0, sizeof(sc->regs));
556 hda_set_reg_by_offset(sc, HDAC_GCAP,
558 (HDA_ISS_NO << HDAC_GCAP_ISS_SHIFT) |
559 (HDA_OSS_NO << HDAC_GCAP_OSS_SHIFT));
560 hda_set_reg_by_offset(sc, HDAC_VMAJ, 0x01);
561 hda_set_reg_by_offset(sc, HDAC_OUTPAY, 0x3c);
562 hda_set_reg_by_offset(sc, HDAC_INPAY, 0x1d);
563 hda_set_reg_by_offset(sc, HDAC_CORBSIZE,
564 HDAC_CORBSIZE_CORBSZCAP_256 | HDAC_CORBSIZE_CORBSIZE_256);
565 hda_set_reg_by_offset(sc, HDAC_RIRBSIZE,
566 HDAC_RIRBSIZE_RIRBSZCAP_256 | HDAC_RIRBSIZE_RIRBSIZE_256);
568 for (i = 0; i < HDA_IOSS_NO; i++) {
569 off = hda_get_offset_stream(i);
570 hda_set_reg_by_offset(sc, off + HDAC_SDFIFOS, HDA_FIFO_SIZE);
575 hda_stream_reset(struct hda_softc *sc, uint8_t stream_ind)
577 struct hda_stream_desc *st = &sc->streams[stream_ind];
578 uint32_t off = hda_get_offset_stream(stream_ind);
580 DPRINTF("Reset the HDA stream: 0x%x", stream_ind);
582 /* Reset the Stream Descriptor registers */
583 memset(sc->regs + HDA_STREAM_REGS_BASE + off, 0, HDA_STREAM_REGS_LEN);
585 /* Reset the Stream Descriptor */
586 memset(st, 0, sizeof(*st));
588 hda_set_field_by_offset(sc, off + HDAC_SDSTS,
589 HDAC_SDSTS_FIFORDY, HDAC_SDSTS_FIFORDY);
590 hda_set_field_by_offset(sc, off + HDAC_SDCTL0,
591 HDAC_SDCTL_SRST, HDAC_SDCTL_SRST);
595 hda_stream_start(struct hda_softc *sc, uint8_t stream_ind)
597 struct hda_stream_desc *st = &sc->streams[stream_ind];
598 struct hda_bdle_desc *bdle_desc = NULL;
599 struct hda_bdle *bdle = NULL;
601 uint32_t bdl_cnt = 0;
604 uint64_t bdl_paddr = 0;
605 void *bdl_vaddr = NULL;
606 uint32_t bdle_sz = 0;
607 uint64_t bdle_addrl = 0;
608 uint64_t bdle_addrh = 0;
609 uint64_t bdle_paddr = 0;
610 void *bdle_vaddr = NULL;
611 uint32_t off = hda_get_offset_stream(stream_ind);
618 lvi = hda_get_reg_by_offset(sc, off + HDAC_SDLVI);
619 bdpl = hda_get_reg_by_offset(sc, off + HDAC_SDBDPL);
620 bdpu = hda_get_reg_by_offset(sc, off + HDAC_SDBDPU);
623 assert(bdl_cnt <= HDA_BDL_MAX_LEN);
625 bdl_paddr = bdpl | (bdpu << 32);
626 bdl_vaddr = hda_dma_get_vaddr(sc, bdl_paddr,
627 HDA_BDL_ENTRY_LEN * bdl_cnt);
629 DPRINTF("Fail to get the guest virtual address");
633 DPRINTF("stream: 0x%x bdl_cnt: 0x%x bdl_paddr: 0x%lx",
634 stream_ind, bdl_cnt, bdl_paddr);
636 st->bdl_cnt = bdl_cnt;
638 bdle = (struct hda_bdle *)bdl_vaddr;
639 for (size_t i = 0; i < bdl_cnt; i++, bdle++) {
641 assert(!(bdle_sz % HDA_DMA_ACCESS_LEN));
643 bdle_addrl = bdle->addrl;
644 bdle_addrh = bdle->addrh;
646 bdle_paddr = bdle_addrl | (bdle_addrh << 32);
647 bdle_vaddr = hda_dma_get_vaddr(sc, bdle_paddr, bdle_sz);
649 DPRINTF("Fail to get the guest virtual address");
653 bdle_desc = &st->bdl[i];
654 bdle_desc->addr = bdle_vaddr;
655 bdle_desc->len = bdle_sz;
656 bdle_desc->ioc = bdle->ioc;
658 DPRINTF("bdle: 0x%zx bdle_sz: 0x%x", i, bdle_sz);
661 sdctl = hda_get_reg_by_offset(sc, off + HDAC_SDCTL0);
662 strm = (sdctl >> 20) & 0x0f;
663 dir = stream_ind >= HDA_ISS_NO;
665 DPRINTF("strm: 0x%x, dir: 0x%x", strm, dir);
667 sc->stream_map[dir][strm] = stream_ind;
673 hda_set_pib(sc, stream_ind, 0);
677 hda_notify_codecs(sc, 1, strm, dir);
683 hda_stream_stop(struct hda_softc *sc, uint8_t stream_ind)
685 struct hda_stream_desc *st = &sc->streams[stream_ind];
686 uint8_t strm = st->stream;
687 uint8_t dir = st->dir;
689 DPRINTF("stream: 0x%x, strm: 0x%x, dir: 0x%x", stream_ind, strm, dir);
693 hda_notify_codecs(sc, 0, strm, dir);
699 hda_read(struct hda_softc *sc, uint32_t offset)
701 if (offset == HDAC_WALCLK)
702 return (24 * (hda_get_clock_ns() - \
703 sc->wall_clock_start) / 1000);
705 return (hda_get_reg_by_offset(sc, offset));
709 hda_write(struct hda_softc *sc, uint32_t offset, uint8_t size, uint32_t value)
711 uint32_t old = hda_get_reg_by_offset(sc, offset);
712 uint32_t masks[] = {0x00000000, 0x000000ff, 0x0000ffff,
713 0x00ffffff, 0xffffffff};
714 hda_set_reg_handler set_reg_handler = NULL;
716 if (offset < nitems(hda_set_reg_table))
717 set_reg_handler = hda_set_reg_table[offset];
719 hda_set_field_by_offset(sc, offset, masks[size], value);
722 set_reg_handler(sc, offset, old);
728 hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl *p)
731 const char *name = p->name;
733 DPRINTF("%s size: %d", name, p->size);
734 DPRINTF("%s dma_vaddr: %p", name, p->dma_vaddr);
735 DPRINTF("%s wp: 0x%x", name, p->wp);
736 DPRINTF("%s rp: 0x%x", name, p->rp);
740 hda_corb_start(struct hda_softc *sc)
742 struct hda_codec_cmd_ctl *corb = &sc->corb;
743 uint8_t corbsize = 0;
744 uint64_t corblbase = 0;
745 uint64_t corbubase = 0;
746 uint64_t corbpaddr = 0;
750 corbsize = hda_get_reg_by_offset(sc, HDAC_CORBSIZE) & \
751 HDAC_CORBSIZE_CORBSIZE_MASK;
752 corb->size = hda_corb_sizes[corbsize];
755 DPRINTF("Invalid corb size");
759 corblbase = hda_get_reg_by_offset(sc, HDAC_CORBLBASE);
760 corbubase = hda_get_reg_by_offset(sc, HDAC_CORBUBASE);
762 corbpaddr = corblbase | (corbubase << 32);
763 DPRINTF("CORB dma_paddr: %p", (void *)corbpaddr);
765 corb->dma_vaddr = hda_dma_get_vaddr(sc, corbpaddr,
766 HDA_CORB_ENTRY_LEN * corb->size);
767 if (!corb->dma_vaddr) {
768 DPRINTF("Fail to get the guest virtual address");
772 corb->wp = hda_get_reg_by_offset(sc, HDAC_CORBWP);
773 corb->rp = hda_get_reg_by_offset(sc, HDAC_CORBRP);
777 hda_print_cmd_ctl_data(corb);
783 hda_corb_run(struct hda_softc *sc)
785 struct hda_codec_cmd_ctl *corb = &sc->corb;
789 corb->wp = hda_get_reg_by_offset(sc, HDAC_CORBWP);
791 while (corb->rp != corb->wp && corb->run) {
793 corb->rp %= corb->size;
795 verb = hda_dma_ld_dword((uint8_t *)corb->dma_vaddr +
796 HDA_CORB_ENTRY_LEN * corb->rp);
798 err = hda_send_command(sc, verb);
802 hda_set_reg_by_offset(sc, HDAC_CORBRP, corb->rp);
805 hda_response_interrupt(sc);
811 hda_rirb_start(struct hda_softc *sc)
813 struct hda_codec_cmd_ctl *rirb = &sc->rirb;
814 uint8_t rirbsize = 0;
815 uint64_t rirblbase = 0;
816 uint64_t rirbubase = 0;
817 uint64_t rirbpaddr = 0;
821 rirbsize = hda_get_reg_by_offset(sc, HDAC_RIRBSIZE) & \
822 HDAC_RIRBSIZE_RIRBSIZE_MASK;
823 rirb->size = hda_rirb_sizes[rirbsize];
826 DPRINTF("Invalid rirb size");
830 rirblbase = hda_get_reg_by_offset(sc, HDAC_RIRBLBASE);
831 rirbubase = hda_get_reg_by_offset(sc, HDAC_RIRBUBASE);
833 rirbpaddr = rirblbase | (rirbubase << 32);
834 DPRINTF("RIRB dma_paddr: %p", (void *)rirbpaddr);
836 rirb->dma_vaddr = hda_dma_get_vaddr(sc, rirbpaddr,
837 HDA_RIRB_ENTRY_LEN * rirb->size);
838 if (!rirb->dma_vaddr) {
839 DPRINTF("Fail to get the guest virtual address");
843 rirb->wp = hda_get_reg_by_offset(sc, HDAC_RIRBWP);
848 hda_print_cmd_ctl_data(rirb);
854 hda_dma_get_vaddr(struct hda_softc *sc, uint64_t dma_paddr, size_t len)
856 struct pci_devinst *pi = sc->pci_dev;
860 return (paddr_guest2host(pi->pi_vmctx, (uintptr_t)dma_paddr, len));
864 hda_dma_st_dword(void *dma_vaddr, uint32_t data)
866 *(uint32_t*)dma_vaddr = data;
870 hda_dma_ld_dword(void *dma_vaddr)
872 return (*(uint32_t*)dma_vaddr);
875 static inline uint8_t
876 hda_get_stream_by_offsets(uint32_t offset, uint8_t reg_offset)
878 uint8_t stream_ind = (offset - reg_offset) >> 5;
880 assert(stream_ind < HDA_IOSS_NO);
885 static inline uint32_t
886 hda_get_offset_stream(uint8_t stream_ind)
888 return (stream_ind << 5);
892 hda_set_gctl(struct hda_softc *sc, uint32_t offset, uint32_t old __unused)
894 uint32_t value = hda_get_reg_by_offset(sc, offset);
896 if (!(value & HDAC_GCTL_CRST)) {
902 hda_set_statests(struct hda_softc *sc, uint32_t offset, uint32_t old)
904 uint32_t value = hda_get_reg_by_offset(sc, offset);
906 hda_set_reg_by_offset(sc, offset, old);
908 /* clear the corresponding bits written by the software (guest) */
909 hda_set_field_by_offset(sc, offset, value & HDA_STATESTS_IRQ_MASK, 0);
915 hda_set_corbwp(struct hda_softc *sc, uint32_t offset __unused,
916 uint32_t old __unused)
922 hda_set_corbctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
924 uint32_t value = hda_get_reg_by_offset(sc, offset);
926 struct hda_codec_cmd_ctl *corb = NULL;
928 if (value & HDAC_CORBCTL_CORBRUN) {
929 if (!(old & HDAC_CORBCTL_CORBRUN)) {
930 err = hda_corb_start(sc);
935 memset(corb, 0, sizeof(*corb));
942 hda_set_rirbctl(struct hda_softc *sc, uint32_t offset, uint32_t old __unused)
944 uint32_t value = hda_get_reg_by_offset(sc, offset);
946 struct hda_codec_cmd_ctl *rirb = NULL;
948 if (value & HDAC_RIRBCTL_RIRBDMAEN) {
949 err = hda_rirb_start(sc);
953 memset(rirb, 0, sizeof(*rirb));
958 hda_set_rirbsts(struct hda_softc *sc, uint32_t offset, uint32_t old)
960 uint32_t value = hda_get_reg_by_offset(sc, offset);
962 hda_set_reg_by_offset(sc, offset, old);
964 /* clear the corresponding bits written by the software (guest) */
965 hda_set_field_by_offset(sc, offset, value & HDA_RIRBSTS_IRQ_MASK, 0);
971 hda_set_dpiblbase(struct hda_softc *sc, uint32_t offset, uint32_t old)
973 uint32_t value = hda_get_reg_by_offset(sc, offset);
974 uint64_t dpiblbase = 0;
975 uint64_t dpibubase = 0;
976 uint64_t dpibpaddr = 0;
978 if ((value & HDAC_DPLBASE_DPLBASE_DMAPBE) != (old & \
979 HDAC_DPLBASE_DPLBASE_DMAPBE)) {
980 if (value & HDAC_DPLBASE_DPLBASE_DMAPBE) {
981 dpiblbase = value & HDAC_DPLBASE_DPLBASE_MASK;
982 dpibubase = hda_get_reg_by_offset(sc, HDAC_DPIBUBASE);
984 dpibpaddr = dpiblbase | (dpibubase << 32);
985 DPRINTF("DMA Position In Buffer dma_paddr: %p",
988 sc->dma_pib_vaddr = hda_dma_get_vaddr(sc, dpibpaddr,
989 HDA_DMA_PIB_ENTRY_LEN * HDA_IOSS_NO);
990 if (!sc->dma_pib_vaddr) {
991 DPRINTF("Fail to get the guest \
996 DPRINTF("DMA Position In Buffer Reset");
997 sc->dma_pib_vaddr = NULL;
1003 hda_set_sdctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
1005 uint8_t stream_ind = hda_get_stream_by_offsets(offset, HDAC_SDCTL0);
1006 uint32_t value = hda_get_reg_by_offset(sc, offset);
1009 DPRINTF("stream_ind: 0x%x old: 0x%x value: 0x%x",
1010 stream_ind, old, value);
1012 if (value & HDAC_SDCTL_SRST) {
1013 hda_stream_reset(sc, stream_ind);
1016 if ((value & HDAC_SDCTL_RUN) != (old & HDAC_SDCTL_RUN)) {
1017 if (value & HDAC_SDCTL_RUN) {
1018 err = hda_stream_start(sc, stream_ind);
1021 err = hda_stream_stop(sc, stream_ind);
1028 hda_set_sdctl2(struct hda_softc *sc, uint32_t offset, uint32_t old __unused)
1030 uint32_t value = hda_get_reg_by_offset(sc, offset);
1032 hda_set_field_by_offset(sc, offset - 2, 0x00ff0000, value << 16);
1036 hda_set_sdsts(struct hda_softc *sc, uint32_t offset, uint32_t old)
1038 uint32_t value = hda_get_reg_by_offset(sc, offset);
1040 hda_set_reg_by_offset(sc, offset, old);
1042 /* clear the corresponding bits written by the software (guest) */
1043 hda_set_field_by_offset(sc, offset, value & HDA_SDSTS_IRQ_MASK, 0);
1045 hda_update_intr(sc);
1049 hda_signal_state_change(struct hda_codec_inst *hci)
1051 struct hda_softc *sc = NULL;
1052 uint32_t sdiwake = 0;
1057 DPRINTF("cad: 0x%x", hci->cad);
1060 sdiwake = 1 << hci->cad;
1062 hda_set_field_by_offset(sc, HDAC_STATESTS, sdiwake, sdiwake);
1063 hda_update_intr(sc);
1069 hda_response(struct hda_codec_inst *hci, uint32_t response, uint8_t unsol)
1071 struct hda_softc *sc = NULL;
1072 struct hda_codec_cmd_ctl *rirb = NULL;
1073 uint32_t response_ex = 0;
1074 uint8_t rintcnt = 0;
1077 assert(hci->cad <= HDA_CODEC_MAX);
1079 response_ex = hci->cad | unsol;
1088 rirb->wp %= rirb->size;
1090 hda_dma_st_dword((uint8_t *)rirb->dma_vaddr +
1091 HDA_RIRB_ENTRY_LEN * rirb->wp, response);
1092 hda_dma_st_dword((uint8_t *)rirb->dma_vaddr +
1093 HDA_RIRB_ENTRY_LEN * rirb->wp + 0x04, response_ex);
1095 hda_set_reg_by_offset(sc, HDAC_RIRBWP, rirb->wp);
1100 rintcnt = hda_get_reg_by_offset(sc, HDAC_RINTCNT);
1101 if (sc->rirb_cnt == rintcnt)
1102 hda_response_interrupt(sc);
1108 hda_transfer(struct hda_codec_inst *hci, uint8_t stream, uint8_t dir,
1109 uint8_t *buf, size_t count)
1111 struct hda_softc *sc = NULL;
1112 struct hda_stream_desc *st = NULL;
1113 struct hda_bdle_desc *bdl = NULL;
1114 struct hda_bdle_desc *bdle_desc = NULL;
1115 uint8_t stream_ind = 0;
1124 assert(!(count % HDA_DMA_ACCESS_LEN));
1127 DPRINTF("Invalid stream");
1133 assert(stream < HDA_STREAM_TAGS_CNT);
1134 stream_ind = sc->stream_map[dir][stream];
1137 assert(stream_ind < HDA_ISS_NO);
1139 assert(stream_ind >= HDA_ISS_NO && stream_ind < HDA_IOSS_NO);
1141 st = &sc->streams[stream_ind];
1143 DPRINTF("Stream 0x%x stopped", stream);
1147 assert(st->stream == stream);
1149 off = hda_get_offset_stream(stream_ind);
1151 lpib = hda_get_reg_by_offset(sc, off + HDAC_SDLPIB);
1155 assert(st->be < st->bdl_cnt);
1156 assert(st->bp < bdl[st->be].len);
1160 bdle_desc = &bdl[st->be];
1163 *(uint32_t *)buf = hda_dma_ld_dword(
1164 (uint8_t *)bdle_desc->addr + st->bp);
1166 hda_dma_st_dword((uint8_t *)bdle_desc->addr +
1167 st->bp, *(uint32_t *)buf);
1169 buf += HDA_DMA_ACCESS_LEN;
1170 st->bp += HDA_DMA_ACCESS_LEN;
1171 lpib += HDA_DMA_ACCESS_LEN;
1172 left -= HDA_DMA_ACCESS_LEN;
1174 if (st->bp == bdle_desc->len) {
1179 if (st->be == st->bdl_cnt) {
1183 bdle_desc = &bdl[st->be];
1187 hda_set_pib(sc, stream_ind, lpib);
1190 hda_set_field_by_offset(sc, off + HDAC_SDSTS,
1191 HDAC_SDSTS_BCIS, HDAC_SDSTS_BCIS);
1192 hda_update_intr(sc);
1199 hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib)
1201 uint32_t off = hda_get_offset_stream(stream_ind);
1203 hda_set_reg_by_offset(sc, off + HDAC_SDLPIB, pib);
1205 hda_set_reg_by_offset(sc, 0x2000 + off + HDAC_SDLPIB, pib);
1206 if (sc->dma_pib_vaddr)
1207 *(uint32_t *)((uint8_t *)sc->dma_pib_vaddr + stream_ind *
1208 HDA_DMA_PIB_ENTRY_LEN) = pib;
1211 static uint64_t hda_get_clock_ns(void)
1216 err = clock_gettime(CLOCK_MONOTONIC, &ts);
1219 return (ts.tv_sec * 1000000000LL + ts.tv_nsec);
1223 * PCI HDA function definitions
1226 pci_hda_init(struct pci_devinst *pi, nvlist_t *nvl)
1228 struct hda_softc *sc = NULL;
1232 pci_set_cfgdata16(pi, PCIR_VENDOR, INTEL_VENDORID);
1233 pci_set_cfgdata16(pi, PCIR_DEVICE, HDA_INTEL_82801G);
1235 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_MULTIMEDIA_HDA);
1236 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_MULTIMEDIA);
1238 /* select the Intel HDA mode */
1239 pci_set_cfgdata8(pi, PCIR_HDCTL, 0x01);
1241 /* allocate one BAR register for the Memory address offsets */
1242 pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, HDA_LAST_OFFSET);
1244 /* allocate an IRQ pin for our slot */
1245 pci_lintr_request(pi);
1258 pci_hda_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
1261 struct hda_softc *sc = pi->pi_arg;
1265 assert(baridx == 0);
1268 DPRINTF("offset: 0x%lx value: 0x%lx", offset, value);
1270 err = hda_write(sc, offset, size, value);
1275 pci_hda_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
1277 struct hda_softc *sc = pi->pi_arg;
1281 assert(baridx == 0);
1284 value = hda_read(sc, offset);
1286 DPRINTF("offset: 0x%lx value: 0x%lx", offset, value);