2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2016 Alex Teaca <iateaca@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/param.h>
42 #define PCIR_HDCTL 0x40
43 #define INTEL_VENDORID 0x8086
44 #define HDA_INTEL_82801G 0x27d8
46 #define HDA_IOSS_NO 0x08
47 #define HDA_OSS_NO 0x04
48 #define HDA_ISS_NO 0x04
49 #define HDA_CODEC_MAX 0x0f
50 #define HDA_LAST_OFFSET \
51 (0x2084 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
52 #define HDA_CORB_ENTRY_LEN 0x04
53 #define HDA_RIRB_ENTRY_LEN 0x08
54 #define HDA_BDL_ENTRY_LEN 0x10
55 #define HDA_DMA_PIB_ENTRY_LEN 0x08
56 #define HDA_STREAM_TAGS_CNT 0x10
57 #define HDA_STREAM_REGS_BASE 0x80
58 #define HDA_STREAM_REGS_LEN 0x20
60 #define HDA_DMA_ACCESS_LEN (sizeof(uint32_t))
61 #define HDA_BDL_MAX_LEN 0x0100
63 #define HDAC_SDSTS_FIFORDY (1 << 5)
65 #define HDA_RIRBSTS_IRQ_MASK (HDAC_RIRBSTS_RINTFL | HDAC_RIRBSTS_RIRBOIS)
66 #define HDA_STATESTS_IRQ_MASK ((1 << HDA_CODEC_MAX) - 1)
67 #define HDA_SDSTS_IRQ_MASK \
68 (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS)
76 typedef void (*hda_set_reg_handler)(struct hda_softc *sc, uint32_t offset,
86 struct hda_bdle_desc {
92 struct hda_codec_cmd_ctl {
101 struct hda_stream_desc {
106 /* bp is the no. of bytes transferred in the current bdle */
108 /* be is the no. of bdles transferred in the bdl */
112 struct hda_bdle_desc bdl[HDA_BDL_MAX_LEN];
116 struct pci_devinst *pci_dev;
117 uint32_t regs[HDA_LAST_OFFSET];
121 uint64_t wall_clock_start;
123 struct hda_codec_cmd_ctl corb;
124 struct hda_codec_cmd_ctl rirb;
127 struct hda_codec_inst *codecs[HDA_CODEC_MAX];
129 /* Base Address of the DMA Position Buffer */
132 struct hda_stream_desc streams[HDA_IOSS_NO];
133 /* 2 tables for output and input */
134 uint8_t stream_map[2][HDA_STREAM_TAGS_CNT];
138 * HDA module function declarations
140 static inline void hda_set_reg_by_offset(struct hda_softc *sc, uint32_t offset,
142 static inline uint32_t hda_get_reg_by_offset(struct hda_softc *sc,
144 static inline void hda_set_field_by_offset(struct hda_softc *sc,
145 uint32_t offset, uint32_t mask, uint32_t value);
147 static struct hda_softc *hda_init(nvlist_t *nvl);
148 static void hda_update_intr(struct hda_softc *sc);
149 static void hda_response_interrupt(struct hda_softc *sc);
150 static int hda_codec_constructor(struct hda_softc *sc,
151 struct hda_codec_class *codec, const char *play, const char *rec);
152 static struct hda_codec_class *hda_find_codec_class(const char *name);
154 static int hda_send_command(struct hda_softc *sc, uint32_t verb);
155 static int hda_notify_codecs(struct hda_softc *sc, uint8_t run,
156 uint8_t stream, uint8_t dir);
157 static void hda_reset(struct hda_softc *sc);
158 static void hda_reset_regs(struct hda_softc *sc);
159 static void hda_stream_reset(struct hda_softc *sc, uint8_t stream_ind);
160 static int hda_stream_start(struct hda_softc *sc, uint8_t stream_ind);
161 static int hda_stream_stop(struct hda_softc *sc, uint8_t stream_ind);
162 static uint32_t hda_read(struct hda_softc *sc, uint32_t offset);
163 static int hda_write(struct hda_softc *sc, uint32_t offset, uint8_t size,
166 static inline void hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl *p);
167 static int hda_corb_start(struct hda_softc *sc);
168 static int hda_corb_run(struct hda_softc *sc);
169 static int hda_rirb_start(struct hda_softc *sc);
171 static void *hda_dma_get_vaddr(struct hda_softc *sc, uint64_t dma_paddr,
173 static void hda_dma_st_dword(void *dma_vaddr, uint32_t data);
174 static uint32_t hda_dma_ld_dword(void *dma_vaddr);
176 static inline uint8_t hda_get_stream_by_offsets(uint32_t offset,
178 static inline uint32_t hda_get_offset_stream(uint8_t stream_ind);
180 static void hda_set_gctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
181 static void hda_set_statests(struct hda_softc *sc, uint32_t offset,
183 static void hda_set_corbwp(struct hda_softc *sc, uint32_t offset, uint32_t old);
184 static void hda_set_corbctl(struct hda_softc *sc, uint32_t offset,
186 static void hda_set_rirbctl(struct hda_softc *sc, uint32_t offset,
188 static void hda_set_rirbsts(struct hda_softc *sc, uint32_t offset,
190 static void hda_set_dpiblbase(struct hda_softc *sc, uint32_t offset,
192 static void hda_set_sdctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
193 static void hda_set_sdctl2(struct hda_softc *sc, uint32_t offset, uint32_t old);
194 static void hda_set_sdsts(struct hda_softc *sc, uint32_t offset, uint32_t old);
196 static int hda_signal_state_change(struct hda_codec_inst *hci);
197 static int hda_response(struct hda_codec_inst *hci, uint32_t response,
199 static int hda_transfer(struct hda_codec_inst *hci, uint8_t stream,
200 uint8_t dir, uint8_t *buf, size_t count);
202 static void hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib);
203 static uint64_t hda_get_clock_ns(void);
206 * PCI HDA function declarations
208 static int pci_hda_init(struct pci_devinst *pi, nvlist_t *nvl);
209 static void pci_hda_write(struct pci_devinst *pi, int baridx, uint64_t offset,
210 int size, uint64_t value);
211 static uint64_t pci_hda_read(struct pci_devinst *pi, int baridx,
212 uint64_t offset, int size);
217 static const hda_set_reg_handler hda_set_reg_table[] = {
218 [HDAC_GCTL] = hda_set_gctl,
219 [HDAC_STATESTS] = hda_set_statests,
220 [HDAC_CORBWP] = hda_set_corbwp,
221 [HDAC_CORBCTL] = hda_set_corbctl,
222 [HDAC_RIRBCTL] = hda_set_rirbctl,
223 [HDAC_RIRBSTS] = hda_set_rirbsts,
224 [HDAC_DPIBLBASE] = hda_set_dpiblbase,
226 #define HDAC_ISTREAM(n, iss, oss) \
227 [_HDAC_ISDCTL(n, iss, oss)] = hda_set_sdctl, \
228 [_HDAC_ISDCTL(n, iss, oss) + 2] = hda_set_sdctl2, \
229 [_HDAC_ISDSTS(n, iss, oss)] = hda_set_sdsts, \
231 #define HDAC_OSTREAM(n, iss, oss) \
232 [_HDAC_OSDCTL(n, iss, oss)] = hda_set_sdctl, \
233 [_HDAC_OSDCTL(n, iss, oss) + 2] = hda_set_sdctl2, \
234 [_HDAC_OSDSTS(n, iss, oss)] = hda_set_sdsts, \
236 HDAC_ISTREAM(0, HDA_ISS_NO, HDA_OSS_NO)
237 HDAC_ISTREAM(1, HDA_ISS_NO, HDA_OSS_NO)
238 HDAC_ISTREAM(2, HDA_ISS_NO, HDA_OSS_NO)
239 HDAC_ISTREAM(3, HDA_ISS_NO, HDA_OSS_NO)
241 HDAC_OSTREAM(0, HDA_ISS_NO, HDA_OSS_NO)
242 HDAC_OSTREAM(1, HDA_ISS_NO, HDA_OSS_NO)
243 HDAC_OSTREAM(2, HDA_ISS_NO, HDA_OSS_NO)
244 HDAC_OSTREAM(3, HDA_ISS_NO, HDA_OSS_NO)
247 static const uint16_t hda_corb_sizes[] = {
248 [HDAC_CORBSIZE_CORBSIZE_2] = 2,
249 [HDAC_CORBSIZE_CORBSIZE_16] = 16,
250 [HDAC_CORBSIZE_CORBSIZE_256] = 256,
251 [HDAC_CORBSIZE_CORBSIZE_MASK] = 0,
254 static const uint16_t hda_rirb_sizes[] = {
255 [HDAC_RIRBSIZE_RIRBSIZE_2] = 2,
256 [HDAC_RIRBSIZE_RIRBSIZE_16] = 16,
257 [HDAC_RIRBSIZE_RIRBSIZE_256] = 256,
258 [HDAC_RIRBSIZE_RIRBSIZE_MASK] = 0,
261 static const struct hda_ops hops = {
262 .signal = hda_signal_state_change,
263 .response = hda_response,
264 .transfer = hda_transfer,
267 static const struct pci_devemu pci_de_hda = {
269 .pe_init = pci_hda_init,
270 .pe_barwrite = pci_hda_write,
271 .pe_barread = pci_hda_read
273 PCI_EMUL_SET(pci_de_hda);
275 SET_DECLARE(hda_codec_class_set, struct hda_codec_class);
282 * HDA module function definitions
286 hda_set_reg_by_offset(struct hda_softc *sc, uint32_t offset, uint32_t value)
288 assert(offset < HDA_LAST_OFFSET);
289 sc->regs[offset] = value;
292 static inline uint32_t
293 hda_get_reg_by_offset(struct hda_softc *sc, uint32_t offset)
295 assert(offset < HDA_LAST_OFFSET);
296 return sc->regs[offset];
300 hda_set_field_by_offset(struct hda_softc *sc, uint32_t offset,
301 uint32_t mask, uint32_t value)
303 uint32_t reg_value = 0;
305 reg_value = hda_get_reg_by_offset(sc, offset);
308 reg_value |= (value & mask);
310 hda_set_reg_by_offset(sc, offset, reg_value);
313 static struct hda_softc *
314 hda_init(nvlist_t *nvl)
316 struct hda_softc *sc = NULL;
317 struct hda_codec_class *codec = NULL;
324 dbg = fopen(DEBUG_HDA_FILE, "w+");
327 sc = calloc(1, sizeof(*sc));
334 * TODO search all configured codecs
335 * For now we play with one single codec
337 codec = hda_find_codec_class("hda_codec");
339 value = get_config_value_node(nvl, "play");
343 play = strdup(value);
344 value = get_config_value_node(nvl, "rec");
349 DPRINTF("play: %s rec: %s", play, rec);
350 if (play != NULL || rec != NULL) {
351 err = hda_codec_constructor(sc, codec, play, rec);
362 hda_update_intr(struct hda_softc *sc)
364 struct pci_devinst *pi = sc->pci_dev;
365 uint32_t intctl = hda_get_reg_by_offset(sc, HDAC_INTCTL);
368 uint32_t rirbsts = 0;
370 uint32_t statests = 0;
374 /* update the CIS bits */
375 rirbsts = hda_get_reg_by_offset(sc, HDAC_RIRBSTS);
376 if (rirbsts & (HDAC_RIRBSTS_RINTFL | HDAC_RIRBSTS_RIRBOIS))
377 intsts |= HDAC_INTSTS_CIS;
379 wakeen = hda_get_reg_by_offset(sc, HDAC_WAKEEN);
380 statests = hda_get_reg_by_offset(sc, HDAC_STATESTS);
381 if (statests & wakeen)
382 intsts |= HDAC_INTSTS_CIS;
384 /* update the SIS bits */
385 for (i = 0; i < HDA_IOSS_NO; i++) {
386 off = hda_get_offset_stream(i);
387 sdsts = hda_get_reg_by_offset(sc, off + HDAC_SDSTS);
388 if (sdsts & HDAC_SDSTS_BCIS)
392 /* update the GIS bit */
394 intsts |= HDAC_INTSTS_GIS;
396 hda_set_reg_by_offset(sc, HDAC_INTSTS, intsts);
398 if ((intctl & HDAC_INTCTL_GIE) && ((intsts & \
399 ~HDAC_INTSTS_GIS) & intctl)) {
401 pci_lintr_assert(pi);
406 pci_lintr_deassert(pi);
413 hda_response_interrupt(struct hda_softc *sc)
415 uint8_t rirbctl = hda_get_reg_by_offset(sc, HDAC_RIRBCTL);
417 if ((rirbctl & HDAC_RIRBCTL_RINTCTL) && sc->rirb_cnt) {
419 hda_set_field_by_offset(sc, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL,
420 HDAC_RIRBSTS_RINTFL);
426 hda_codec_constructor(struct hda_softc *sc, struct hda_codec_class *codec,
427 const char *play, const char *rec)
429 struct hda_codec_inst *hci = NULL;
431 if (sc->codecs_no >= HDA_CODEC_MAX)
434 hci = calloc(1, sizeof(struct hda_codec_inst));
440 hci->cad = sc->codecs_no;
443 sc->codecs[sc->codecs_no++] = hci;
446 DPRINTF("This codec does not implement the init function");
450 return (codec->init(hci, play, rec));
453 static struct hda_codec_class *
454 hda_find_codec_class(const char *name)
456 struct hda_codec_class **pdpp = NULL, *pdp = NULL;
458 SET_FOREACH(pdpp, hda_codec_class_set) {
460 if (!strcmp(pdp->name, name)) {
469 hda_send_command(struct hda_softc *sc, uint32_t verb)
471 struct hda_codec_inst *hci = NULL;
472 struct hda_codec_class *codec = NULL;
473 uint8_t cad = (verb >> HDA_CMD_CAD_SHIFT) & 0x0f;
475 if (cad >= sc->codecs_no)
478 DPRINTF("cad: 0x%x verb: 0x%x", cad, verb);
480 hci = sc->codecs[cad];
486 if (!codec->command) {
487 DPRINTF("This codec does not implement the command function");
491 return (codec->command(hci, verb));
495 hda_notify_codecs(struct hda_softc *sc, uint8_t run, uint8_t stream,
498 struct hda_codec_inst *hci = NULL;
499 struct hda_codec_class *codec = NULL;
503 /* Notify each codec */
504 for (i = 0; i < sc->codecs_no; i++) {
512 err = codec->notify(hci, run, stream, dir);
518 return (i == sc->codecs_no ? (-1) : 0);
522 hda_reset(struct hda_softc *sc)
525 struct hda_codec_inst *hci = NULL;
526 struct hda_codec_class *codec = NULL;
530 /* Reset each codec */
531 for (i = 0; i < sc->codecs_no; i++) {
542 sc->wall_clock_start = hda_get_clock_ns();
546 hda_reset_regs(struct hda_softc *sc)
551 DPRINTF("Reset the HDA controller registers ...");
553 memset(sc->regs, 0, sizeof(sc->regs));
555 hda_set_reg_by_offset(sc, HDAC_GCAP,
557 (HDA_ISS_NO << HDAC_GCAP_ISS_SHIFT) |
558 (HDA_OSS_NO << HDAC_GCAP_OSS_SHIFT));
559 hda_set_reg_by_offset(sc, HDAC_VMAJ, 0x01);
560 hda_set_reg_by_offset(sc, HDAC_OUTPAY, 0x3c);
561 hda_set_reg_by_offset(sc, HDAC_INPAY, 0x1d);
562 hda_set_reg_by_offset(sc, HDAC_CORBSIZE,
563 HDAC_CORBSIZE_CORBSZCAP_256 | HDAC_CORBSIZE_CORBSIZE_256);
564 hda_set_reg_by_offset(sc, HDAC_RIRBSIZE,
565 HDAC_RIRBSIZE_RIRBSZCAP_256 | HDAC_RIRBSIZE_RIRBSIZE_256);
567 for (i = 0; i < HDA_IOSS_NO; i++) {
568 off = hda_get_offset_stream(i);
569 hda_set_reg_by_offset(sc, off + HDAC_SDFIFOS, HDA_FIFO_SIZE);
574 hda_stream_reset(struct hda_softc *sc, uint8_t stream_ind)
576 struct hda_stream_desc *st = &sc->streams[stream_ind];
577 uint32_t off = hda_get_offset_stream(stream_ind);
579 DPRINTF("Reset the HDA stream: 0x%x", stream_ind);
581 /* Reset the Stream Descriptor registers */
582 memset(sc->regs + HDA_STREAM_REGS_BASE + off, 0, HDA_STREAM_REGS_LEN);
584 /* Reset the Stream Descriptor */
585 memset(st, 0, sizeof(*st));
587 hda_set_field_by_offset(sc, off + HDAC_SDSTS,
588 HDAC_SDSTS_FIFORDY, HDAC_SDSTS_FIFORDY);
589 hda_set_field_by_offset(sc, off + HDAC_SDCTL0,
590 HDAC_SDCTL_SRST, HDAC_SDCTL_SRST);
594 hda_stream_start(struct hda_softc *sc, uint8_t stream_ind)
596 struct hda_stream_desc *st = &sc->streams[stream_ind];
597 struct hda_bdle_desc *bdle_desc = NULL;
598 struct hda_bdle *bdle = NULL;
600 uint32_t bdl_cnt = 0;
603 uint64_t bdl_paddr = 0;
604 void *bdl_vaddr = NULL;
605 uint32_t bdle_sz = 0;
606 uint64_t bdle_addrl = 0;
607 uint64_t bdle_addrh = 0;
608 uint64_t bdle_paddr = 0;
609 void *bdle_vaddr = NULL;
610 uint32_t off = hda_get_offset_stream(stream_ind);
617 lvi = hda_get_reg_by_offset(sc, off + HDAC_SDLVI);
618 bdpl = hda_get_reg_by_offset(sc, off + HDAC_SDBDPL);
619 bdpu = hda_get_reg_by_offset(sc, off + HDAC_SDBDPU);
622 assert(bdl_cnt <= HDA_BDL_MAX_LEN);
624 bdl_paddr = bdpl | (bdpu << 32);
625 bdl_vaddr = hda_dma_get_vaddr(sc, bdl_paddr,
626 HDA_BDL_ENTRY_LEN * bdl_cnt);
628 DPRINTF("Fail to get the guest virtual address");
632 DPRINTF("stream: 0x%x bdl_cnt: 0x%x bdl_paddr: 0x%lx",
633 stream_ind, bdl_cnt, bdl_paddr);
635 st->bdl_cnt = bdl_cnt;
637 bdle = (struct hda_bdle *)bdl_vaddr;
638 for (size_t i = 0; i < bdl_cnt; i++, bdle++) {
640 assert(!(bdle_sz % HDA_DMA_ACCESS_LEN));
642 bdle_addrl = bdle->addrl;
643 bdle_addrh = bdle->addrh;
645 bdle_paddr = bdle_addrl | (bdle_addrh << 32);
646 bdle_vaddr = hda_dma_get_vaddr(sc, bdle_paddr, bdle_sz);
648 DPRINTF("Fail to get the guest virtual address");
652 bdle_desc = &st->bdl[i];
653 bdle_desc->addr = bdle_vaddr;
654 bdle_desc->len = bdle_sz;
655 bdle_desc->ioc = bdle->ioc;
657 DPRINTF("bdle: 0x%zx bdle_sz: 0x%x", i, bdle_sz);
660 sdctl = hda_get_reg_by_offset(sc, off + HDAC_SDCTL0);
661 strm = (sdctl >> 20) & 0x0f;
662 dir = stream_ind >= HDA_ISS_NO;
664 DPRINTF("strm: 0x%x, dir: 0x%x", strm, dir);
666 sc->stream_map[dir][strm] = stream_ind;
672 hda_set_pib(sc, stream_ind, 0);
676 hda_notify_codecs(sc, 1, strm, dir);
682 hda_stream_stop(struct hda_softc *sc, uint8_t stream_ind)
684 struct hda_stream_desc *st = &sc->streams[stream_ind];
685 uint8_t strm = st->stream;
686 uint8_t dir = st->dir;
688 DPRINTF("stream: 0x%x, strm: 0x%x, dir: 0x%x", stream_ind, strm, dir);
692 hda_notify_codecs(sc, 0, strm, dir);
698 hda_read(struct hda_softc *sc, uint32_t offset)
700 if (offset == HDAC_WALCLK)
701 return (24 * (hda_get_clock_ns() - \
702 sc->wall_clock_start) / 1000);
704 return (hda_get_reg_by_offset(sc, offset));
708 hda_write(struct hda_softc *sc, uint32_t offset, uint8_t size, uint32_t value)
710 uint32_t old = hda_get_reg_by_offset(sc, offset);
711 uint32_t masks[] = {0x00000000, 0x000000ff, 0x0000ffff,
712 0x00ffffff, 0xffffffff};
713 hda_set_reg_handler set_reg_handler = NULL;
715 if (offset < nitems(hda_set_reg_table))
716 set_reg_handler = hda_set_reg_table[offset];
718 hda_set_field_by_offset(sc, offset, masks[size], value);
721 set_reg_handler(sc, offset, old);
728 hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl *p)
730 DPRINTF("%s size: %d", p->name, p->size);
731 DPRINTF("%s dma_vaddr: %p", p->name, p->dma_vaddr);
732 DPRINTF("%s wp: 0x%x", p->name, p->wp);
733 DPRINTF("%s rp: 0x%x", p->name, p->rp);
737 hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl *p __unused) {}
741 hda_corb_start(struct hda_softc *sc)
743 struct hda_codec_cmd_ctl *corb = &sc->corb;
744 uint8_t corbsize = 0;
745 uint64_t corblbase = 0;
746 uint64_t corbubase = 0;
747 uint64_t corbpaddr = 0;
751 corbsize = hda_get_reg_by_offset(sc, HDAC_CORBSIZE) & \
752 HDAC_CORBSIZE_CORBSIZE_MASK;
753 corb->size = hda_corb_sizes[corbsize];
756 DPRINTF("Invalid corb size");
760 corblbase = hda_get_reg_by_offset(sc, HDAC_CORBLBASE);
761 corbubase = hda_get_reg_by_offset(sc, HDAC_CORBUBASE);
763 corbpaddr = corblbase | (corbubase << 32);
764 DPRINTF("CORB dma_paddr: %p", (void *)corbpaddr);
766 corb->dma_vaddr = hda_dma_get_vaddr(sc, corbpaddr,
767 HDA_CORB_ENTRY_LEN * corb->size);
768 if (!corb->dma_vaddr) {
769 DPRINTF("Fail to get the guest virtual address");
773 corb->wp = hda_get_reg_by_offset(sc, HDAC_CORBWP);
774 corb->rp = hda_get_reg_by_offset(sc, HDAC_CORBRP);
778 hda_print_cmd_ctl_data(corb);
784 hda_corb_run(struct hda_softc *sc)
786 struct hda_codec_cmd_ctl *corb = &sc->corb;
790 corb->wp = hda_get_reg_by_offset(sc, HDAC_CORBWP);
792 while (corb->rp != corb->wp && corb->run) {
794 corb->rp %= corb->size;
796 verb = hda_dma_ld_dword((uint8_t *)corb->dma_vaddr +
797 HDA_CORB_ENTRY_LEN * corb->rp);
799 err = hda_send_command(sc, verb);
803 hda_set_reg_by_offset(sc, HDAC_CORBRP, corb->rp);
806 hda_response_interrupt(sc);
812 hda_rirb_start(struct hda_softc *sc)
814 struct hda_codec_cmd_ctl *rirb = &sc->rirb;
815 uint8_t rirbsize = 0;
816 uint64_t rirblbase = 0;
817 uint64_t rirbubase = 0;
818 uint64_t rirbpaddr = 0;
822 rirbsize = hda_get_reg_by_offset(sc, HDAC_RIRBSIZE) & \
823 HDAC_RIRBSIZE_RIRBSIZE_MASK;
824 rirb->size = hda_rirb_sizes[rirbsize];
827 DPRINTF("Invalid rirb size");
831 rirblbase = hda_get_reg_by_offset(sc, HDAC_RIRBLBASE);
832 rirbubase = hda_get_reg_by_offset(sc, HDAC_RIRBUBASE);
834 rirbpaddr = rirblbase | (rirbubase << 32);
835 DPRINTF("RIRB dma_paddr: %p", (void *)rirbpaddr);
837 rirb->dma_vaddr = hda_dma_get_vaddr(sc, rirbpaddr,
838 HDA_RIRB_ENTRY_LEN * rirb->size);
839 if (!rirb->dma_vaddr) {
840 DPRINTF("Fail to get the guest virtual address");
844 rirb->wp = hda_get_reg_by_offset(sc, HDAC_RIRBWP);
849 hda_print_cmd_ctl_data(rirb);
855 hda_dma_get_vaddr(struct hda_softc *sc, uint64_t dma_paddr, size_t len)
857 struct pci_devinst *pi = sc->pci_dev;
861 return (paddr_guest2host(pi->pi_vmctx, (uintptr_t)dma_paddr, len));
865 hda_dma_st_dword(void *dma_vaddr, uint32_t data)
867 *(uint32_t*)dma_vaddr = data;
871 hda_dma_ld_dword(void *dma_vaddr)
873 return (*(uint32_t*)dma_vaddr);
876 static inline uint8_t
877 hda_get_stream_by_offsets(uint32_t offset, uint8_t reg_offset)
879 uint8_t stream_ind = (offset - reg_offset) >> 5;
881 assert(stream_ind < HDA_IOSS_NO);
886 static inline uint32_t
887 hda_get_offset_stream(uint8_t stream_ind)
889 return (stream_ind << 5);
893 hda_set_gctl(struct hda_softc *sc, uint32_t offset, uint32_t old __unused)
895 uint32_t value = hda_get_reg_by_offset(sc, offset);
897 if (!(value & HDAC_GCTL_CRST)) {
903 hda_set_statests(struct hda_softc *sc, uint32_t offset, uint32_t old)
905 uint32_t value = hda_get_reg_by_offset(sc, offset);
907 hda_set_reg_by_offset(sc, offset, old);
909 /* clear the corresponding bits written by the software (guest) */
910 hda_set_field_by_offset(sc, offset, value & HDA_STATESTS_IRQ_MASK, 0);
916 hda_set_corbwp(struct hda_softc *sc, uint32_t offset __unused,
917 uint32_t old __unused)
923 hda_set_corbctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
925 uint32_t value = hda_get_reg_by_offset(sc, offset);
927 struct hda_codec_cmd_ctl *corb = NULL;
929 if (value & HDAC_CORBCTL_CORBRUN) {
930 if (!(old & HDAC_CORBCTL_CORBRUN)) {
931 err = hda_corb_start(sc);
936 memset(corb, 0, sizeof(*corb));
943 hda_set_rirbctl(struct hda_softc *sc, uint32_t offset, uint32_t old __unused)
945 uint32_t value = hda_get_reg_by_offset(sc, offset);
947 struct hda_codec_cmd_ctl *rirb = NULL;
949 if (value & HDAC_RIRBCTL_RIRBDMAEN) {
950 err = hda_rirb_start(sc);
954 memset(rirb, 0, sizeof(*rirb));
959 hda_set_rirbsts(struct hda_softc *sc, uint32_t offset, uint32_t old)
961 uint32_t value = hda_get_reg_by_offset(sc, offset);
963 hda_set_reg_by_offset(sc, offset, old);
965 /* clear the corresponding bits written by the software (guest) */
966 hda_set_field_by_offset(sc, offset, value & HDA_RIRBSTS_IRQ_MASK, 0);
972 hda_set_dpiblbase(struct hda_softc *sc, uint32_t offset, uint32_t old)
974 uint32_t value = hda_get_reg_by_offset(sc, offset);
975 uint64_t dpiblbase = 0;
976 uint64_t dpibubase = 0;
977 uint64_t dpibpaddr = 0;
979 if ((value & HDAC_DPLBASE_DPLBASE_DMAPBE) != (old & \
980 HDAC_DPLBASE_DPLBASE_DMAPBE)) {
981 if (value & HDAC_DPLBASE_DPLBASE_DMAPBE) {
982 dpiblbase = value & HDAC_DPLBASE_DPLBASE_MASK;
983 dpibubase = hda_get_reg_by_offset(sc, HDAC_DPIBUBASE);
985 dpibpaddr = dpiblbase | (dpibubase << 32);
986 DPRINTF("DMA Position In Buffer dma_paddr: %p",
989 sc->dma_pib_vaddr = hda_dma_get_vaddr(sc, dpibpaddr,
990 HDA_DMA_PIB_ENTRY_LEN * HDA_IOSS_NO);
991 if (!sc->dma_pib_vaddr) {
992 DPRINTF("Fail to get the guest \
997 DPRINTF("DMA Position In Buffer Reset");
998 sc->dma_pib_vaddr = NULL;
1004 hda_set_sdctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
1006 uint8_t stream_ind = hda_get_stream_by_offsets(offset, HDAC_SDCTL0);
1007 uint32_t value = hda_get_reg_by_offset(sc, offset);
1010 DPRINTF("stream_ind: 0x%x old: 0x%x value: 0x%x",
1011 stream_ind, old, value);
1013 if (value & HDAC_SDCTL_SRST) {
1014 hda_stream_reset(sc, stream_ind);
1017 if ((value & HDAC_SDCTL_RUN) != (old & HDAC_SDCTL_RUN)) {
1018 if (value & HDAC_SDCTL_RUN) {
1019 err = hda_stream_start(sc, stream_ind);
1022 err = hda_stream_stop(sc, stream_ind);
1029 hda_set_sdctl2(struct hda_softc *sc, uint32_t offset, uint32_t old __unused)
1031 uint32_t value = hda_get_reg_by_offset(sc, offset);
1033 hda_set_field_by_offset(sc, offset - 2, 0x00ff0000, value << 16);
1037 hda_set_sdsts(struct hda_softc *sc, uint32_t offset, uint32_t old)
1039 uint32_t value = hda_get_reg_by_offset(sc, offset);
1041 hda_set_reg_by_offset(sc, offset, old);
1043 /* clear the corresponding bits written by the software (guest) */
1044 hda_set_field_by_offset(sc, offset, value & HDA_SDSTS_IRQ_MASK, 0);
1046 hda_update_intr(sc);
1050 hda_signal_state_change(struct hda_codec_inst *hci)
1052 struct hda_softc *sc = NULL;
1053 uint32_t sdiwake = 0;
1058 DPRINTF("cad: 0x%x", hci->cad);
1061 sdiwake = 1 << hci->cad;
1063 hda_set_field_by_offset(sc, HDAC_STATESTS, sdiwake, sdiwake);
1064 hda_update_intr(sc);
1070 hda_response(struct hda_codec_inst *hci, uint32_t response, uint8_t unsol)
1072 struct hda_softc *sc = NULL;
1073 struct hda_codec_cmd_ctl *rirb = NULL;
1074 uint32_t response_ex = 0;
1075 uint8_t rintcnt = 0;
1078 assert(hci->cad <= HDA_CODEC_MAX);
1080 response_ex = hci->cad | unsol;
1089 rirb->wp %= rirb->size;
1091 hda_dma_st_dword((uint8_t *)rirb->dma_vaddr +
1092 HDA_RIRB_ENTRY_LEN * rirb->wp, response);
1093 hda_dma_st_dword((uint8_t *)rirb->dma_vaddr +
1094 HDA_RIRB_ENTRY_LEN * rirb->wp + 0x04, response_ex);
1096 hda_set_reg_by_offset(sc, HDAC_RIRBWP, rirb->wp);
1101 rintcnt = hda_get_reg_by_offset(sc, HDAC_RINTCNT);
1102 if (sc->rirb_cnt == rintcnt)
1103 hda_response_interrupt(sc);
1109 hda_transfer(struct hda_codec_inst *hci, uint8_t stream, uint8_t dir,
1110 uint8_t *buf, size_t count)
1112 struct hda_softc *sc = NULL;
1113 struct hda_stream_desc *st = NULL;
1114 struct hda_bdle_desc *bdl = NULL;
1115 struct hda_bdle_desc *bdle_desc = NULL;
1116 uint8_t stream_ind = 0;
1125 assert(!(count % HDA_DMA_ACCESS_LEN));
1128 DPRINTF("Invalid stream");
1134 assert(stream < HDA_STREAM_TAGS_CNT);
1135 stream_ind = sc->stream_map[dir][stream];
1138 assert(stream_ind < HDA_ISS_NO);
1140 assert(stream_ind >= HDA_ISS_NO && stream_ind < HDA_IOSS_NO);
1142 st = &sc->streams[stream_ind];
1144 DPRINTF("Stream 0x%x stopped", stream);
1148 assert(st->stream == stream);
1150 off = hda_get_offset_stream(stream_ind);
1152 lpib = hda_get_reg_by_offset(sc, off + HDAC_SDLPIB);
1156 assert(st->be < st->bdl_cnt);
1157 assert(st->bp < bdl[st->be].len);
1161 bdle_desc = &bdl[st->be];
1164 *(uint32_t *)buf = hda_dma_ld_dword(
1165 (uint8_t *)bdle_desc->addr + st->bp);
1167 hda_dma_st_dword((uint8_t *)bdle_desc->addr +
1168 st->bp, *(uint32_t *)buf);
1170 buf += HDA_DMA_ACCESS_LEN;
1171 st->bp += HDA_DMA_ACCESS_LEN;
1172 lpib += HDA_DMA_ACCESS_LEN;
1173 left -= HDA_DMA_ACCESS_LEN;
1175 if (st->bp == bdle_desc->len) {
1180 if (st->be == st->bdl_cnt) {
1184 bdle_desc = &bdl[st->be];
1188 hda_set_pib(sc, stream_ind, lpib);
1191 hda_set_field_by_offset(sc, off + HDAC_SDSTS,
1192 HDAC_SDSTS_BCIS, HDAC_SDSTS_BCIS);
1193 hda_update_intr(sc);
1200 hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib)
1202 uint32_t off = hda_get_offset_stream(stream_ind);
1204 hda_set_reg_by_offset(sc, off + HDAC_SDLPIB, pib);
1206 hda_set_reg_by_offset(sc, 0x2000 + off + HDAC_SDLPIB, pib);
1207 if (sc->dma_pib_vaddr)
1208 *(uint32_t *)((uint8_t *)sc->dma_pib_vaddr + stream_ind *
1209 HDA_DMA_PIB_ENTRY_LEN) = pib;
1212 static uint64_t hda_get_clock_ns(void)
1217 err = clock_gettime(CLOCK_MONOTONIC, &ts);
1220 return (ts.tv_sec * 1000000000LL + ts.tv_nsec);
1224 * PCI HDA function definitions
1227 pci_hda_init(struct pci_devinst *pi, nvlist_t *nvl)
1229 struct hda_softc *sc = NULL;
1233 pci_set_cfgdata16(pi, PCIR_VENDOR, INTEL_VENDORID);
1234 pci_set_cfgdata16(pi, PCIR_DEVICE, HDA_INTEL_82801G);
1236 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_MULTIMEDIA_HDA);
1237 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_MULTIMEDIA);
1239 /* select the Intel HDA mode */
1240 pci_set_cfgdata8(pi, PCIR_HDCTL, 0x01);
1242 /* allocate one BAR register for the Memory address offsets */
1243 pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, HDA_LAST_OFFSET);
1245 /* allocate an IRQ pin for our slot */
1246 pci_lintr_request(pi);
1259 pci_hda_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
1262 struct hda_softc *sc = pi->pi_arg;
1266 assert(baridx == 0);
1269 DPRINTF("offset: 0x%lx value: 0x%lx", offset, value);
1271 err = hda_write(sc, offset, size, value);
1276 pci_hda_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
1278 struct hda_softc *sc = pi->pi_arg;
1282 assert(baridx == 0);
1285 value = hda_read(sc, offset);
1287 DPRINTF("offset: 0x%lx value: 0x%lx", offset, value);