2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2014 Hudson River Trading LLC
5 * Written by: John H. Baldwin <jhb@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <machine/vmm.h>
51 * Implement an 8 pin PCI interrupt router compatible with the router
52 * present on Intel's ICH10 chip.
55 /* Fields in each PIRQ register. */
59 /* Only IRQs 3-7, 9-12, and 14-15 are permitted. */
60 #define PERMITTED_IRQS 0xdef8
61 #define IRQ_PERMITTED(irq) (((1U << (irq)) & PERMITTED_IRQS) != 0)
63 /* IRQ count to disable an IRQ. */
64 #define IRQ_DISABLED 0xff
73 static u_char irq_counts[16];
74 static int pirq_cold = 1;
77 * Returns true if this pin is enabled with a valid IRQ. Setting the
78 * register to a reserved IRQ causes interrupts to not be asserted as
79 * if the pin was disabled.
82 pirq_valid_irq(int reg)
87 return (IRQ_PERMITTED(reg & PIRQ_IRQ));
94 assert(pin > 0 && pin <= nitems(pirqs));
95 return (pirqs[pin - 1].reg);
99 pirq_write(struct vmctx *ctx, int pin, uint8_t val)
103 assert(pin > 0 && pin <= nitems(pirqs));
104 pirq = &pirqs[pin - 1];
105 pthread_mutex_lock(&pirq->lock);
106 if (pirq->reg != (val & (PIRQ_DIS | PIRQ_IRQ))) {
107 if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))
108 vm_isa_deassert_irq(ctx, pirq->reg & PIRQ_IRQ, -1);
109 pirq->reg = val & (PIRQ_DIS | PIRQ_IRQ);
110 if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))
111 vm_isa_assert_irq(ctx, pirq->reg & PIRQ_IRQ, -1);
113 pthread_mutex_unlock(&pirq->lock);
117 pci_irq_reserve(int irq)
120 assert(irq >= 0 && irq < nitems(irq_counts));
122 assert(irq_counts[irq] == 0 || irq_counts[irq] == IRQ_DISABLED);
123 irq_counts[irq] = IRQ_DISABLED;
130 assert(irq >= 0 && irq < nitems(irq_counts));
132 assert(irq_counts[irq] != IRQ_DISABLED);
137 pci_irq_init(struct vmctx *ctx)
141 for (i = 0; i < nitems(pirqs); i++) {
142 pirqs[i].reg = PIRQ_DIS;
143 pirqs[i].use_count = 0;
144 pirqs[i].active_count = 0;
145 pthread_mutex_init(&pirqs[i].lock, NULL);
147 for (i = 0; i < nitems(irq_counts); i++) {
148 if (IRQ_PERMITTED(i))
151 irq_counts[i] = IRQ_DISABLED;
156 pci_irq_assert(struct pci_devinst *pi)
160 if (pi->pi_lintr.pirq_pin > 0) {
161 assert(pi->pi_lintr.pirq_pin <= nitems(pirqs));
162 pirq = &pirqs[pi->pi_lintr.pirq_pin - 1];
163 pthread_mutex_lock(&pirq->lock);
164 pirq->active_count++;
165 if (pirq->active_count == 1 && pirq_valid_irq(pirq->reg)) {
166 vm_isa_assert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ,
167 pi->pi_lintr.ioapic_irq);
168 pthread_mutex_unlock(&pirq->lock);
171 pthread_mutex_unlock(&pirq->lock);
173 vm_ioapic_assert_irq(pi->pi_vmctx, pi->pi_lintr.ioapic_irq);
177 pci_irq_deassert(struct pci_devinst *pi)
181 if (pi->pi_lintr.pirq_pin > 0) {
182 assert(pi->pi_lintr.pirq_pin <= nitems(pirqs));
183 pirq = &pirqs[pi->pi_lintr.pirq_pin - 1];
184 pthread_mutex_lock(&pirq->lock);
185 pirq->active_count--;
186 if (pirq->active_count == 0 && pirq_valid_irq(pirq->reg)) {
187 vm_isa_deassert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ,
188 pi->pi_lintr.ioapic_irq);
189 pthread_mutex_unlock(&pirq->lock);
192 pthread_mutex_unlock(&pirq->lock);
194 vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr.ioapic_irq);
198 pirq_alloc_pin(struct pci_devinst *pi)
200 struct vmctx *ctx = pi->pi_vmctx;
201 int best_count, best_irq, best_pin, irq, pin;
206 /* For external bootrom use fixed mapping. */
207 best_pin = (4 + pi->pi_slot + pi->pi_lintr.pin) % 8;
209 /* Find the least-used PIRQ pin. */
211 best_count = pirqs[0].use_count;
212 for (pin = 1; pin < nitems(pirqs); pin++) {
213 if (pirqs[pin].use_count < best_count) {
215 best_count = pirqs[pin].use_count;
219 pirqs[best_pin].use_count++;
221 /* Second, route this pin to an IRQ. */
222 if (pirqs[best_pin].reg == PIRQ_DIS) {
225 for (irq = 0; irq < nitems(irq_counts); irq++) {
226 if (irq_counts[irq] == IRQ_DISABLED)
228 if (best_irq == -1 || irq_counts[irq] < best_count) {
230 best_count = irq_counts[irq];
233 assert(best_irq >= 0);
234 irq_counts[best_irq]++;
235 pirqs[best_pin].reg = best_irq;
236 vm_isa_set_irq_trigger(ctx, best_irq, LEVEL_TRIGGER);
239 return (best_pin + 1);
245 assert(pin > 0 && pin <= nitems(pirqs));
246 return (pirqs[pin - 1].reg & PIRQ_IRQ);
249 /* XXX: Generate $PIR table. */
258 for (irq = 0; irq < nitems(irq_counts); irq++) {
259 if (!IRQ_PERMITTED(irq))
262 asprintf(&irq_prs, "%d", irq);
265 asprintf(&irq_prs, "%s,%d", old, irq);
271 * A helper method to validate a link register's value. This
272 * duplicates pirq_valid_irq().
275 dsdt_line("Method (PIRV, 1, NotSerialized)");
277 dsdt_line(" If (And (Arg0, 0x%02X))", PIRQ_DIS);
279 dsdt_line(" Return (0x00)");
281 dsdt_line(" And (Arg0, 0x%02X, Local0)", PIRQ_IRQ);
282 dsdt_line(" If (LLess (Local0, 0x03))");
284 dsdt_line(" Return (0x00)");
286 dsdt_line(" If (LEqual (Local0, 0x08))");
288 dsdt_line(" Return (0x00)");
290 dsdt_line(" If (LEqual (Local0, 0x0D))");
292 dsdt_line(" Return (0x00)");
294 dsdt_line(" Return (0x01)");
297 for (pin = 0; pin < nitems(pirqs); pin++) {
299 dsdt_line("Device (LNK%c)", 'A' + pin);
301 dsdt_line(" Name (_HID, EisaId (\"PNP0C0F\"))");
302 dsdt_line(" Name (_UID, 0x%02X)", pin + 1);
303 dsdt_line(" Method (_STA, 0, NotSerialized)");
305 dsdt_line(" If (PIRV (PIR%c))", 'A' + pin);
307 dsdt_line(" Return (0x0B)");
311 dsdt_line(" Return (0x09)");
314 dsdt_line(" Name (_PRS, ResourceTemplate ()");
316 dsdt_line(" IRQ (Level, ActiveLow, Shared, )");
317 dsdt_line(" {%s}", irq_prs);
319 dsdt_line(" Name (CB%02X, ResourceTemplate ()", pin + 1);
321 dsdt_line(" IRQ (Level, ActiveLow, Shared, )");
324 dsdt_line(" CreateWordField (CB%02X, 0x01, CIR%c)",
326 dsdt_line(" Method (_CRS, 0, NotSerialized)");
328 dsdt_line(" And (PIR%c, 0x%02X, Local0)", 'A' + pin,
329 PIRQ_DIS | PIRQ_IRQ);
330 dsdt_line(" If (PIRV (Local0))");
332 dsdt_line(" ShiftLeft (0x01, Local0, CIR%c)", 'A' + pin);
336 dsdt_line(" Store (0x00, CIR%c)", 'A' + pin);
338 dsdt_line(" Return (CB%02X)", pin + 1);
340 dsdt_line(" Method (_DIS, 0, NotSerialized)");
342 dsdt_line(" Store (0x80, PIR%c)", 'A' + pin);
344 dsdt_line(" Method (_SRS, 1, NotSerialized)");
346 dsdt_line(" CreateWordField (Arg0, 0x01, SIR%c)", 'A' + pin);
347 dsdt_line(" FindSetRightBit (SIR%c, Local0)", 'A' + pin);
348 dsdt_line(" Store (Decrement (Local0), PIR%c)", 'A' + pin);