2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #include <machine/vmm.h>
50 #include "uart_emul.h"
55 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
56 SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
58 #define ELCR_PORT 0x4d0
59 SYSRES_IO(ELCR_PORT, 2);
61 #define IO_TIMER1_PORT 0x40
63 #define NMISC_PORT 0x61
64 SYSRES_IO(NMISC_PORT, 1);
66 static struct pci_devinst *lpc_bridge;
68 static const char *romfile;
70 #define LPC_UART_NUM 2
71 static struct lpc_uart_softc {
72 struct uart_softc *uart_softc;
77 } lpc_uart_softc[LPC_UART_NUM];
79 static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" };
82 * LPC device configuration is in the following form:
83 * <lpc_device_name>[,<options>]
84 * For e.g. "com1,stdio" or "bootrom,/var/romfile"
87 lpc_device_parse(const char *opts)
90 char *str, *cpy, *lpcdev;
93 str = cpy = strdup(opts);
94 lpcdev = strsep(&str, ",");
96 if (strcasecmp(lpcdev, "bootrom") == 0) {
101 for (unit = 0; unit < LPC_UART_NUM; unit++) {
102 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
103 lpc_uart_softc[unit].opts = str;
125 lpc_uart_intr_assert(void *arg)
127 struct lpc_uart_softc *sc = arg;
129 assert(sc->irq >= 0);
131 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq);
135 lpc_uart_intr_deassert(void *arg)
138 * The COM devices on the LPC bus generate edge triggered interrupts,
139 * so nothing more to do here.
144 lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
145 uint32_t *eax, void *arg)
148 struct lpc_uart_softc *sc = arg;
150 offset = port - sc->iobase;
155 *eax = uart_read(sc->uart_softc, offset);
157 uart_write(sc->uart_softc, offset, *eax);
161 *eax = uart_read(sc->uart_softc, offset);
162 *eax |= uart_read(sc->uart_softc, offset + 1) << 8;
164 uart_write(sc->uart_softc, offset, *eax);
165 uart_write(sc->uart_softc, offset + 1, *eax >> 8);
176 lpc_init(struct vmctx *ctx)
178 struct lpc_uart_softc *sc;
179 struct inout_port iop;
183 if (romfile != NULL) {
184 error = bootrom_init(ctx, romfile);
190 for (unit = 0; unit < LPC_UART_NUM; unit++) {
191 sc = &lpc_uart_softc[unit];
192 name = lpc_uart_names[unit];
194 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
195 fprintf(stderr, "Unable to allocate resources for "
196 "LPC device %s\n", name);
199 pci_irq_reserve(sc->irq);
201 sc->uart_softc = uart_init(lpc_uart_intr_assert,
202 lpc_uart_intr_deassert, sc);
204 if (uart_set_backend(sc->uart_softc, sc->opts) != 0) {
205 fprintf(stderr, "Unable to initialize backend '%s' "
206 "for LPC device %s\n", sc->opts, name);
210 bzero(&iop, sizeof(struct inout_port));
212 iop.port = sc->iobase;
213 iop.size = UART_IO_BAR_SIZE;
214 iop.flags = IOPORT_F_INOUT;
215 iop.handler = lpc_uart_io_handler;
218 error = register_inout(&iop);
227 pci_lpc_write_dsdt(struct pci_devinst *pi)
229 struct lpc_dsdt **ldpp, *ldp;
232 dsdt_line("Device (ISA)");
234 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
235 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");
236 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)");
238 dsdt_line(" Offset (0x60),");
239 dsdt_line(" PIRA, 8,");
240 dsdt_line(" PIRB, 8,");
241 dsdt_line(" PIRC, 8,");
242 dsdt_line(" PIRD, 8,");
243 dsdt_line(" Offset (0x68),");
244 dsdt_line(" PIRE, 8,");
245 dsdt_line(" PIRF, 8,");
246 dsdt_line(" PIRG, 8,");
247 dsdt_line(" PIRH, 8");
252 SET_FOREACH(ldpp, lpc_dsdt_set) {
258 dsdt_line("Device (PIC)");
260 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))");
261 dsdt_line(" Name (_CRS, ResourceTemplate ()");
264 dsdt_fixed_ioport(IO_ICU1, 2);
265 dsdt_fixed_ioport(IO_ICU2, 2);
272 dsdt_line("Device (TIMR)");
274 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))");
275 dsdt_line(" Name (_CRS, ResourceTemplate ()");
278 dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
289 pci_lpc_sysres_dsdt(void)
291 struct lpc_sysres **lspp, *lsp;
294 dsdt_line("Device (SIO)");
296 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))");
297 dsdt_line(" Name (_CRS, ResourceTemplate ()");
301 SET_FOREACH(lspp, lpc_sysres_set) {
305 dsdt_fixed_ioport(lsp->base, lsp->length);
308 dsdt_fixed_mem32(lsp->base, lsp->length);
317 LPC_DSDT(pci_lpc_sysres_dsdt);
320 pci_lpc_uart_dsdt(void)
322 struct lpc_uart_softc *sc;
325 for (unit = 0; unit < LPC_UART_NUM; unit++) {
326 sc = &lpc_uart_softc[unit];
330 dsdt_line("Device (%s)", lpc_uart_names[unit]);
332 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))");
333 dsdt_line(" Name (_UID, %d)", unit + 1);
334 dsdt_line(" Name (_CRS, ResourceTemplate ()");
337 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE);
338 dsdt_fixed_irq(sc->irq);
344 LPC_DSDT(pci_lpc_uart_dsdt);
347 pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
348 int coff, int bytes, uint32_t val)
354 if (coff >= 0x60 && coff <= 0x63)
355 pirq_pin = coff - 0x60 + 1;
356 if (coff >= 0x68 && coff <= 0x6b)
357 pirq_pin = coff - 0x68 + 5;
359 pirq_write(ctx, pirq_pin, val);
360 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
368 pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
369 int baridx, uint64_t offset, int size, uint64_t value)
374 pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
375 int baridx, uint64_t offset, int size)
380 #define LPC_DEV 0x7000
381 #define LPC_VENDOR 0x8086
384 pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
388 * Do not allow more than one LPC bridge to be configured.
390 if (lpc_bridge != NULL) {
391 fprintf(stderr, "Only one LPC bridge is allowed.\n");
396 * Enforce that the LPC can only be configured on bus 0. This
397 * simplifies the ACPI DSDT because it can provide a decode for
398 * all legacy i/o ports behind bus 0.
400 if (pi->pi_bus != 0) {
401 fprintf(stderr, "LPC bridge can be present only on bus 0.\n");
405 if (lpc_init(ctx) != 0)
408 /* initialize config space */
409 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
410 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
411 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
412 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
420 lpc_pirq_name(int pin)
424 if (lpc_bridge == NULL)
426 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1);
431 lpc_pirq_routed(void)
435 if (lpc_bridge == NULL)
438 for (pin = 0; pin < 4; pin++)
439 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));
440 for (pin = 0; pin < 4; pin++)
441 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));
444 struct pci_devemu pci_de_lpc = {
446 .pe_init = pci_lpc_init,
447 .pe_write_dsdt = pci_lpc_write_dsdt,
448 .pe_cfgwrite = pci_lpc_cfgwrite,
449 .pe_barwrite = pci_lpc_write,
450 .pe_barread = pci_lpc_read
452 PCI_EMUL_SET(pci_de_lpc);