2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #include <machine/vmm.h>
37 #include <machine/vmm_snapshot.h>
53 #include "pctestdev.h"
54 #include "uart_emul.h"
59 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
60 SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
62 #define ELCR_PORT 0x4d0
63 SYSRES_IO(ELCR_PORT, 2);
65 #define IO_TIMER1_PORT 0x40
67 #define NMISC_PORT 0x61
68 SYSRES_IO(NMISC_PORT, 1);
70 static struct pci_devinst *lpc_bridge;
72 #define LPC_UART_NUM 4
73 static struct lpc_uart_softc {
74 struct uart_softc *uart_softc;
78 } lpc_uart_softc[LPC_UART_NUM];
80 static const char *lpc_uart_names[LPC_UART_NUM] = {
81 "com1", "com2", "com3", "com4"
84 static const char *lpc_uart_acpi_names[LPC_UART_NUM] = {
85 "COM1", "COM2", "COM3", "COM4"
89 * LPC device configuration is in the following form:
90 * <lpc_device_name>[,<options>]
91 * For e.g. "com1,stdio" or "bootrom,/var/romfile"
94 lpc_device_parse(const char *opts)
97 char *str, *cpy, *lpcdev, *node_name;
100 str = cpy = strdup(opts);
101 lpcdev = strsep(&str, ",");
102 if (lpcdev != NULL) {
103 if (strcasecmp(lpcdev, "bootrom") == 0) {
104 set_config_value("lpc.bootrom", str);
108 for (unit = 0; unit < LPC_UART_NUM; unit++) {
109 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
110 asprintf(&node_name, "lpc.%s.path",
111 lpc_uart_names[unit]);
112 set_config_value(node_name, str);
118 if (strcasecmp(lpcdev, pctestdev_getname()) == 0) {
119 asprintf(&node_name, "lpc.%s", pctestdev_getname());
120 set_config_bool(node_name, true);
134 lpc_print_supported_devices()
139 for (i = 0; i < LPC_UART_NUM; i++)
140 printf("%s\n", lpc_uart_names[i]);
141 printf("%s\n", pctestdev_getname());
148 return (get_config_value("lpc.bootrom"));
152 lpc_uart_intr_assert(void *arg)
154 struct lpc_uart_softc *sc = arg;
156 assert(sc->irq >= 0);
158 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq);
162 lpc_uart_intr_deassert(void *arg)
165 * The COM devices on the LPC bus generate edge triggered interrupts,
166 * so nothing more to do here.
171 lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
172 uint32_t *eax, void *arg)
175 struct lpc_uart_softc *sc = arg;
177 offset = port - sc->iobase;
182 *eax = uart_read(sc->uart_softc, offset);
184 uart_write(sc->uart_softc, offset, *eax);
188 *eax = uart_read(sc->uart_softc, offset);
189 *eax |= uart_read(sc->uart_softc, offset + 1) << 8;
191 uart_write(sc->uart_softc, offset, *eax);
192 uart_write(sc->uart_softc, offset + 1, *eax >> 8);
203 lpc_init(struct vmctx *ctx)
205 struct lpc_uart_softc *sc;
206 struct inout_port iop;
207 const char *backend, *name, *romfile;
211 romfile = get_config_value("lpc.bootrom");
212 if (romfile != NULL) {
213 error = bootrom_loadrom(ctx, romfile);
219 for (unit = 0; unit < LPC_UART_NUM; unit++) {
220 sc = &lpc_uart_softc[unit];
221 name = lpc_uart_names[unit];
223 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
224 EPRINTLN("Unable to allocate resources for "
225 "LPC device %s", name);
228 pci_irq_reserve(sc->irq);
230 sc->uart_softc = uart_init(lpc_uart_intr_assert,
231 lpc_uart_intr_deassert, sc);
233 asprintf(&node_name, "lpc.%s.path", name);
234 backend = get_config_value(node_name);
236 if (uart_set_backend(sc->uart_softc, backend) != 0) {
237 EPRINTLN("Unable to initialize backend '%s' "
238 "for LPC device %s", backend, name);
242 bzero(&iop, sizeof(struct inout_port));
244 iop.port = sc->iobase;
245 iop.size = UART_IO_BAR_SIZE;
246 iop.flags = IOPORT_F_INOUT;
247 iop.handler = lpc_uart_io_handler;
250 error = register_inout(&iop);
256 asprintf(&node_name, "lpc.%s", pctestdev_getname());
257 if (get_config_bool_default(node_name, false)) {
258 error = pctestdev_init(ctx);
268 pci_lpc_write_dsdt(struct pci_devinst *pi)
270 struct lpc_dsdt **ldpp, *ldp;
273 dsdt_line("Device (ISA)");
275 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
276 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");
277 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)");
279 dsdt_line(" Offset (0x60),");
280 dsdt_line(" PIRA, 8,");
281 dsdt_line(" PIRB, 8,");
282 dsdt_line(" PIRC, 8,");
283 dsdt_line(" PIRD, 8,");
284 dsdt_line(" Offset (0x68),");
285 dsdt_line(" PIRE, 8,");
286 dsdt_line(" PIRF, 8,");
287 dsdt_line(" PIRG, 8,");
288 dsdt_line(" PIRH, 8");
293 SET_FOREACH(ldpp, lpc_dsdt_set) {
299 dsdt_line("Device (PIC)");
301 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))");
302 dsdt_line(" Name (_CRS, ResourceTemplate ()");
305 dsdt_fixed_ioport(IO_ICU1, 2);
306 dsdt_fixed_ioport(IO_ICU2, 2);
313 dsdt_line("Device (TIMR)");
315 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))");
316 dsdt_line(" Name (_CRS, ResourceTemplate ()");
319 dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
330 pci_lpc_sysres_dsdt(void)
332 struct lpc_sysres **lspp, *lsp;
335 dsdt_line("Device (SIO)");
337 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))");
338 dsdt_line(" Name (_CRS, ResourceTemplate ()");
342 SET_FOREACH(lspp, lpc_sysres_set) {
346 dsdt_fixed_ioport(lsp->base, lsp->length);
349 dsdt_fixed_mem32(lsp->base, lsp->length);
358 LPC_DSDT(pci_lpc_sysres_dsdt);
361 pci_lpc_uart_dsdt(void)
363 struct lpc_uart_softc *sc;
366 for (unit = 0; unit < LPC_UART_NUM; unit++) {
367 sc = &lpc_uart_softc[unit];
371 dsdt_line("Device (%s)", lpc_uart_acpi_names[unit]);
373 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))");
374 dsdt_line(" Name (_UID, %d)", unit + 1);
375 dsdt_line(" Name (_CRS, ResourceTemplate ()");
378 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE);
379 dsdt_fixed_irq(sc->irq);
385 LPC_DSDT(pci_lpc_uart_dsdt);
388 pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
389 int coff, int bytes, uint32_t val)
395 if (coff >= 0x60 && coff <= 0x63)
396 pirq_pin = coff - 0x60 + 1;
397 if (coff >= 0x68 && coff <= 0x6b)
398 pirq_pin = coff - 0x68 + 5;
400 pirq_write(ctx, pirq_pin, val);
401 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
409 pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
410 int baridx, uint64_t offset, int size, uint64_t value)
415 pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
416 int baridx, uint64_t offset, int size)
421 #define LPC_DEV 0x7000
422 #define LPC_VENDOR 0x8086
425 pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
429 * Do not allow more than one LPC bridge to be configured.
431 if (lpc_bridge != NULL) {
432 EPRINTLN("Only one LPC bridge is allowed.");
437 * Enforce that the LPC can only be configured on bus 0. This
438 * simplifies the ACPI DSDT because it can provide a decode for
439 * all legacy i/o ports behind bus 0.
441 if (pi->pi_bus != 0) {
442 EPRINTLN("LPC bridge can be present only on bus 0.");
446 if (lpc_init(ctx) != 0)
449 /* initialize config space */
450 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
451 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
452 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
453 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
461 lpc_pirq_name(int pin)
465 if (lpc_bridge == NULL)
467 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1);
472 lpc_pirq_routed(void)
476 if (lpc_bridge == NULL)
479 for (pin = 0; pin < 4; pin++)
480 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));
481 for (pin = 0; pin < 4; pin++)
482 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));
485 #ifdef BHYVE_SNAPSHOT
487 pci_lpc_snapshot(struct vm_snapshot_meta *meta)
490 struct uart_softc *sc;
492 for (unit = 0; unit < LPC_UART_NUM; unit++) {
493 sc = lpc_uart_softc[unit].uart_softc;
495 ret = uart_snapshot(sc, meta);
505 struct pci_devemu pci_de_lpc = {
507 .pe_init = pci_lpc_init,
508 .pe_write_dsdt = pci_lpc_write_dsdt,
509 .pe_cfgwrite = pci_lpc_cfgwrite,
510 .pe_barwrite = pci_lpc_write,
511 .pe_barread = pci_lpc_read,
512 #ifdef BHYVE_SNAPSHOT
513 .pe_snapshot = pci_lpc_snapshot,
516 PCI_EMUL_SET(pci_de_lpc);