2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #include <machine/vmm.h>
51 #include "uart_emul.h"
56 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
57 SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
59 #define ELCR_PORT 0x4d0
60 SYSRES_IO(ELCR_PORT, 2);
62 #define IO_TIMER1_PORT 0x40
64 #define NMISC_PORT 0x61
65 SYSRES_IO(NMISC_PORT, 1);
67 static struct pci_devinst *lpc_bridge;
69 static const char *romfile;
71 #define LPC_UART_NUM 2
72 static struct lpc_uart_softc {
73 struct uart_softc *uart_softc;
78 } lpc_uart_softc[LPC_UART_NUM];
80 static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" };
83 * LPC device configuration is in the following form:
84 * <lpc_device_name>[,<options>]
85 * For e.g. "com1,stdio" or "bootrom,/var/romfile"
88 lpc_device_parse(const char *opts)
91 char *str, *cpy, *lpcdev;
94 str = cpy = strdup(opts);
95 lpcdev = strsep(&str, ",");
97 if (strcasecmp(lpcdev, "bootrom") == 0) {
102 for (unit = 0; unit < LPC_UART_NUM; unit++) {
103 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
104 lpc_uart_softc[unit].opts = str;
119 lpc_print_supported_devices()
124 for (i = 0; i < LPC_UART_NUM; i++)
125 printf("%s\n", lpc_uart_names[i]);
136 lpc_uart_intr_assert(void *arg)
138 struct lpc_uart_softc *sc = arg;
140 assert(sc->irq >= 0);
142 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq);
146 lpc_uart_intr_deassert(void *arg)
149 * The COM devices on the LPC bus generate edge triggered interrupts,
150 * so nothing more to do here.
155 lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
156 uint32_t *eax, void *arg)
159 struct lpc_uart_softc *sc = arg;
161 offset = port - sc->iobase;
166 *eax = uart_read(sc->uart_softc, offset);
168 uart_write(sc->uart_softc, offset, *eax);
172 *eax = uart_read(sc->uart_softc, offset);
173 *eax |= uart_read(sc->uart_softc, offset + 1) << 8;
175 uart_write(sc->uart_softc, offset, *eax);
176 uart_write(sc->uart_softc, offset + 1, *eax >> 8);
187 lpc_init(struct vmctx *ctx)
189 struct lpc_uart_softc *sc;
190 struct inout_port iop;
194 if (romfile != NULL) {
195 error = bootrom_init(ctx, romfile);
201 for (unit = 0; unit < LPC_UART_NUM; unit++) {
202 sc = &lpc_uart_softc[unit];
203 name = lpc_uart_names[unit];
205 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
206 EPRINTLN("Unable to allocate resources for "
207 "LPC device %s", name);
210 pci_irq_reserve(sc->irq);
212 sc->uart_softc = uart_init(lpc_uart_intr_assert,
213 lpc_uart_intr_deassert, sc);
215 if (uart_set_backend(sc->uart_softc, sc->opts) != 0) {
216 EPRINTLN("Unable to initialize backend '%s' "
217 "for LPC device %s", sc->opts, name);
221 bzero(&iop, sizeof(struct inout_port));
223 iop.port = sc->iobase;
224 iop.size = UART_IO_BAR_SIZE;
225 iop.flags = IOPORT_F_INOUT;
226 iop.handler = lpc_uart_io_handler;
229 error = register_inout(&iop);
238 pci_lpc_write_dsdt(struct pci_devinst *pi)
240 struct lpc_dsdt **ldpp, *ldp;
243 dsdt_line("Device (ISA)");
245 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
246 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");
247 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)");
249 dsdt_line(" Offset (0x60),");
250 dsdt_line(" PIRA, 8,");
251 dsdt_line(" PIRB, 8,");
252 dsdt_line(" PIRC, 8,");
253 dsdt_line(" PIRD, 8,");
254 dsdt_line(" Offset (0x68),");
255 dsdt_line(" PIRE, 8,");
256 dsdt_line(" PIRF, 8,");
257 dsdt_line(" PIRG, 8,");
258 dsdt_line(" PIRH, 8");
263 SET_FOREACH(ldpp, lpc_dsdt_set) {
269 dsdt_line("Device (PIC)");
271 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))");
272 dsdt_line(" Name (_CRS, ResourceTemplate ()");
275 dsdt_fixed_ioport(IO_ICU1, 2);
276 dsdt_fixed_ioport(IO_ICU2, 2);
283 dsdt_line("Device (TIMR)");
285 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))");
286 dsdt_line(" Name (_CRS, ResourceTemplate ()");
289 dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
300 pci_lpc_sysres_dsdt(void)
302 struct lpc_sysres **lspp, *lsp;
305 dsdt_line("Device (SIO)");
307 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))");
308 dsdt_line(" Name (_CRS, ResourceTemplate ()");
312 SET_FOREACH(lspp, lpc_sysres_set) {
316 dsdt_fixed_ioport(lsp->base, lsp->length);
319 dsdt_fixed_mem32(lsp->base, lsp->length);
328 LPC_DSDT(pci_lpc_sysres_dsdt);
331 pci_lpc_uart_dsdt(void)
333 struct lpc_uart_softc *sc;
336 for (unit = 0; unit < LPC_UART_NUM; unit++) {
337 sc = &lpc_uart_softc[unit];
341 dsdt_line("Device (%s)", lpc_uart_names[unit]);
343 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))");
344 dsdt_line(" Name (_UID, %d)", unit + 1);
345 dsdt_line(" Name (_CRS, ResourceTemplate ()");
348 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE);
349 dsdt_fixed_irq(sc->irq);
355 LPC_DSDT(pci_lpc_uart_dsdt);
358 pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
359 int coff, int bytes, uint32_t val)
365 if (coff >= 0x60 && coff <= 0x63)
366 pirq_pin = coff - 0x60 + 1;
367 if (coff >= 0x68 && coff <= 0x6b)
368 pirq_pin = coff - 0x68 + 5;
370 pirq_write(ctx, pirq_pin, val);
371 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
379 pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
380 int baridx, uint64_t offset, int size, uint64_t value)
385 pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
386 int baridx, uint64_t offset, int size)
391 #define LPC_DEV 0x7000
392 #define LPC_VENDOR 0x8086
395 pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
399 * Do not allow more than one LPC bridge to be configured.
401 if (lpc_bridge != NULL) {
402 EPRINTLN("Only one LPC bridge is allowed.");
407 * Enforce that the LPC can only be configured on bus 0. This
408 * simplifies the ACPI DSDT because it can provide a decode for
409 * all legacy i/o ports behind bus 0.
411 if (pi->pi_bus != 0) {
412 EPRINTLN("LPC bridge can be present only on bus 0.");
416 if (lpc_init(ctx) != 0)
419 /* initialize config space */
420 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
421 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
422 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
423 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
431 lpc_pirq_name(int pin)
435 if (lpc_bridge == NULL)
437 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1);
442 lpc_pirq_routed(void)
446 if (lpc_bridge == NULL)
449 for (pin = 0; pin < 4; pin++)
450 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));
451 for (pin = 0; pin < 4; pin++)
452 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));
455 struct pci_devemu pci_de_lpc = {
457 .pe_init = pci_lpc_init,
458 .pe_write_dsdt = pci_lpc_write_dsdt,
459 .pe_cfgwrite = pci_lpc_cfgwrite,
460 .pe_barwrite = pci_lpc_write,
461 .pe_barread = pci_lpc_read
463 PCI_EMUL_SET(pci_de_lpc);