2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #include <machine/vmm.h>
37 #include <machine/vmm_snapshot.h>
54 #include "pctestdev.h"
55 #include "uart_emul.h"
60 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
61 SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
63 #define ELCR_PORT 0x4d0
64 SYSRES_IO(ELCR_PORT, 2);
66 #define IO_TIMER1_PORT 0x40
68 #define NMISC_PORT 0x61
69 SYSRES_IO(NMISC_PORT, 1);
71 static struct pci_devinst *lpc_bridge;
73 #define LPC_UART_NUM 4
74 static struct lpc_uart_softc {
75 struct uart_softc *uart_softc;
79 } lpc_uart_softc[LPC_UART_NUM];
81 static const char *lpc_uart_names[LPC_UART_NUM] = {
82 "com1", "com2", "com3", "com4"
85 static const char *lpc_uart_acpi_names[LPC_UART_NUM] = {
86 "COM1", "COM2", "COM3", "COM4"
90 * LPC device configuration is in the following form:
91 * <lpc_device_name>[,<options>]
92 * For e.g. "com1,stdio" or "bootrom,/var/romfile"
95 lpc_device_parse(const char *opts)
98 char *str, *cpy, *lpcdev, *node_name;
99 const char *romfile, *varfile;
102 str = cpy = strdup(opts);
103 lpcdev = strsep(&str, ",");
104 if (lpcdev != NULL) {
105 if (strcasecmp(lpcdev, "bootrom") == 0) {
106 romfile = strsep(&str, ",");
107 if (romfile == NULL) {
108 errx(4, "invalid bootrom option \"%s\"", opts);
110 set_config_value("lpc.bootrom", romfile);
112 varfile = strsep(&str, ",");
113 if (varfile != NULL) {
114 set_config_value("lpc.bootvars", varfile);
120 for (unit = 0; unit < LPC_UART_NUM; unit++) {
121 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
122 asprintf(&node_name, "lpc.%s.path",
123 lpc_uart_names[unit]);
124 set_config_value(node_name, str);
130 if (strcasecmp(lpcdev, pctestdev_getname()) == 0) {
131 asprintf(&node_name, "lpc.%s", pctestdev_getname());
132 set_config_bool(node_name, true);
146 lpc_print_supported_devices(void)
151 for (i = 0; i < LPC_UART_NUM; i++)
152 printf("%s\n", lpc_uart_names[i]);
153 printf("%s\n", pctestdev_getname());
160 return (get_config_value("lpc.bootrom"));
164 lpc_uart_intr_assert(void *arg)
166 struct lpc_uart_softc *sc = arg;
168 assert(sc->irq >= 0);
170 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq);
174 lpc_uart_intr_deassert(void *arg)
177 * The COM devices on the LPC bus generate edge triggered interrupts,
178 * so nothing more to do here.
183 lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
184 uint32_t *eax, void *arg)
187 struct lpc_uart_softc *sc = arg;
189 offset = port - sc->iobase;
194 *eax = uart_read(sc->uart_softc, offset);
196 uart_write(sc->uart_softc, offset, *eax);
200 *eax = uart_read(sc->uart_softc, offset);
201 *eax |= uart_read(sc->uart_softc, offset + 1) << 8;
203 uart_write(sc->uart_softc, offset, *eax);
204 uart_write(sc->uart_softc, offset + 1, *eax >> 8);
215 lpc_init(struct vmctx *ctx)
217 struct lpc_uart_softc *sc;
218 struct inout_port iop;
219 const char *backend, *name;
224 nvl = find_config_node("lpc");
225 if (nvl != NULL && nvlist_exists(nvl, "bootrom")) {
226 error = bootrom_loadrom(ctx, nvl);
232 for (unit = 0; unit < LPC_UART_NUM; unit++) {
233 sc = &lpc_uart_softc[unit];
234 name = lpc_uart_names[unit];
236 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
237 EPRINTLN("Unable to allocate resources for "
238 "LPC device %s", name);
241 pci_irq_reserve(sc->irq);
243 sc->uart_softc = uart_init(lpc_uart_intr_assert,
244 lpc_uart_intr_deassert, sc);
246 asprintf(&node_name, "lpc.%s.path", name);
247 backend = get_config_value(node_name);
249 if (uart_set_backend(sc->uart_softc, backend) != 0) {
250 EPRINTLN("Unable to initialize backend '%s' "
251 "for LPC device %s", backend, name);
255 bzero(&iop, sizeof(struct inout_port));
257 iop.port = sc->iobase;
258 iop.size = UART_IO_BAR_SIZE;
259 iop.flags = IOPORT_F_INOUT;
260 iop.handler = lpc_uart_io_handler;
263 error = register_inout(&iop);
269 asprintf(&node_name, "lpc.%s", pctestdev_getname());
270 if (get_config_bool_default(node_name, false)) {
271 error = pctestdev_init(ctx);
281 pci_lpc_write_dsdt(struct pci_devinst *pi)
283 struct lpc_dsdt **ldpp, *ldp;
286 dsdt_line("Device (ISA)");
288 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
289 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");
290 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)");
292 dsdt_line(" Offset (0x60),");
293 dsdt_line(" PIRA, 8,");
294 dsdt_line(" PIRB, 8,");
295 dsdt_line(" PIRC, 8,");
296 dsdt_line(" PIRD, 8,");
297 dsdt_line(" Offset (0x68),");
298 dsdt_line(" PIRE, 8,");
299 dsdt_line(" PIRF, 8,");
300 dsdt_line(" PIRG, 8,");
301 dsdt_line(" PIRH, 8");
306 SET_FOREACH(ldpp, lpc_dsdt_set) {
312 dsdt_line("Device (PIC)");
314 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))");
315 dsdt_line(" Name (_CRS, ResourceTemplate ()");
318 dsdt_fixed_ioport(IO_ICU1, 2);
319 dsdt_fixed_ioport(IO_ICU2, 2);
326 dsdt_line("Device (TIMR)");
328 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))");
329 dsdt_line(" Name (_CRS, ResourceTemplate ()");
332 dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
343 pci_lpc_sysres_dsdt(void)
345 struct lpc_sysres **lspp, *lsp;
348 dsdt_line("Device (SIO)");
350 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))");
351 dsdt_line(" Name (_CRS, ResourceTemplate ()");
355 SET_FOREACH(lspp, lpc_sysres_set) {
359 dsdt_fixed_ioport(lsp->base, lsp->length);
362 dsdt_fixed_mem32(lsp->base, lsp->length);
371 LPC_DSDT(pci_lpc_sysres_dsdt);
374 pci_lpc_uart_dsdt(void)
376 struct lpc_uart_softc *sc;
379 for (unit = 0; unit < LPC_UART_NUM; unit++) {
380 sc = &lpc_uart_softc[unit];
384 dsdt_line("Device (%s)", lpc_uart_acpi_names[unit]);
386 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))");
387 dsdt_line(" Name (_UID, %d)", unit + 1);
388 dsdt_line(" Name (_CRS, ResourceTemplate ()");
391 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE);
392 dsdt_fixed_irq(sc->irq);
398 LPC_DSDT(pci_lpc_uart_dsdt);
401 pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
402 int coff, int bytes, uint32_t val)
408 if (coff >= 0x60 && coff <= 0x63)
409 pirq_pin = coff - 0x60 + 1;
410 if (coff >= 0x68 && coff <= 0x6b)
411 pirq_pin = coff - 0x68 + 5;
413 pirq_write(ctx, pirq_pin, val);
414 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
422 pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
423 int baridx, uint64_t offset, int size, uint64_t value)
428 pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
429 int baridx, uint64_t offset, int size)
434 #define LPC_DEV 0x7000
435 #define LPC_VENDOR 0x8086
438 pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
442 * Do not allow more than one LPC bridge to be configured.
444 if (lpc_bridge != NULL) {
445 EPRINTLN("Only one LPC bridge is allowed.");
450 * Enforce that the LPC can only be configured on bus 0. This
451 * simplifies the ACPI DSDT because it can provide a decode for
452 * all legacy i/o ports behind bus 0.
454 if (pi->pi_bus != 0) {
455 EPRINTLN("LPC bridge can be present only on bus 0.");
459 if (lpc_init(ctx) != 0)
462 /* initialize config space */
463 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
464 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
465 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
466 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
474 lpc_pirq_name(int pin)
478 if (lpc_bridge == NULL)
480 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1);
485 lpc_pirq_routed(void)
489 if (lpc_bridge == NULL)
492 for (pin = 0; pin < 4; pin++)
493 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));
494 for (pin = 0; pin < 4; pin++)
495 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));
498 #ifdef BHYVE_SNAPSHOT
500 pci_lpc_snapshot(struct vm_snapshot_meta *meta)
503 struct uart_softc *sc;
505 for (unit = 0; unit < LPC_UART_NUM; unit++) {
506 sc = lpc_uart_softc[unit].uart_softc;
508 ret = uart_snapshot(sc, meta);
518 static const struct pci_devemu pci_de_lpc = {
520 .pe_init = pci_lpc_init,
521 .pe_write_dsdt = pci_lpc_write_dsdt,
522 .pe_cfgwrite = pci_lpc_cfgwrite,
523 .pe_barwrite = pci_lpc_write,
524 .pe_barread = pci_lpc_read,
525 #ifdef BHYVE_SNAPSHOT
526 .pe_snapshot = pci_lpc_snapshot,
529 PCI_EMUL_SET(pci_de_lpc);