2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #ifndef WITHOUT_CAPSICUM
36 #include <sys/capsicum.h>
38 #include <sys/types.h>
40 #include <sys/pciio.h>
41 #include <sys/ioctl.h>
44 #include <dev/io/iodev.h>
45 #include <dev/pci/pcireg.h>
49 #include <machine/iodev.h>
50 #include <machine/vm.h>
52 #ifndef WITHOUT_CAPSICUM
53 #include <capsicum_helpers.h>
65 #include <machine/vmm.h>
70 #include "pci_passthru.h"
73 #define _PATH_DEVPCI "/dev/pci"
76 #define LEGACY_SUPPORT 1
78 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
79 #define MSIX_CAPLEN 12
81 static int pcifd = -1;
83 struct passthru_softc {
84 struct pci_devinst *psc_pi;
85 /* ROM is handled like a BAR */
86 struct pcibar psc_bar[PCI_BARMAX_WITH_ROM + 1];
95 struct pcisel psc_sel;
99 msi_caplen(int msgctrl)
103 len = 10; /* minimum length of msi capability */
105 if (msgctrl & PCIM_MSICTRL_64BIT)
110 * Ignore the 'mask' and 'pending' bits in the MSI capability.
111 * We'll let the guest manipulate them directly.
113 if (msgctrl & PCIM_MSICTRL_VECTOR)
123 pcifd = open(_PATH_DEVPCI, O_RDWR, 0);
125 warn("failed to open %s", _PATH_DEVPCI);
129 #ifndef WITHOUT_CAPSICUM
130 cap_rights_t pcifd_rights;
131 cap_rights_init(&pcifd_rights, CAP_IOCTL, CAP_READ, CAP_WRITE);
132 if (caph_rights_limit(pcifd, &pcifd_rights) == -1)
133 errx(EX_OSERR, "Unable to apply rights for sandbox");
135 const cap_ioctl_t pcifd_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR,
136 PCIOCBARIO, PCIOCBARMMAP, PCIOCGETCONF };
137 if (caph_ioctls_limit(pcifd, pcifd_ioctls, nitems(pcifd_ioctls)) == -1)
138 errx(EX_OSERR, "Unable to apply rights for sandbox");
145 read_config(const struct pcisel *sel, long reg, int width)
149 if (pcifd < 0 && pcifd_init()) {
153 bzero(&pi, sizeof(pi));
158 if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
159 return (0); /* XXX */
165 write_config(const struct pcisel *sel, long reg, int width, uint32_t data)
169 if (pcifd < 0 && pcifd_init()) {
173 bzero(&pi, sizeof(pi));
179 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
182 #ifdef LEGACY_SUPPORT
184 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
187 struct msicap msicap;
190 pci_populate_msicap(&msicap, msgnum, nextptr);
194 * Copy the msi capability structure in the last 16 bytes of the
195 * config space. This is wrong because it could shadow something
196 * useful to the device.
198 capoff = 256 - roundup(sizeof(msicap), 4);
199 capdata = (u_char *)&msicap;
200 for (i = 0; i < sizeof(msicap); i++)
201 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
205 #endif /* LEGACY_SUPPORT */
208 cfginitmsi(struct passthru_softc *sc)
210 int i, ptr, capptr, cap, sts, caplen, table_size;
213 struct pci_devinst *pi;
214 struct msixcap msixcap;
215 uint32_t *msixcap_ptr;
221 * Parse the capabilities and cache the location of the MSI
222 * and MSI-X capabilities.
224 sts = read_config(&sel, PCIR_STATUS, 2);
225 if (sts & PCIM_STATUS_CAPPRESENT) {
226 ptr = read_config(&sel, PCIR_CAP_PTR, 1);
227 while (ptr != 0 && ptr != 0xff) {
228 cap = read_config(&sel, ptr + PCICAP_ID, 1);
229 if (cap == PCIY_MSI) {
231 * Copy the MSI capability into the config
232 * space of the emulated pci device
234 sc->psc_msi.capoff = ptr;
235 sc->psc_msi.msgctrl = read_config(&sel,
237 sc->psc_msi.emulated = 0;
238 caplen = msi_caplen(sc->psc_msi.msgctrl);
241 u32 = read_config(&sel, capptr, 4);
242 pci_set_cfgdata32(pi, capptr, u32);
246 } else if (cap == PCIY_MSIX) {
248 * Copy the MSI-X capability
250 sc->psc_msix.capoff = ptr;
252 msixcap_ptr = (uint32_t*) &msixcap;
255 u32 = read_config(&sel, capptr, 4);
257 pci_set_cfgdata32(pi, capptr, u32);
263 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1);
267 if (sc->psc_msix.capoff != 0) {
268 pi->pi_msix.pba_bar =
269 msixcap.pba_info & PCIM_MSIX_BIR_MASK;
270 pi->pi_msix.pba_offset =
271 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
272 pi->pi_msix.table_bar =
273 msixcap.table_info & PCIM_MSIX_BIR_MASK;
274 pi->pi_msix.table_offset =
275 msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
276 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
277 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
279 /* Allocate the emulated MSI-X table array */
280 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
281 pi->pi_msix.table = calloc(1, table_size);
283 /* Mask all table entries */
284 for (i = 0; i < pi->pi_msix.table_count; i++) {
285 pi->pi_msix.table[i].vector_control |=
286 PCIM_MSIX_VCTRL_MASK;
290 #ifdef LEGACY_SUPPORT
292 * If the passthrough device does not support MSI then craft a
293 * MSI capability for it. We link the new MSI capability at the
294 * head of the list of capabilities.
296 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
298 origptr = read_config(&sel, PCIR_CAP_PTR, 1);
299 msiptr = passthru_add_msicap(pi, 1, origptr);
300 sc->psc_msi.capoff = msiptr;
301 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
302 sc->psc_msi.emulated = 1;
303 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
307 /* Make sure one of the capabilities is present */
308 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
315 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
317 struct pci_devinst *pi;
318 struct msix_table_entry *entry;
325 uint32_t table_offset;
326 int index, table_count;
330 table_offset = pi->pi_msix.table_offset;
331 table_count = pi->pi_msix.table_count;
332 if (offset < table_offset ||
333 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
336 src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
340 src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
344 src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
348 src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
357 offset -= table_offset;
358 index = offset / MSIX_TABLE_ENTRY_SIZE;
359 assert(index < table_count);
361 entry = &pi->pi_msix.table[index];
362 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
366 src8 = (uint8_t *)((uint8_t *)entry + entry_offset);
370 src16 = (uint16_t *)((uint8_t *)entry + entry_offset);
374 src32 = (uint32_t *)((uint8_t *)entry + entry_offset);
378 src64 = (uint64_t *)((uint8_t *)entry + entry_offset);
389 msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc,
390 uint64_t offset, int size, uint64_t data)
392 struct pci_devinst *pi;
393 struct msix_table_entry *entry;
399 uint32_t table_offset, vector_control;
400 int index, table_count;
404 table_offset = pi->pi_msix.table_offset;
405 table_count = pi->pi_msix.table_count;
406 if (offset < table_offset ||
407 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
410 dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
414 dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
418 dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
422 dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
429 offset -= table_offset;
430 index = offset / MSIX_TABLE_ENTRY_SIZE;
431 assert(index < table_count);
433 entry = &pi->pi_msix.table[index];
434 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
436 /* Only 4 byte naturally-aligned writes are supported */
438 assert(entry_offset % 4 == 0);
440 vector_control = entry->vector_control;
441 dest32 = (uint32_t *)((void *)entry + entry_offset);
443 /* If MSI-X hasn't been enabled, do nothing */
444 if (pi->pi_msix.enabled) {
445 /* If the entry is masked, don't set it up */
446 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
447 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
448 (void)vm_setup_pptdev_msix(ctx, vcpu,
449 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
450 sc->psc_sel.pc_func, index, entry->addr,
451 entry->msg_data, entry->vector_control);
457 init_msix_table(struct vmctx *ctx, struct passthru_softc *sc)
459 struct pci_devinst *pi = sc->psc_pi;
460 struct pci_bar_mmap pbm;
462 uint32_t table_size, table_offset;
464 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
466 b = sc->psc_sel.pc_bus;
467 s = sc->psc_sel.pc_dev;
468 f = sc->psc_sel.pc_func;
471 * Map the region of the BAR containing the MSI-X table. This is
472 * necessary for two reasons:
473 * 1. The PBA may reside in the first or last page containing the MSI-X
475 * 2. While PCI devices are not supposed to use the page(s) containing
476 * the MSI-X table for other purposes, some do in practice.
478 memset(&pbm, 0, sizeof(pbm));
479 pbm.pbm_sel = sc->psc_sel;
480 pbm.pbm_flags = PCIIO_BAR_MMAP_RW;
481 pbm.pbm_reg = PCIR_BAR(pi->pi_msix.table_bar);
482 pbm.pbm_memattr = VM_MEMATTR_DEVICE;
484 if (ioctl(pcifd, PCIOCBARMMAP, &pbm) != 0) {
485 warn("Failed to map MSI-X table BAR on %d/%d/%d", b, s, f);
488 assert(pbm.pbm_bar_off == 0);
489 pi->pi_msix.mapped_addr = (uint8_t *)(uintptr_t)pbm.pbm_map_base;
490 pi->pi_msix.mapped_size = pbm.pbm_map_length;
492 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
494 table_size = pi->pi_msix.table_offset - table_offset;
495 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
496 table_size = roundup2(table_size, 4096);
499 * Unmap any pages not containing the table, we do not need to emulate
500 * accesses to them. Avoid releasing address space to help ensure that
501 * a buggy out-of-bounds access causes a crash.
503 if (table_offset != 0)
504 if (mprotect(pi->pi_msix.mapped_addr, table_offset,
506 warn("Failed to unmap MSI-X table BAR region");
507 if (table_offset + table_size != pi->pi_msix.mapped_size)
509 pi->pi_msix.mapped_addr + table_offset + table_size,
510 pi->pi_msix.mapped_size - (table_offset + table_size),
512 warn("Failed to unmap MSI-X table BAR region");
518 cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
521 struct pci_devinst *pi;
522 struct pci_bar_io bar;
523 enum pcibar_type bartype;
529 * Initialize BAR registers
531 for (i = 0; i <= PCI_BARMAX; i++) {
532 bzero(&bar, sizeof(bar));
533 bar.pbi_sel = sc->psc_sel;
534 bar.pbi_reg = PCIR_BAR(i);
536 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
539 if (PCI_BAR_IO(bar.pbi_base)) {
541 base = bar.pbi_base & PCIM_BAR_IO_BASE;
543 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
544 case PCIM_BAR_MEM_64:
545 bartype = PCIBAR_MEM64;
548 bartype = PCIBAR_MEM32;
551 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
553 size = bar.pbi_length;
555 if (bartype != PCIBAR_IO) {
556 if (((base | size) & PAGE_MASK) != 0) {
557 warnx("passthru device %d/%d/%d BAR %d: "
558 "base %#lx or size %#lx not page aligned\n",
559 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
560 sc->psc_sel.pc_func, i, base, size);
565 /* Cache information about the "real" BAR */
566 sc->psc_bar[i].type = bartype;
567 sc->psc_bar[i].size = size;
568 sc->psc_bar[i].addr = base;
569 sc->psc_bar[i].lobits = 0;
571 /* Allocate the BAR in the guest I/O or MMIO space */
572 error = pci_emul_alloc_bar(pi, i, bartype, size);
576 /* Use same lobits as physical bar */
577 uint8_t lobits = read_config(&sc->psc_sel, PCIR_BAR(i), 0x01);
578 if (bartype == PCIBAR_MEM32 || bartype == PCIBAR_MEM64) {
579 lobits &= ~PCIM_BAR_MEM_BASE;
581 lobits &= ~PCIM_BAR_IO_BASE;
583 sc->psc_bar[i].lobits = lobits;
584 pi->pi_bar[i].lobits = lobits;
587 * 64-bit BAR takes up two slots so skip the next one.
589 if (bartype == PCIBAR_MEM64) {
591 assert(i <= PCI_BARMAX);
592 sc->psc_bar[i].type = PCIBAR_MEMHI64;
599 cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
602 struct passthru_softc *sc;
607 bzero(&sc->psc_sel, sizeof(struct pcisel));
608 sc->psc_sel.pc_bus = bus;
609 sc->psc_sel.pc_dev = slot;
610 sc->psc_sel.pc_func = func;
612 if (cfginitmsi(sc) != 0) {
613 warnx("failed to initialize MSI for PCI %d/%d/%d",
618 if (cfginitbar(ctx, sc) != 0) {
619 warnx("failed to initialize BARs for PCI %d/%d/%d",
624 write_config(&sc->psc_sel, PCIR_COMMAND, 2,
625 pci_get_cfgdata16(pi, PCIR_COMMAND));
628 * We need to do this after PCIR_COMMAND got possibly updated, e.g.,
629 * a BAR was enabled, as otherwise the PCIOCBARMMAP might fail on us.
631 if (pci_msix_table_bar(pi) >= 0) {
632 error = init_msix_table(ctx, sc);
635 "failed to initialize MSI-X table for PCI %d/%d/%d: %d",
636 bus, slot, func, error);
641 error = 0; /* success */
647 passthru_legacy_config(nvlist_t *nvl, const char *opts)
657 cp = strchr(opts, ',');
659 if (strncmp(opts, "ppt", strlen("ppt")) == 0) {
660 tofree = strndup(opts, cp - opts);
661 set_config_value_node(nvl, "pptdev", tofree);
663 } else if (sscanf(opts, "pci0:%d:%d:%d", &bus, &slot, &func) == 3 ||
664 sscanf(opts, "pci%d:%d:%d", &bus, &slot, &func) == 3 ||
665 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) == 3) {
666 snprintf(value, sizeof(value), "%d", bus);
667 set_config_value_node(nvl, "bus", value);
668 snprintf(value, sizeof(value), "%d", slot);
669 set_config_value_node(nvl, "slot", value);
670 snprintf(value, sizeof(value), "%d", func);
671 set_config_value_node(nvl, "func", value);
673 EPRINTLN("passthru: invalid options \"%s\"", opts);
681 return (pci_parse_legacy_config(nvl, cp + 1));
685 passthru_init_rom(struct vmctx *const ctx, struct passthru_softc *const sc,
686 const char *const romfile)
688 if (romfile == NULL) {
692 const int fd = open(romfile, O_RDONLY);
694 warnx("%s: can't open romfile \"%s\"", __func__, romfile);
699 if (fstat(fd, &sbuf) < 0) {
700 warnx("%s: can't fstat romfile \"%s\"", __func__, romfile);
704 const uint64_t rom_size = sbuf.st_size;
706 void *const rom_data = mmap(NULL, rom_size, PROT_READ, MAP_SHARED, fd,
708 if (rom_data == MAP_FAILED) {
709 warnx("%s: unable to mmap romfile \"%s\" (%d)", __func__,
716 int error = pci_emul_alloc_rom(sc->psc_pi, rom_size, &rom_addr);
718 warnx("%s: failed to alloc rom segment", __func__);
719 munmap(rom_data, rom_size);
723 memcpy(rom_addr, rom_data, rom_size);
725 sc->psc_bar[PCI_ROM_IDX].type = PCIBAR_ROM;
726 sc->psc_bar[PCI_ROM_IDX].addr = (uint64_t)rom_addr;
727 sc->psc_bar[PCI_ROM_IDX].size = rom_size;
729 munmap(rom_data, rom_size);
736 passthru_lookup_pptdev(const char *name, int *bus, int *slot, int *func)
738 struct pci_conf_io pc;
739 struct pci_conf conf[1];
740 struct pci_match_conf patterns[1];
743 bzero(&pc, sizeof(struct pci_conf_io));
744 pc.match_buf_len = sizeof(conf);
747 bzero(&patterns, sizeof(patterns));
750 * The pattern structure requires the unit to be split out from
751 * the driver name. Walk backwards from the end of the name to
752 * find the start of the unit.
754 cp = strchr(name, '\0');
756 while (cp != name && isdigit(cp[-1]))
758 if (cp == name || !isdigit(*cp)) {
759 EPRINTLN("Invalid passthru device name %s", name);
762 if ((size_t)(cp - name) + 1 > sizeof(patterns[0].pd_name)) {
763 EPRINTLN("Passthru device name %s is too long", name);
766 memcpy(patterns[0].pd_name, name, cp - name);
767 patterns[0].pd_unit = strtol(cp, &cp, 10);
769 EPRINTLN("Invalid passthru device name %s", name);
772 patterns[0].flags = PCI_GETCONF_MATCH_NAME | PCI_GETCONF_MATCH_UNIT;
774 pc.pat_buf_len = sizeof(patterns);
775 pc.patterns = patterns;
777 if (ioctl(pcifd, PCIOCGETCONF, &pc) == -1) {
778 EPRINTLN("ioctl(PCIOCGETCONF): %s", strerror(errno));
781 if (pc.status != PCI_GETCONF_LAST_DEVICE &&
782 pc.status != PCI_GETCONF_MORE_DEVS) {
783 EPRINTLN("error returned from PCIOCGETCONF ioctl");
786 if (pc.num_matches == 0) {
787 EPRINTLN("Passthru device %s not found", name);
791 if (conf[0].pc_sel.pc_domain != 0) {
792 EPRINTLN("Passthru device %s on unsupported domain", name);
795 *bus = conf[0].pc_sel.pc_bus;
796 *slot = conf[0].pc_sel.pc_dev;
797 *func = conf[0].pc_sel.pc_func;
802 passthru_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
804 int bus, slot, func, error, memflags;
805 struct passthru_softc *sc;
811 memflags = vm_get_memflags(ctx);
812 if (!(memflags & VM_MEM_F_WIRED)) {
813 warnx("passthru requires guest memory to be wired");
817 if (pcifd < 0 && pcifd_init()) {
821 #define GET_INT_CONFIG(var, name) do { \
822 value = get_config_value_node(nvl, name); \
823 if (value == NULL) { \
824 EPRINTLN("passthru: missing required %s setting", name); \
830 value = get_config_value_node(nvl, "pptdev");
832 if (!passthru_lookup_pptdev(value, &bus, &slot, &func))
835 GET_INT_CONFIG(bus, "bus");
836 GET_INT_CONFIG(slot, "slot");
837 GET_INT_CONFIG(func, "func");
840 if (vm_assign_pptdev(ctx, bus, slot, func) != 0) {
841 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
846 sc = calloc(1, sizeof(struct passthru_softc));
851 /* initialize config space */
852 if ((error = cfginit(ctx, pi, bus, slot, func)) != 0)
856 if ((error = passthru_init_rom(ctx, sc,
857 get_config_value_node(nvl, "rom"))) != 0)
860 error = 0; /* success */
864 vm_unassign_pptdev(ctx, bus, slot, func);
872 if ((coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) ||
880 msicap_access(struct passthru_softc *sc, int coff)
884 if (sc->psc_msi.capoff == 0)
887 caplen = msi_caplen(sc->psc_msi.msgctrl);
889 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
896 msixcap_access(struct passthru_softc *sc, int coff)
898 if (sc->psc_msix.capoff == 0)
901 return (coff >= sc->psc_msix.capoff &&
902 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
906 passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
907 int coff, int bytes, uint32_t *rv)
909 struct passthru_softc *sc;
914 * PCI BARs and MSI capability is emulated.
916 if (bar_access(coff) || msicap_access(sc, coff) ||
917 msixcap_access(sc, coff))
920 #ifdef LEGACY_SUPPORT
922 * Emulate PCIR_CAP_PTR if this device does not support MSI capability
925 if (sc->psc_msi.emulated) {
926 if (coff >= PCIR_CAP_PTR && coff < PCIR_CAP_PTR + 4)
932 * Emulate the command register. If a single read reads both the
933 * command and status registers, read the status register from the
934 * device's config space.
936 if (coff == PCIR_COMMAND) {
939 *rv = read_config(&sc->psc_sel, PCIR_STATUS, 2) << 16 |
940 pci_get_cfgdata16(pi, PCIR_COMMAND);
944 /* Everything else just read from the device's config space */
945 *rv = read_config(&sc->psc_sel, coff, bytes);
951 passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
952 int coff, int bytes, uint32_t val)
954 int error, msix_table_entries, i;
955 struct passthru_softc *sc;
961 * PCI BARs are emulated
963 if (bar_access(coff))
967 * MSI capability is emulated
969 if (msicap_access(sc, coff)) {
970 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff,
972 error = vm_setup_pptdev_msi(ctx, vcpu, sc->psc_sel.pc_bus,
973 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
974 pi->pi_msi.addr, pi->pi_msi.msg_data,
975 pi->pi_msi.maxmsgnum);
977 err(1, "vm_setup_pptdev_msi");
981 if (msixcap_access(sc, coff)) {
982 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff,
984 if (pi->pi_msix.enabled) {
985 msix_table_entries = pi->pi_msix.table_count;
986 for (i = 0; i < msix_table_entries; i++) {
987 error = vm_setup_pptdev_msix(ctx, vcpu,
988 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
989 sc->psc_sel.pc_func, i,
990 pi->pi_msix.table[i].addr,
991 pi->pi_msix.table[i].msg_data,
992 pi->pi_msix.table[i].vector_control);
995 err(1, "vm_setup_pptdev_msix");
998 error = vm_disable_pptdev_msix(ctx, sc->psc_sel.pc_bus,
999 sc->psc_sel.pc_dev, sc->psc_sel.pc_func);
1001 err(1, "vm_disable_pptdev_msix");
1006 #ifdef LEGACY_SUPPORT
1008 * If this device does not support MSI natively then we cannot let
1009 * the guest disable legacy interrupts from the device. It is the
1010 * legacy interrupt that is triggering the virtual MSI to the guest.
1012 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
1013 if (coff == PCIR_COMMAND && bytes == 2)
1014 val &= ~PCIM_CMD_INTxDIS;
1018 write_config(&sc->psc_sel, coff, bytes, val);
1019 if (coff == PCIR_COMMAND) {
1020 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);
1022 pci_set_cfgdata8(pi, PCIR_COMMAND, val);
1023 else if (bytes == 2)
1024 pci_set_cfgdata16(pi, PCIR_COMMAND, val);
1025 pci_emul_cmd_changed(pi, cmd_old);
1032 passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1033 uint64_t offset, int size, uint64_t value)
1035 struct passthru_softc *sc;
1036 struct pci_bar_ioreq pio;
1040 if (baridx == pci_msix_table_bar(pi)) {
1041 msix_table_write(ctx, vcpu, sc, offset, size, value);
1043 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1044 assert(size == 1 || size == 2 || size == 4);
1045 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
1047 bzero(&pio, sizeof(pio));
1048 pio.pbi_sel = sc->psc_sel;
1049 pio.pbi_op = PCIBARIO_WRITE;
1050 pio.pbi_bar = baridx;
1051 pio.pbi_offset = (uint32_t)offset;
1052 pio.pbi_width = size;
1053 pio.pbi_value = (uint32_t)value;
1055 (void)ioctl(pcifd, PCIOCBARIO, &pio);
1060 passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1061 uint64_t offset, int size)
1063 struct passthru_softc *sc;
1064 struct pci_bar_ioreq pio;
1069 if (baridx == pci_msix_table_bar(pi)) {
1070 val = msix_table_read(sc, offset, size);
1072 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1073 assert(size == 1 || size == 2 || size == 4);
1074 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
1076 bzero(&pio, sizeof(pio));
1077 pio.pbi_sel = sc->psc_sel;
1078 pio.pbi_op = PCIBARIO_READ;
1079 pio.pbi_bar = baridx;
1080 pio.pbi_offset = (uint32_t)offset;
1081 pio.pbi_width = size;
1083 (void)ioctl(pcifd, PCIOCBARIO, &pio);
1085 val = pio.pbi_value;
1092 passthru_msix_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
1093 int enabled, uint64_t address)
1095 struct passthru_softc *sc;
1097 uint32_t table_size, table_offset;
1100 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
1101 if (table_offset > 0) {
1103 if (vm_unmap_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
1105 sc->psc_sel.pc_func, address,
1107 warnx("pci_passthru: unmap_pptdev_mmio failed");
1109 if (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
1111 sc->psc_sel.pc_func, address,
1113 sc->psc_bar[baridx].addr) != 0)
1114 warnx("pci_passthru: map_pptdev_mmio failed");
1117 table_size = pi->pi_msix.table_offset - table_offset;
1118 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
1119 table_size = roundup2(table_size, 4096);
1120 remaining = pi->pi_bar[baridx].size - table_offset - table_size;
1121 if (remaining > 0) {
1122 address += table_offset + table_size;
1124 if (vm_unmap_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
1126 sc->psc_sel.pc_func, address,
1128 warnx("pci_passthru: unmap_pptdev_mmio failed");
1130 if (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
1132 sc->psc_sel.pc_func, address,
1134 sc->psc_bar[baridx].addr +
1135 table_offset + table_size) != 0)
1136 warnx("pci_passthru: map_pptdev_mmio failed");
1142 passthru_mmio_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
1143 int enabled, uint64_t address)
1145 struct passthru_softc *sc;
1149 if (vm_unmap_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
1151 sc->psc_sel.pc_func, address,
1152 sc->psc_bar[baridx].size) != 0)
1153 warnx("pci_passthru: unmap_pptdev_mmio failed");
1155 if (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
1157 sc->psc_sel.pc_func, address,
1158 sc->psc_bar[baridx].size,
1159 sc->psc_bar[baridx].addr) != 0)
1160 warnx("pci_passthru: map_pptdev_mmio failed");
1165 passthru_addr_rom(struct pci_devinst *const pi, const int idx,
1168 const uint64_t addr = pi->pi_bar[idx].addr;
1169 const uint64_t size = pi->pi_bar[idx].size;
1172 if (vm_munmap_memseg(pi->pi_vmctx, addr, size) != 0) {
1173 errx(4, "%s: munmap_memseg @ [%016lx - %016lx] failed",
1174 __func__, addr, addr + size);
1178 if (vm_mmap_memseg(pi->pi_vmctx, addr, VM_PCIROM,
1179 pi->pi_romoffset, size, PROT_READ | PROT_EXEC) != 0) {
1180 errx(4, "%s: mmap_memseg @ [%016lx - %016lx] failed",
1181 __func__, addr, addr + size);
1187 passthru_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
1188 int enabled, uint64_t address)
1190 switch (pi->pi_bar[baridx].type) {
1192 /* IO BARs are emulated */
1195 passthru_addr_rom(pi, baridx, enabled);
1199 if (baridx == pci_msix_table_bar(pi))
1200 passthru_msix_addr(ctx, pi, baridx, enabled, address);
1202 passthru_mmio_addr(ctx, pi, baridx, enabled, address);
1205 errx(4, "%s: invalid BAR type %d", __func__,
1206 pi->pi_bar[baridx].type);
1210 static const struct pci_devemu passthru = {
1211 .pe_emu = "passthru",
1212 .pe_init = passthru_init,
1213 .pe_legacy_config = passthru_legacy_config,
1214 .pe_cfgwrite = passthru_cfgwrite,
1215 .pe_cfgread = passthru_cfgread,
1216 .pe_barwrite = passthru_write,
1217 .pe_barread = passthru_read,
1218 .pe_baraddr = passthru_addr,
1220 PCI_EMUL_SET(passthru);