2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #ifndef WITHOUT_CAPSICUM
36 #include <sys/capsicum.h>
38 #include <sys/types.h>
40 #include <sys/pciio.h>
41 #include <sys/ioctl.h>
43 #include <dev/io/iodev.h>
44 #include <dev/pci/pcireg.h>
48 #include <machine/iodev.h>
49 #include <machine/vm.h>
51 #ifndef WITHOUT_CAPSICUM
52 #include <capsicum_helpers.h>
63 #include <machine/vmm.h>
72 #define _PATH_DEVPCI "/dev/pci"
75 #define LEGACY_SUPPORT 1
77 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
78 #define MSIX_CAPLEN 12
80 static int pcifd = -1;
82 struct passthru_softc {
83 struct pci_devinst *psc_pi;
84 struct pcibar psc_bar[PCI_BARMAX + 1];
93 struct pcisel psc_sel;
97 msi_caplen(int msgctrl)
101 len = 10; /* minimum length of msi capability */
103 if (msgctrl & PCIM_MSICTRL_64BIT)
108 * Ignore the 'mask' and 'pending' bits in the MSI capability.
109 * We'll let the guest manipulate them directly.
111 if (msgctrl & PCIM_MSICTRL_VECTOR)
119 read_config(const struct pcisel *sel, long reg, int width)
123 bzero(&pi, sizeof(pi));
128 if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
129 return (0); /* XXX */
135 write_config(const struct pcisel *sel, long reg, int width, uint32_t data)
139 bzero(&pi, sizeof(pi));
145 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
148 #ifdef LEGACY_SUPPORT
150 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
153 struct msicap msicap;
156 pci_populate_msicap(&msicap, msgnum, nextptr);
160 * Copy the msi capability structure in the last 16 bytes of the
161 * config space. This is wrong because it could shadow something
162 * useful to the device.
164 capoff = 256 - roundup(sizeof(msicap), 4);
165 capdata = (u_char *)&msicap;
166 for (i = 0; i < sizeof(msicap); i++)
167 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
171 #endif /* LEGACY_SUPPORT */
174 cfginitmsi(struct passthru_softc *sc)
176 int i, ptr, capptr, cap, sts, caplen, table_size;
179 struct pci_devinst *pi;
180 struct msixcap msixcap;
181 uint32_t *msixcap_ptr;
187 * Parse the capabilities and cache the location of the MSI
188 * and MSI-X capabilities.
190 sts = read_config(&sel, PCIR_STATUS, 2);
191 if (sts & PCIM_STATUS_CAPPRESENT) {
192 ptr = read_config(&sel, PCIR_CAP_PTR, 1);
193 while (ptr != 0 && ptr != 0xff) {
194 cap = read_config(&sel, ptr + PCICAP_ID, 1);
195 if (cap == PCIY_MSI) {
197 * Copy the MSI capability into the config
198 * space of the emulated pci device
200 sc->psc_msi.capoff = ptr;
201 sc->psc_msi.msgctrl = read_config(&sel,
203 sc->psc_msi.emulated = 0;
204 caplen = msi_caplen(sc->psc_msi.msgctrl);
207 u32 = read_config(&sel, capptr, 4);
208 pci_set_cfgdata32(pi, capptr, u32);
212 } else if (cap == PCIY_MSIX) {
214 * Copy the MSI-X capability
216 sc->psc_msix.capoff = ptr;
218 msixcap_ptr = (uint32_t*) &msixcap;
221 u32 = read_config(&sel, capptr, 4);
223 pci_set_cfgdata32(pi, capptr, u32);
229 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1);
233 if (sc->psc_msix.capoff != 0) {
234 pi->pi_msix.pba_bar =
235 msixcap.pba_info & PCIM_MSIX_BIR_MASK;
236 pi->pi_msix.pba_offset =
237 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
238 pi->pi_msix.table_bar =
239 msixcap.table_info & PCIM_MSIX_BIR_MASK;
240 pi->pi_msix.table_offset =
241 msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
242 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
243 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
245 /* Allocate the emulated MSI-X table array */
246 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
247 pi->pi_msix.table = calloc(1, table_size);
249 /* Mask all table entries */
250 for (i = 0; i < pi->pi_msix.table_count; i++) {
251 pi->pi_msix.table[i].vector_control |=
252 PCIM_MSIX_VCTRL_MASK;
256 #ifdef LEGACY_SUPPORT
258 * If the passthrough device does not support MSI then craft a
259 * MSI capability for it. We link the new MSI capability at the
260 * head of the list of capabilities.
262 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
264 origptr = read_config(&sel, PCIR_CAP_PTR, 1);
265 msiptr = passthru_add_msicap(pi, 1, origptr);
266 sc->psc_msi.capoff = msiptr;
267 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
268 sc->psc_msi.emulated = 1;
269 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
273 /* Make sure one of the capabilities is present */
274 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
281 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
283 struct pci_devinst *pi;
284 struct msix_table_entry *entry;
291 uint32_t table_offset;
292 int index, table_count;
296 table_offset = pi->pi_msix.table_offset;
297 table_count = pi->pi_msix.table_count;
298 if (offset < table_offset ||
299 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
302 src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
306 src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
310 src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
314 src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
323 offset -= table_offset;
324 index = offset / MSIX_TABLE_ENTRY_SIZE;
325 assert(index < table_count);
327 entry = &pi->pi_msix.table[index];
328 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
332 src8 = (uint8_t *)((uint8_t *)entry + entry_offset);
336 src16 = (uint16_t *)((uint8_t *)entry + entry_offset);
340 src32 = (uint32_t *)((uint8_t *)entry + entry_offset);
344 src64 = (uint64_t *)((uint8_t *)entry + entry_offset);
355 msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc,
356 uint64_t offset, int size, uint64_t data)
358 struct pci_devinst *pi;
359 struct msix_table_entry *entry;
365 uint32_t table_offset, vector_control;
366 int index, table_count;
370 table_offset = pi->pi_msix.table_offset;
371 table_count = pi->pi_msix.table_count;
372 if (offset < table_offset ||
373 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
376 dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
380 dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
384 dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
388 dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
395 offset -= table_offset;
396 index = offset / MSIX_TABLE_ENTRY_SIZE;
397 assert(index < table_count);
399 entry = &pi->pi_msix.table[index];
400 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
402 /* Only 4 byte naturally-aligned writes are supported */
404 assert(entry_offset % 4 == 0);
406 vector_control = entry->vector_control;
407 dest32 = (uint32_t *)((void *)entry + entry_offset);
409 /* If MSI-X hasn't been enabled, do nothing */
410 if (pi->pi_msix.enabled) {
411 /* If the entry is masked, don't set it up */
412 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
413 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
414 (void)vm_setup_pptdev_msix(ctx, vcpu,
415 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
416 sc->psc_sel.pc_func, index, entry->addr,
417 entry->msg_data, entry->vector_control);
423 init_msix_table(struct vmctx *ctx, struct passthru_softc *sc)
425 struct pci_devinst *pi = sc->psc_pi;
426 struct pci_bar_mmap pbm;
428 uint32_t table_size, table_offset;
430 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
432 b = sc->psc_sel.pc_bus;
433 s = sc->psc_sel.pc_dev;
434 f = sc->psc_sel.pc_func;
437 * Map the region of the BAR containing the MSI-X table. This is
438 * necessary for two reasons:
439 * 1. The PBA may reside in the first or last page containing the MSI-X
441 * 2. While PCI devices are not supposed to use the page(s) containing
442 * the MSI-X table for other purposes, some do in practice.
444 memset(&pbm, 0, sizeof(pbm));
445 pbm.pbm_sel = sc->psc_sel;
446 pbm.pbm_flags = PCIIO_BAR_MMAP_RW;
447 pbm.pbm_reg = PCIR_BAR(pi->pi_msix.table_bar);
448 pbm.pbm_memattr = VM_MEMATTR_DEVICE;
450 if (ioctl(pcifd, PCIOCBARMMAP, &pbm) != 0) {
451 warn("Failed to map MSI-X table BAR on %d/%d/%d", b, s, f);
454 assert(pbm.pbm_bar_off == 0);
455 pi->pi_msix.mapped_addr = (uint8_t *)(uintptr_t)pbm.pbm_map_base;
456 pi->pi_msix.mapped_size = pbm.pbm_map_length;
458 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
460 table_size = pi->pi_msix.table_offset - table_offset;
461 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
462 table_size = roundup2(table_size, 4096);
465 * Unmap any pages not containing the table, we do not need to emulate
466 * accesses to them. Avoid releasing address space to help ensure that
467 * a buggy out-of-bounds access causes a crash.
469 if (table_offset != 0)
470 if (mprotect(pi->pi_msix.mapped_addr, table_offset,
472 warn("Failed to unmap MSI-X table BAR region");
473 if (table_offset + table_size != pi->pi_msix.mapped_size)
475 pi->pi_msix.mapped_addr + table_offset + table_size,
476 pi->pi_msix.mapped_size - (table_offset + table_size),
478 warn("Failed to unmap MSI-X table BAR region");
484 cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
487 struct pci_devinst *pi;
488 struct pci_bar_io bar;
489 enum pcibar_type bartype;
495 * Initialize BAR registers
497 for (i = 0; i <= PCI_BARMAX; i++) {
498 bzero(&bar, sizeof(bar));
499 bar.pbi_sel = sc->psc_sel;
500 bar.pbi_reg = PCIR_BAR(i);
502 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
505 if (PCI_BAR_IO(bar.pbi_base)) {
507 base = bar.pbi_base & PCIM_BAR_IO_BASE;
509 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
510 case PCIM_BAR_MEM_64:
511 bartype = PCIBAR_MEM64;
514 bartype = PCIBAR_MEM32;
517 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
519 size = bar.pbi_length;
521 if (bartype != PCIBAR_IO) {
522 if (((base | size) & PAGE_MASK) != 0) {
523 warnx("passthru device %d/%d/%d BAR %d: "
524 "base %#lx or size %#lx not page aligned\n",
525 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
526 sc->psc_sel.pc_func, i, base, size);
531 /* Cache information about the "real" BAR */
532 sc->psc_bar[i].type = bartype;
533 sc->psc_bar[i].size = size;
534 sc->psc_bar[i].addr = base;
535 sc->psc_bar[i].lobits = 0;
537 /* Allocate the BAR in the guest I/O or MMIO space */
538 error = pci_emul_alloc_bar(pi, i, bartype, size);
542 /* Use same lobits as physical bar */
543 uint8_t lobits = read_config(&sc->psc_sel, PCIR_BAR(i), 0x01);
544 if (bartype == PCIBAR_MEM32 || bartype == PCIBAR_MEM64) {
545 lobits &= ~PCIM_BAR_MEM_BASE;
547 lobits &= ~PCIM_BAR_IO_BASE;
549 sc->psc_bar[i].lobits = lobits;
550 pi->pi_bar[i].lobits = lobits;
552 /* The MSI-X table needs special handling */
553 if (i == pci_msix_table_bar(pi)) {
554 error = init_msix_table(ctx, sc);
560 * 64-bit BAR takes up two slots so skip the next one.
562 if (bartype == PCIBAR_MEM64) {
564 assert(i <= PCI_BARMAX);
565 sc->psc_bar[i].type = PCIBAR_MEMHI64;
572 cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
575 struct passthru_softc *sc;
580 bzero(&sc->psc_sel, sizeof(struct pcisel));
581 sc->psc_sel.pc_bus = bus;
582 sc->psc_sel.pc_dev = slot;
583 sc->psc_sel.pc_func = func;
585 if (cfginitmsi(sc) != 0) {
586 warnx("failed to initialize MSI for PCI %d/%d/%d",
591 if (cfginitbar(ctx, sc) != 0) {
592 warnx("failed to initialize BARs for PCI %d/%d/%d",
597 write_config(&sc->psc_sel, PCIR_COMMAND, 2,
598 pci_get_cfgdata16(pi, PCIR_COMMAND));
601 * We need to do this after PCIR_COMMAND got possibly updated, e.g.,
602 * a BAR was enabled, as otherwise the PCIOCBARMMAP might fail on us.
604 if (pci_msix_table_bar(pi) >= 0) {
605 error = init_msix_table(ctx, sc);
608 "failed to initialize MSI-X table for PCI %d/%d/%d: %d",
609 bus, slot, func, error);
614 error = 0; /* success */
620 passthru_legacy_config(nvlist_t *nvl, const char *opts)
628 if (sscanf(opts, "%d/%d/%d", &bus, &slot, &func) != 3) {
629 EPRINTLN("passthru: invalid options \"%s\"", opts);
633 snprintf(value, sizeof(value), "%d", bus);
634 set_config_value_node(nvl, "bus", value);
635 snprintf(value, sizeof(value), "%d", slot);
636 set_config_value_node(nvl, "slot", value);
637 snprintf(value, sizeof(value), "%d", func);
638 set_config_value_node(nvl, "func", value);
643 passthru_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
645 int bus, slot, func, error, memflags;
646 struct passthru_softc *sc;
648 #ifndef WITHOUT_CAPSICUM
650 cap_ioctl_t pci_ioctls[] =
651 { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR, PCIOCBARIO, PCIOCBARMMAP };
657 #ifndef WITHOUT_CAPSICUM
658 cap_rights_init(&rights, CAP_IOCTL, CAP_READ, CAP_WRITE);
661 memflags = vm_get_memflags(ctx);
662 if (!(memflags & VM_MEM_F_WIRED)) {
663 warnx("passthru requires guest memory to be wired");
668 pcifd = open(_PATH_DEVPCI, O_RDWR, 0);
670 warn("failed to open %s", _PATH_DEVPCI);
675 #ifndef WITHOUT_CAPSICUM
676 if (caph_rights_limit(pcifd, &rights) == -1)
677 errx(EX_OSERR, "Unable to apply rights for sandbox");
678 if (caph_ioctls_limit(pcifd, pci_ioctls, nitems(pci_ioctls)) == -1)
679 errx(EX_OSERR, "Unable to apply rights for sandbox");
682 #define GET_INT_CONFIG(var, name) do { \
683 value = get_config_value_node(nvl, name); \
684 if (value == NULL) { \
685 EPRINTLN("passthru: missing required %s setting", name); \
691 GET_INT_CONFIG(bus, "bus");
692 GET_INT_CONFIG(slot, "slot");
693 GET_INT_CONFIG(func, "func");
695 if (vm_assign_pptdev(ctx, bus, slot, func) != 0) {
696 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
701 sc = calloc(1, sizeof(struct passthru_softc));
706 /* initialize config space */
707 error = cfginit(ctx, pi, bus, slot, func);
711 vm_unassign_pptdev(ctx, bus, slot, func);
719 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1))
726 msicap_access(struct passthru_softc *sc, int coff)
730 if (sc->psc_msi.capoff == 0)
733 caplen = msi_caplen(sc->psc_msi.msgctrl);
735 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
742 msixcap_access(struct passthru_softc *sc, int coff)
744 if (sc->psc_msix.capoff == 0)
747 return (coff >= sc->psc_msix.capoff &&
748 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
752 passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
753 int coff, int bytes, uint32_t *rv)
755 struct passthru_softc *sc;
760 * PCI BARs and MSI capability is emulated.
762 if (bar_access(coff) || msicap_access(sc, coff) ||
763 msixcap_access(sc, coff))
766 #ifdef LEGACY_SUPPORT
768 * Emulate PCIR_CAP_PTR if this device does not support MSI capability
771 if (sc->psc_msi.emulated) {
772 if (coff >= PCIR_CAP_PTR && coff < PCIR_CAP_PTR + 4)
778 * Emulate the command register. If a single read reads both the
779 * command and status registers, read the status register from the
780 * device's config space.
782 if (coff == PCIR_COMMAND) {
785 *rv = read_config(&sc->psc_sel, PCIR_STATUS, 2) << 16 |
786 pci_get_cfgdata16(pi, PCIR_COMMAND);
790 /* Everything else just read from the device's config space */
791 *rv = read_config(&sc->psc_sel, coff, bytes);
797 passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
798 int coff, int bytes, uint32_t val)
800 int error, msix_table_entries, i;
801 struct passthru_softc *sc;
807 * PCI BARs are emulated
809 if (bar_access(coff))
813 * MSI capability is emulated
815 if (msicap_access(sc, coff)) {
816 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff,
818 error = vm_setup_pptdev_msi(ctx, vcpu, sc->psc_sel.pc_bus,
819 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
820 pi->pi_msi.addr, pi->pi_msi.msg_data,
821 pi->pi_msi.maxmsgnum);
823 err(1, "vm_setup_pptdev_msi");
827 if (msixcap_access(sc, coff)) {
828 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff,
830 if (pi->pi_msix.enabled) {
831 msix_table_entries = pi->pi_msix.table_count;
832 for (i = 0; i < msix_table_entries; i++) {
833 error = vm_setup_pptdev_msix(ctx, vcpu,
834 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
835 sc->psc_sel.pc_func, i,
836 pi->pi_msix.table[i].addr,
837 pi->pi_msix.table[i].msg_data,
838 pi->pi_msix.table[i].vector_control);
841 err(1, "vm_setup_pptdev_msix");
844 error = vm_disable_pptdev_msix(ctx, sc->psc_sel.pc_bus,
845 sc->psc_sel.pc_dev, sc->psc_sel.pc_func);
847 err(1, "vm_disable_pptdev_msix");
852 #ifdef LEGACY_SUPPORT
854 * If this device does not support MSI natively then we cannot let
855 * the guest disable legacy interrupts from the device. It is the
856 * legacy interrupt that is triggering the virtual MSI to the guest.
858 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
859 if (coff == PCIR_COMMAND && bytes == 2)
860 val &= ~PCIM_CMD_INTxDIS;
864 write_config(&sc->psc_sel, coff, bytes, val);
865 if (coff == PCIR_COMMAND) {
866 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);
868 pci_set_cfgdata8(pi, PCIR_COMMAND, val);
870 pci_set_cfgdata16(pi, PCIR_COMMAND, val);
871 pci_emul_cmd_changed(pi, cmd_old);
878 passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
879 uint64_t offset, int size, uint64_t value)
881 struct passthru_softc *sc;
882 struct pci_bar_ioreq pio;
886 if (baridx == pci_msix_table_bar(pi)) {
887 msix_table_write(ctx, vcpu, sc, offset, size, value);
889 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
890 assert(size == 1 || size == 2 || size == 4);
891 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
893 bzero(&pio, sizeof(pio));
894 pio.pbi_sel = sc->psc_sel;
895 pio.pbi_op = PCIBARIO_WRITE;
896 pio.pbi_bar = baridx;
897 pio.pbi_offset = (uint32_t)offset;
898 pio.pbi_width = size;
899 pio.pbi_value = (uint32_t)value;
901 (void)ioctl(pcifd, PCIOCBARIO, &pio);
906 passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
907 uint64_t offset, int size)
909 struct passthru_softc *sc;
910 struct pci_bar_ioreq pio;
915 if (baridx == pci_msix_table_bar(pi)) {
916 val = msix_table_read(sc, offset, size);
918 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
919 assert(size == 1 || size == 2 || size == 4);
920 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
922 bzero(&pio, sizeof(pio));
923 pio.pbi_sel = sc->psc_sel;
924 pio.pbi_op = PCIBARIO_READ;
925 pio.pbi_bar = baridx;
926 pio.pbi_offset = (uint32_t)offset;
927 pio.pbi_width = size;
929 (void)ioctl(pcifd, PCIOCBARIO, &pio);
938 passthru_msix_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
939 int enabled, uint64_t address)
941 struct passthru_softc *sc;
943 uint32_t table_size, table_offset;
946 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
947 if (table_offset > 0) {
949 if (vm_unmap_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
951 sc->psc_sel.pc_func, address,
953 warnx("pci_passthru: unmap_pptdev_mmio failed");
955 if (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
957 sc->psc_sel.pc_func, address,
959 sc->psc_bar[baridx].addr) != 0)
960 warnx("pci_passthru: map_pptdev_mmio failed");
963 table_size = pi->pi_msix.table_offset - table_offset;
964 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
965 table_size = roundup2(table_size, 4096);
966 remaining = pi->pi_bar[baridx].size - table_offset - table_size;
968 address += table_offset + table_size;
970 if (vm_unmap_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
972 sc->psc_sel.pc_func, address,
974 warnx("pci_passthru: unmap_pptdev_mmio failed");
976 if (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
978 sc->psc_sel.pc_func, address,
980 sc->psc_bar[baridx].addr +
981 table_offset + table_size) != 0)
982 warnx("pci_passthru: map_pptdev_mmio failed");
988 passthru_mmio_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
989 int enabled, uint64_t address)
991 struct passthru_softc *sc;
995 if (vm_unmap_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
997 sc->psc_sel.pc_func, address,
998 sc->psc_bar[baridx].size) != 0)
999 warnx("pci_passthru: unmap_pptdev_mmio failed");
1001 if (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
1003 sc->psc_sel.pc_func, address,
1004 sc->psc_bar[baridx].size,
1005 sc->psc_bar[baridx].addr) != 0)
1006 warnx("pci_passthru: map_pptdev_mmio failed");
1011 passthru_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
1012 int enabled, uint64_t address)
1015 if (pi->pi_bar[baridx].type == PCIBAR_IO)
1017 if (baridx == pci_msix_table_bar(pi))
1018 passthru_msix_addr(ctx, pi, baridx, enabled, address);
1020 passthru_mmio_addr(ctx, pi, baridx, enabled, address);
1023 struct pci_devemu passthru = {
1024 .pe_emu = "passthru",
1025 .pe_init = passthru_init,
1026 .pe_legacy_config = passthru_legacy_config,
1027 .pe_cfgwrite = passthru_cfgwrite,
1028 .pe_cfgread = passthru_cfgread,
1029 .pe_barwrite = passthru_write,
1030 .pe_barread = passthru_read,
1031 .pe_baraddr = passthru_addr,
1033 PCI_EMUL_SET(passthru);