2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #ifndef WITHOUT_CAPSICUM
36 #include <sys/capsicum.h>
38 #include <sys/types.h>
40 #include <sys/pciio.h>
41 #include <sys/ioctl.h>
43 #include <dev/io/iodev.h>
44 #include <dev/pci/pcireg.h>
46 #include <machine/iodev.h>
48 #ifndef WITHOUT_CAPSICUM
49 #include <capsicum_helpers.h>
60 #include <machine/vmm.h>
66 #define _PATH_DEVPCI "/dev/pci"
70 #define _PATH_DEVIO "/dev/io"
74 #define _PATH_MEM "/dev/mem"
77 #define LEGACY_SUPPORT 1
79 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
80 #define MSIX_CAPLEN 12
82 static int pcifd = -1;
84 static int memfd = -1;
86 struct passthru_softc {
87 struct pci_devinst *psc_pi;
88 struct pcibar psc_bar[PCI_BARMAX + 1];
97 struct pcisel psc_sel;
101 msi_caplen(int msgctrl)
105 len = 10; /* minimum length of msi capability */
107 if (msgctrl & PCIM_MSICTRL_64BIT)
112 * Ignore the 'mask' and 'pending' bits in the MSI capability.
113 * We'll let the guest manipulate them directly.
115 if (msgctrl & PCIM_MSICTRL_VECTOR)
123 read_config(const struct pcisel *sel, long reg, int width)
127 bzero(&pi, sizeof(pi));
132 if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
133 return (0); /* XXX */
139 write_config(const struct pcisel *sel, long reg, int width, uint32_t data)
143 bzero(&pi, sizeof(pi));
149 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
152 #ifdef LEGACY_SUPPORT
154 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
157 struct msicap msicap;
160 pci_populate_msicap(&msicap, msgnum, nextptr);
164 * Copy the msi capability structure in the last 16 bytes of the
165 * config space. This is wrong because it could shadow something
166 * useful to the device.
168 capoff = 256 - roundup(sizeof(msicap), 4);
169 capdata = (u_char *)&msicap;
170 for (i = 0; i < sizeof(msicap); i++)
171 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
175 #endif /* LEGACY_SUPPORT */
178 cfginitmsi(struct passthru_softc *sc)
180 int i, ptr, capptr, cap, sts, caplen, table_size;
183 struct pci_devinst *pi;
184 struct msixcap msixcap;
185 uint32_t *msixcap_ptr;
191 * Parse the capabilities and cache the location of the MSI
192 * and MSI-X capabilities.
194 sts = read_config(&sel, PCIR_STATUS, 2);
195 if (sts & PCIM_STATUS_CAPPRESENT) {
196 ptr = read_config(&sel, PCIR_CAP_PTR, 1);
197 while (ptr != 0 && ptr != 0xff) {
198 cap = read_config(&sel, ptr + PCICAP_ID, 1);
199 if (cap == PCIY_MSI) {
201 * Copy the MSI capability into the config
202 * space of the emulated pci device
204 sc->psc_msi.capoff = ptr;
205 sc->psc_msi.msgctrl = read_config(&sel,
207 sc->psc_msi.emulated = 0;
208 caplen = msi_caplen(sc->psc_msi.msgctrl);
211 u32 = read_config(&sel, capptr, 4);
212 pci_set_cfgdata32(pi, capptr, u32);
216 } else if (cap == PCIY_MSIX) {
218 * Copy the MSI-X capability
220 sc->psc_msix.capoff = ptr;
222 msixcap_ptr = (uint32_t*) &msixcap;
225 u32 = read_config(&sel, capptr, 4);
227 pci_set_cfgdata32(pi, capptr, u32);
233 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1);
237 if (sc->psc_msix.capoff != 0) {
238 pi->pi_msix.pba_bar =
239 msixcap.pba_info & PCIM_MSIX_BIR_MASK;
240 pi->pi_msix.pba_offset =
241 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
242 pi->pi_msix.table_bar =
243 msixcap.table_info & PCIM_MSIX_BIR_MASK;
244 pi->pi_msix.table_offset =
245 msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
246 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
247 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
249 /* Allocate the emulated MSI-X table array */
250 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
251 pi->pi_msix.table = calloc(1, table_size);
253 /* Mask all table entries */
254 for (i = 0; i < pi->pi_msix.table_count; i++) {
255 pi->pi_msix.table[i].vector_control |=
256 PCIM_MSIX_VCTRL_MASK;
260 #ifdef LEGACY_SUPPORT
262 * If the passthrough device does not support MSI then craft a
263 * MSI capability for it. We link the new MSI capability at the
264 * head of the list of capabilities.
266 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
268 origptr = read_config(&sel, PCIR_CAP_PTR, 1);
269 msiptr = passthru_add_msicap(pi, 1, origptr);
270 sc->psc_msi.capoff = msiptr;
271 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
272 sc->psc_msi.emulated = 1;
273 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
277 /* Make sure one of the capabilities is present */
278 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
285 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
287 struct pci_devinst *pi;
288 struct msix_table_entry *entry;
298 if (pi->pi_msix.pba_page != NULL && offset >= pi->pi_msix.pba_offset &&
299 offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
302 src8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
303 pi->pi_msix.pba_page_offset);
307 src16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
308 pi->pi_msix.pba_page_offset);
312 src32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
313 pi->pi_msix.pba_page_offset);
317 src64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
318 pi->pi_msix.pba_page_offset);
327 if (offset < pi->pi_msix.table_offset)
330 offset -= pi->pi_msix.table_offset;
331 index = offset / MSIX_TABLE_ENTRY_SIZE;
332 if (index >= pi->pi_msix.table_count)
335 entry = &pi->pi_msix.table[index];
336 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
340 src8 = (uint8_t *)((void *)entry + entry_offset);
344 src16 = (uint16_t *)((void *)entry + entry_offset);
348 src32 = (uint32_t *)((void *)entry + entry_offset);
352 src64 = (uint64_t *)((void *)entry + entry_offset);
363 msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc,
364 uint64_t offset, int size, uint64_t data)
366 struct pci_devinst *pi;
367 struct msix_table_entry *entry;
373 uint32_t vector_control;
377 if (pi->pi_msix.pba_page != NULL && offset >= pi->pi_msix.pba_offset &&
378 offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
381 dest8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
382 pi->pi_msix.pba_page_offset);
386 dest16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
387 pi->pi_msix.pba_page_offset);
391 dest32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
392 pi->pi_msix.pba_page_offset);
396 dest64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
397 pi->pi_msix.pba_page_offset);
406 if (offset < pi->pi_msix.table_offset)
409 offset -= pi->pi_msix.table_offset;
410 index = offset / MSIX_TABLE_ENTRY_SIZE;
411 if (index >= pi->pi_msix.table_count)
414 entry = &pi->pi_msix.table[index];
415 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
417 /* Only 4 byte naturally-aligned writes are supported */
419 assert(entry_offset % 4 == 0);
421 vector_control = entry->vector_control;
422 dest32 = (uint32_t *)((void *)entry + entry_offset);
424 /* If MSI-X hasn't been enabled, do nothing */
425 if (pi->pi_msix.enabled) {
426 /* If the entry is masked, don't set it up */
427 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
428 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
429 (void)vm_setup_pptdev_msix(ctx, vcpu,
430 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
431 sc->psc_sel.pc_func, index, entry->addr,
432 entry->msg_data, entry->vector_control);
438 init_msix_table(struct vmctx *ctx, struct passthru_softc *sc, uint64_t base)
442 size_t len, remaining;
443 uint32_t table_size, table_offset;
444 uint32_t pba_size, pba_offset;
446 struct pci_devinst *pi = sc->psc_pi;
448 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
450 b = sc->psc_sel.pc_bus;
451 s = sc->psc_sel.pc_dev;
452 f = sc->psc_sel.pc_func;
455 * If the MSI-X table BAR maps memory intended for
456 * other uses, it is at least assured that the table
457 * either resides in its own page within the region,
458 * or it resides in a page shared with only the PBA.
460 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
462 table_size = pi->pi_msix.table_offset - table_offset;
463 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
464 table_size = roundup2(table_size, 4096);
466 idx = pi->pi_msix.table_bar;
467 start = pi->pi_bar[idx].addr;
468 remaining = pi->pi_bar[idx].size;
470 if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar) {
471 pba_offset = pi->pi_msix.pba_offset;
472 pba_size = pi->pi_msix.pba_size;
473 if (pba_offset >= table_offset + table_size ||
474 table_offset >= pba_offset + pba_size) {
476 * If the PBA does not share a page with the MSI-x
477 * tables, no PBA emulation is required.
479 pi->pi_msix.pba_page = NULL;
480 pi->pi_msix.pba_page_offset = 0;
483 * The PBA overlaps with either the first or last
484 * page of the MSI-X table region. Map the
487 if (pba_offset <= table_offset)
488 pi->pi_msix.pba_page_offset = table_offset;
490 pi->pi_msix.pba_page_offset = table_offset +
492 pi->pi_msix.pba_page = mmap(NULL, 4096, PROT_READ |
493 PROT_WRITE, MAP_SHARED, memfd, start +
494 pi->pi_msix.pba_page_offset);
495 if (pi->pi_msix.pba_page == MAP_FAILED) {
497 "Failed to map PBA page for MSI-X on %d/%d/%d",
504 /* Map everything before the MSI-X table */
505 if (table_offset > 0) {
507 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
516 /* Skip the MSI-X table */
519 remaining -= table_size;
521 /* Map everything beyond the end of the MSI-X table */
524 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
533 cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
536 struct pci_devinst *pi;
537 struct pci_bar_io bar;
538 enum pcibar_type bartype;
544 * Initialize BAR registers
546 for (i = 0; i <= PCI_BARMAX; i++) {
547 bzero(&bar, sizeof(bar));
548 bar.pbi_sel = sc->psc_sel;
549 bar.pbi_reg = PCIR_BAR(i);
551 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
554 if (PCI_BAR_IO(bar.pbi_base)) {
556 base = bar.pbi_base & PCIM_BAR_IO_BASE;
558 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
559 case PCIM_BAR_MEM_64:
560 bartype = PCIBAR_MEM64;
563 bartype = PCIBAR_MEM32;
566 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
568 size = bar.pbi_length;
570 if (bartype != PCIBAR_IO) {
571 if (((base | size) & PAGE_MASK) != 0) {
572 warnx("passthru device %d/%d/%d BAR %d: "
573 "base %#lx or size %#lx not page aligned\n",
574 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
575 sc->psc_sel.pc_func, i, base, size);
580 /* Cache information about the "real" BAR */
581 sc->psc_bar[i].type = bartype;
582 sc->psc_bar[i].size = size;
583 sc->psc_bar[i].addr = base;
585 /* Allocate the BAR in the guest I/O or MMIO space */
586 error = pci_emul_alloc_bar(pi, i, bartype, size);
590 /* The MSI-X table needs special handling */
591 if (i == pci_msix_table_bar(pi)) {
592 error = init_msix_table(ctx, sc, base);
595 } else if (bartype != PCIBAR_IO) {
596 /* Map the physical BAR in the guest MMIO space */
597 error = vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
598 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
599 pi->pi_bar[i].addr, pi->pi_bar[i].size, base);
605 * 64-bit BAR takes up two slots so skip the next one.
607 if (bartype == PCIBAR_MEM64) {
609 assert(i <= PCI_BARMAX);
610 sc->psc_bar[i].type = PCIBAR_MEMHI64;
617 cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
620 struct passthru_softc *sc;
625 bzero(&sc->psc_sel, sizeof(struct pcisel));
626 sc->psc_sel.pc_bus = bus;
627 sc->psc_sel.pc_dev = slot;
628 sc->psc_sel.pc_func = func;
630 if (cfginitmsi(sc) != 0) {
631 warnx("failed to initialize MSI for PCI %d/%d/%d",
636 if (cfginitbar(ctx, sc) != 0) {
637 warnx("failed to initialize BARs for PCI %d/%d/%d",
642 pci_set_cfgdata16(pi, PCIR_COMMAND, read_config(&sc->psc_sel,
645 error = 0; /* success */
651 passthru_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
653 int bus, slot, func, error, memflags;
654 struct passthru_softc *sc;
655 #ifndef WITHOUT_CAPSICUM
657 cap_ioctl_t pci_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR };
658 cap_ioctl_t io_ioctls[] = { IODEV_PIO };
664 #ifndef WITHOUT_CAPSICUM
665 cap_rights_init(&rights, CAP_IOCTL, CAP_READ, CAP_WRITE);
668 memflags = vm_get_memflags(ctx);
669 if (!(memflags & VM_MEM_F_WIRED)) {
670 warnx("passthru requires guest memory to be wired");
675 pcifd = open(_PATH_DEVPCI, O_RDWR, 0);
677 warn("failed to open %s", _PATH_DEVPCI);
682 #ifndef WITHOUT_CAPSICUM
683 if (caph_rights_limit(pcifd, &rights) == -1)
684 errx(EX_OSERR, "Unable to apply rights for sandbox");
685 if (caph_ioctls_limit(pcifd, pci_ioctls, nitems(pci_ioctls)) == -1)
686 errx(EX_OSERR, "Unable to apply rights for sandbox");
690 iofd = open(_PATH_DEVIO, O_RDWR, 0);
692 warn("failed to open %s", _PATH_DEVIO);
697 #ifndef WITHOUT_CAPSICUM
698 if (caph_rights_limit(iofd, &rights) == -1)
699 errx(EX_OSERR, "Unable to apply rights for sandbox");
700 if (caph_ioctls_limit(iofd, io_ioctls, nitems(io_ioctls)) == -1)
701 errx(EX_OSERR, "Unable to apply rights for sandbox");
705 memfd = open(_PATH_MEM, O_RDWR, 0);
707 warn("failed to open %s", _PATH_MEM);
712 #ifndef WITHOUT_CAPSICUM
713 cap_rights_clear(&rights, CAP_IOCTL);
714 cap_rights_set(&rights, CAP_MMAP_RW);
715 if (caph_rights_limit(memfd, &rights) == -1)
716 errx(EX_OSERR, "Unable to apply rights for sandbox");
720 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) != 3) {
721 warnx("invalid passthru options");
725 if (vm_assign_pptdev(ctx, bus, slot, func) != 0) {
726 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
731 sc = calloc(1, sizeof(struct passthru_softc));
736 /* initialize config space */
737 error = cfginit(ctx, pi, bus, slot, func);
741 vm_unassign_pptdev(ctx, bus, slot, func);
749 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1))
756 msicap_access(struct passthru_softc *sc, int coff)
760 if (sc->psc_msi.capoff == 0)
763 caplen = msi_caplen(sc->psc_msi.msgctrl);
765 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
772 msixcap_access(struct passthru_softc *sc, int coff)
774 if (sc->psc_msix.capoff == 0)
777 return (coff >= sc->psc_msix.capoff &&
778 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
782 passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
783 int coff, int bytes, uint32_t *rv)
785 struct passthru_softc *sc;
790 * PCI BARs and MSI capability is emulated.
792 if (bar_access(coff) || msicap_access(sc, coff))
795 #ifdef LEGACY_SUPPORT
797 * Emulate PCIR_CAP_PTR if this device does not support MSI capability
800 if (sc->psc_msi.emulated) {
801 if (coff >= PCIR_CAP_PTR && coff < PCIR_CAP_PTR + 4)
807 * Emulate the command register. If a single read reads both the
808 * command and status registers, read the status register from the
809 * device's config space.
811 if (coff == PCIR_COMMAND) {
814 *rv = read_config(&sc->psc_sel, PCIR_STATUS, 2) << 16 |
815 pci_get_cfgdata16(pi, PCIR_COMMAND);
819 /* Everything else just read from the device's config space */
820 *rv = read_config(&sc->psc_sel, coff, bytes);
826 passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
827 int coff, int bytes, uint32_t val)
829 int error, msix_table_entries, i;
830 struct passthru_softc *sc;
836 * PCI BARs are emulated
838 if (bar_access(coff))
842 * MSI capability is emulated
844 if (msicap_access(sc, coff)) {
845 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff,
847 error = vm_setup_pptdev_msi(ctx, vcpu, sc->psc_sel.pc_bus,
848 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
849 pi->pi_msi.addr, pi->pi_msi.msg_data,
850 pi->pi_msi.maxmsgnum);
852 err(1, "vm_setup_pptdev_msi");
856 if (msixcap_access(sc, coff)) {
857 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff,
859 if (pi->pi_msix.enabled) {
860 msix_table_entries = pi->pi_msix.table_count;
861 for (i = 0; i < msix_table_entries; i++) {
862 error = vm_setup_pptdev_msix(ctx, vcpu,
863 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
864 sc->psc_sel.pc_func, i,
865 pi->pi_msix.table[i].addr,
866 pi->pi_msix.table[i].msg_data,
867 pi->pi_msix.table[i].vector_control);
870 err(1, "vm_setup_pptdev_msix");
876 #ifdef LEGACY_SUPPORT
878 * If this device does not support MSI natively then we cannot let
879 * the guest disable legacy interrupts from the device. It is the
880 * legacy interrupt that is triggering the virtual MSI to the guest.
882 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
883 if (coff == PCIR_COMMAND && bytes == 2)
884 val &= ~PCIM_CMD_INTxDIS;
888 write_config(&sc->psc_sel, coff, bytes, val);
889 if (coff == PCIR_COMMAND) {
890 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);
892 pci_set_cfgdata8(pi, PCIR_COMMAND, val);
894 pci_set_cfgdata16(pi, PCIR_COMMAND, val);
895 pci_emul_cmd_changed(pi, cmd_old);
902 passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
903 uint64_t offset, int size, uint64_t value)
905 struct passthru_softc *sc;
906 struct iodev_pio_req pio;
910 if (baridx == pci_msix_table_bar(pi)) {
911 msix_table_write(ctx, vcpu, sc, offset, size, value);
913 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
914 bzero(&pio, sizeof(struct iodev_pio_req));
915 pio.access = IODEV_PIO_WRITE;
916 pio.port = sc->psc_bar[baridx].addr + offset;
920 (void)ioctl(iofd, IODEV_PIO, &pio);
925 passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
926 uint64_t offset, int size)
928 struct passthru_softc *sc;
929 struct iodev_pio_req pio;
934 if (baridx == pci_msix_table_bar(pi)) {
935 val = msix_table_read(sc, offset, size);
937 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
938 bzero(&pio, sizeof(struct iodev_pio_req));
939 pio.access = IODEV_PIO_READ;
940 pio.port = sc->psc_bar[baridx].addr + offset;
944 (void)ioctl(iofd, IODEV_PIO, &pio);
952 struct pci_devemu passthru = {
953 .pe_emu = "passthru",
954 .pe_init = passthru_init,
955 .pe_cfgwrite = passthru_cfgwrite,
956 .pe_cfgread = passthru_cfgread,
957 .pe_barwrite = passthru_write,
958 .pe_barread = passthru_read,
960 PCI_EMUL_SET(passthru);