2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #ifndef WITHOUT_CAPSICUM
36 #include <sys/capsicum.h>
38 #include <sys/types.h>
40 #include <sys/pciio.h>
41 #include <sys/ioctl.h>
43 #include <dev/io/iodev.h>
44 #include <dev/pci/pcireg.h>
46 #include <machine/iodev.h>
57 #include <machine/vmm.h>
63 #define _PATH_DEVPCI "/dev/pci"
67 #define _PATH_DEVIO "/dev/io"
71 #define _PATH_MEM "/dev/mem"
74 #define LEGACY_SUPPORT 1
76 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
77 #define MSIX_CAPLEN 12
79 static int pcifd = -1;
81 static int memfd = -1;
83 struct passthru_softc {
84 struct pci_devinst *psc_pi;
85 struct pcibar psc_bar[PCI_BARMAX + 1];
94 struct pcisel psc_sel;
98 msi_caplen(int msgctrl)
102 len = 10; /* minimum length of msi capability */
104 if (msgctrl & PCIM_MSICTRL_64BIT)
109 * Ignore the 'mask' and 'pending' bits in the MSI capability.
110 * We'll let the guest manipulate them directly.
112 if (msgctrl & PCIM_MSICTRL_VECTOR)
120 read_config(const struct pcisel *sel, long reg, int width)
124 bzero(&pi, sizeof(pi));
129 if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
130 return (0); /* XXX */
136 write_config(const struct pcisel *sel, long reg, int width, uint32_t data)
140 bzero(&pi, sizeof(pi));
146 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
149 #ifdef LEGACY_SUPPORT
151 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
154 struct msicap msicap;
157 pci_populate_msicap(&msicap, msgnum, nextptr);
161 * Copy the msi capability structure in the last 16 bytes of the
162 * config space. This is wrong because it could shadow something
163 * useful to the device.
165 capoff = 256 - roundup(sizeof(msicap), 4);
166 capdata = (u_char *)&msicap;
167 for (i = 0; i < sizeof(msicap); i++)
168 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
172 #endif /* LEGACY_SUPPORT */
175 cfginitmsi(struct passthru_softc *sc)
177 int i, ptr, capptr, cap, sts, caplen, table_size;
180 struct pci_devinst *pi;
181 struct msixcap msixcap;
182 uint32_t *msixcap_ptr;
188 * Parse the capabilities and cache the location of the MSI
189 * and MSI-X capabilities.
191 sts = read_config(&sel, PCIR_STATUS, 2);
192 if (sts & PCIM_STATUS_CAPPRESENT) {
193 ptr = read_config(&sel, PCIR_CAP_PTR, 1);
194 while (ptr != 0 && ptr != 0xff) {
195 cap = read_config(&sel, ptr + PCICAP_ID, 1);
196 if (cap == PCIY_MSI) {
198 * Copy the MSI capability into the config
199 * space of the emulated pci device
201 sc->psc_msi.capoff = ptr;
202 sc->psc_msi.msgctrl = read_config(&sel,
204 sc->psc_msi.emulated = 0;
205 caplen = msi_caplen(sc->psc_msi.msgctrl);
208 u32 = read_config(&sel, capptr, 4);
209 pci_set_cfgdata32(pi, capptr, u32);
213 } else if (cap == PCIY_MSIX) {
215 * Copy the MSI-X capability
217 sc->psc_msix.capoff = ptr;
219 msixcap_ptr = (uint32_t*) &msixcap;
222 u32 = read_config(&sel, capptr, 4);
224 pci_set_cfgdata32(pi, capptr, u32);
230 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1);
234 if (sc->psc_msix.capoff != 0) {
235 pi->pi_msix.pba_bar =
236 msixcap.pba_info & PCIM_MSIX_BIR_MASK;
237 pi->pi_msix.pba_offset =
238 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
239 pi->pi_msix.table_bar =
240 msixcap.table_info & PCIM_MSIX_BIR_MASK;
241 pi->pi_msix.table_offset =
242 msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
243 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
244 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
246 /* Allocate the emulated MSI-X table array */
247 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
248 pi->pi_msix.table = calloc(1, table_size);
250 /* Mask all table entries */
251 for (i = 0; i < pi->pi_msix.table_count; i++) {
252 pi->pi_msix.table[i].vector_control |=
253 PCIM_MSIX_VCTRL_MASK;
257 #ifdef LEGACY_SUPPORT
259 * If the passthrough device does not support MSI then craft a
260 * MSI capability for it. We link the new MSI capability at the
261 * head of the list of capabilities.
263 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
265 origptr = read_config(&sel, PCIR_CAP_PTR, 1);
266 msiptr = passthru_add_msicap(pi, 1, origptr);
267 sc->psc_msi.capoff = msiptr;
268 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
269 sc->psc_msi.emulated = 1;
270 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
274 /* Make sure one of the capabilities is present */
275 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
282 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
284 struct pci_devinst *pi;
285 struct msix_table_entry *entry;
295 if (offset >= pi->pi_msix.pba_offset &&
296 offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
299 src8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
300 pi->pi_msix.pba_page_offset);
304 src16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
305 pi->pi_msix.pba_page_offset);
309 src32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
310 pi->pi_msix.pba_page_offset);
314 src64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
315 pi->pi_msix.pba_page_offset);
324 if (offset < pi->pi_msix.table_offset)
327 offset -= pi->pi_msix.table_offset;
328 index = offset / MSIX_TABLE_ENTRY_SIZE;
329 if (index >= pi->pi_msix.table_count)
332 entry = &pi->pi_msix.table[index];
333 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
337 src8 = (uint8_t *)((void *)entry + entry_offset);
341 src16 = (uint16_t *)((void *)entry + entry_offset);
345 src32 = (uint32_t *)((void *)entry + entry_offset);
349 src64 = (uint64_t *)((void *)entry + entry_offset);
360 msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc,
361 uint64_t offset, int size, uint64_t data)
363 struct pci_devinst *pi;
364 struct msix_table_entry *entry;
370 uint32_t vector_control;
374 if (offset >= pi->pi_msix.pba_offset &&
375 offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
378 dest8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
379 pi->pi_msix.pba_page_offset);
383 dest16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
384 pi->pi_msix.pba_page_offset);
388 dest32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
389 pi->pi_msix.pba_page_offset);
393 dest64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
394 pi->pi_msix.pba_page_offset);
403 if (offset < pi->pi_msix.table_offset)
406 offset -= pi->pi_msix.table_offset;
407 index = offset / MSIX_TABLE_ENTRY_SIZE;
408 if (index >= pi->pi_msix.table_count)
411 entry = &pi->pi_msix.table[index];
412 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
414 /* Only 4 byte naturally-aligned writes are supported */
416 assert(entry_offset % 4 == 0);
418 vector_control = entry->vector_control;
419 dest32 = (uint32_t *)((void *)entry + entry_offset);
421 /* If MSI-X hasn't been enabled, do nothing */
422 if (pi->pi_msix.enabled) {
423 /* If the entry is masked, don't set it up */
424 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
425 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
426 (void)vm_setup_pptdev_msix(ctx, vcpu,
427 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
428 sc->psc_sel.pc_func, index, entry->addr,
429 entry->msg_data, entry->vector_control);
435 init_msix_table(struct vmctx *ctx, struct passthru_softc *sc, uint64_t base)
439 size_t len, remaining;
440 uint32_t table_size, table_offset;
441 uint32_t pba_size, pba_offset;
443 struct pci_devinst *pi = sc->psc_pi;
445 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
447 b = sc->psc_sel.pc_bus;
448 s = sc->psc_sel.pc_dev;
449 f = sc->psc_sel.pc_func;
452 * If the MSI-X table BAR maps memory intended for
453 * other uses, it is at least assured that the table
454 * either resides in its own page within the region,
455 * or it resides in a page shared with only the PBA.
457 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
459 table_size = pi->pi_msix.table_offset - table_offset;
460 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
461 table_size = roundup2(table_size, 4096);
463 idx = pi->pi_msix.table_bar;
464 start = pi->pi_bar[idx].addr;
465 remaining = pi->pi_bar[idx].size;
467 if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar) {
468 pba_offset = pi->pi_msix.pba_offset;
469 pba_size = pi->pi_msix.pba_size;
470 if (pba_offset >= table_offset + table_size ||
471 table_offset >= pba_offset + pba_size) {
473 * If the PBA does not share a page with the MSI-x
474 * tables, no PBA emulation is required.
476 pi->pi_msix.pba_page = NULL;
477 pi->pi_msix.pba_page_offset = 0;
480 * The PBA overlaps with either the first or last
481 * page of the MSI-X table region. Map the
484 if (pba_offset <= table_offset)
485 pi->pi_msix.pba_page_offset = table_offset;
487 pi->pi_msix.pba_page_offset = table_offset +
489 pi->pi_msix.pba_page = mmap(NULL, 4096, PROT_READ |
490 PROT_WRITE, MAP_SHARED, memfd, start +
491 pi->pi_msix.pba_page_offset);
492 if (pi->pi_msix.pba_page == MAP_FAILED) {
494 "Failed to map PBA page for MSI-X on %d/%d/%d",
501 /* Map everything before the MSI-X table */
502 if (table_offset > 0) {
504 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
513 /* Skip the MSI-X table */
516 remaining -= table_size;
518 /* Map everything beyond the end of the MSI-X table */
521 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
530 cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
533 struct pci_devinst *pi;
534 struct pci_bar_io bar;
535 enum pcibar_type bartype;
541 * Initialize BAR registers
543 for (i = 0; i <= PCI_BARMAX; i++) {
544 bzero(&bar, sizeof(bar));
545 bar.pbi_sel = sc->psc_sel;
546 bar.pbi_reg = PCIR_BAR(i);
548 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
551 if (PCI_BAR_IO(bar.pbi_base)) {
553 base = bar.pbi_base & PCIM_BAR_IO_BASE;
555 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
556 case PCIM_BAR_MEM_64:
557 bartype = PCIBAR_MEM64;
560 bartype = PCIBAR_MEM32;
563 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
565 size = bar.pbi_length;
567 if (bartype != PCIBAR_IO) {
568 if (((base | size) & PAGE_MASK) != 0) {
569 warnx("passthru device %d/%d/%d BAR %d: "
570 "base %#lx or size %#lx not page aligned\n",
571 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
572 sc->psc_sel.pc_func, i, base, size);
577 /* Cache information about the "real" BAR */
578 sc->psc_bar[i].type = bartype;
579 sc->psc_bar[i].size = size;
580 sc->psc_bar[i].addr = base;
582 /* Allocate the BAR in the guest I/O or MMIO space */
583 error = pci_emul_alloc_pbar(pi, i, base, bartype, size);
587 /* The MSI-X table needs special handling */
588 if (i == pci_msix_table_bar(pi)) {
589 error = init_msix_table(ctx, sc, base);
592 } else if (bartype != PCIBAR_IO) {
593 /* Map the physical BAR in the guest MMIO space */
594 error = vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
595 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
596 pi->pi_bar[i].addr, pi->pi_bar[i].size, base);
602 * 64-bit BAR takes up two slots so skip the next one.
604 if (bartype == PCIBAR_MEM64) {
606 assert(i <= PCI_BARMAX);
607 sc->psc_bar[i].type = PCIBAR_MEMHI64;
614 cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
617 struct passthru_softc *sc;
622 bzero(&sc->psc_sel, sizeof(struct pcisel));
623 sc->psc_sel.pc_bus = bus;
624 sc->psc_sel.pc_dev = slot;
625 sc->psc_sel.pc_func = func;
627 if (cfginitmsi(sc) != 0) {
628 warnx("failed to initialize MSI for PCI %d/%d/%d",
633 if (cfginitbar(ctx, sc) != 0) {
634 warnx("failed to initialize BARs for PCI %d/%d/%d",
639 error = 0; /* success */
645 passthru_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
647 int bus, slot, func, error, memflags;
648 struct passthru_softc *sc;
649 #ifndef WITHOUT_CAPSICUM
651 cap_ioctl_t pci_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR };
652 cap_ioctl_t io_ioctls[] = { IODEV_PIO };
658 #ifndef WITHOUT_CAPSICUM
659 cap_rights_init(&rights, CAP_IOCTL, CAP_READ, CAP_WRITE);
662 memflags = vm_get_memflags(ctx);
663 if (!(memflags & VM_MEM_F_WIRED)) {
664 warnx("passthru requires guest memory to be wired");
669 pcifd = open(_PATH_DEVPCI, O_RDWR, 0);
671 warn("failed to open %s", _PATH_DEVPCI);
676 #ifndef WITHOUT_CAPSICUM
677 if (cap_rights_limit(pcifd, &rights) == -1 && errno != ENOSYS)
678 errx(EX_OSERR, "Unable to apply rights for sandbox");
679 if (cap_ioctls_limit(pcifd, pci_ioctls, nitems(pci_ioctls)) == -1 && errno != ENOSYS)
680 errx(EX_OSERR, "Unable to apply rights for sandbox");
684 iofd = open(_PATH_DEVIO, O_RDWR, 0);
686 warn("failed to open %s", _PATH_DEVIO);
691 #ifndef WITHOUT_CAPSICUM
692 if (cap_rights_limit(iofd, &rights) == -1 && errno != ENOSYS)
693 errx(EX_OSERR, "Unable to apply rights for sandbox");
694 if (cap_ioctls_limit(iofd, io_ioctls, nitems(io_ioctls)) == -1 && errno != ENOSYS)
695 errx(EX_OSERR, "Unable to apply rights for sandbox");
699 memfd = open(_PATH_MEM, O_RDWR, 0);
701 warn("failed to open %s", _PATH_MEM);
706 #ifndef WITHOUT_CAPSICUM
707 cap_rights_clear(&rights, CAP_IOCTL);
708 cap_rights_set(&rights, CAP_MMAP_RW);
709 if (cap_rights_limit(memfd, &rights) == -1 && errno != ENOSYS)
710 errx(EX_OSERR, "Unable to apply rights for sandbox");
714 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) != 3) {
715 warnx("invalid passthru options");
719 if (vm_assign_pptdev(ctx, bus, slot, func) != 0) {
720 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
725 sc = calloc(1, sizeof(struct passthru_softc));
730 /* initialize config space */
731 if ((error = cfginit(ctx, pi, bus, slot, func)) != 0)
734 error = 0; /* success */
738 vm_unassign_pptdev(ctx, bus, slot, func);
746 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1))
753 msicap_access(struct passthru_softc *sc, int coff)
757 if (sc->psc_msi.capoff == 0)
760 caplen = msi_caplen(sc->psc_msi.msgctrl);
762 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
769 msixcap_access(struct passthru_softc *sc, int coff)
771 if (sc->psc_msix.capoff == 0)
774 return (coff >= sc->psc_msix.capoff &&
775 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
779 passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
780 int coff, int bytes, uint32_t *rv)
782 struct passthru_softc *sc;
787 * PCI BARs and MSI capability is emulated.
789 if (bar_access(coff) || msicap_access(sc, coff))
792 #ifdef LEGACY_SUPPORT
794 * Emulate PCIR_CAP_PTR if this device does not support MSI capability
797 if (sc->psc_msi.emulated) {
798 if (coff >= PCIR_CAP_PTR && coff < PCIR_CAP_PTR + 4)
803 /* Everything else just read from the device's config space */
804 *rv = read_config(&sc->psc_sel, coff, bytes);
810 passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
811 int coff, int bytes, uint32_t val)
813 int error, msix_table_entries, i;
814 struct passthru_softc *sc;
819 * PCI BARs are emulated
821 if (bar_access(coff))
825 * MSI capability is emulated
827 if (msicap_access(sc, coff)) {
828 msicap_cfgwrite(pi, sc->psc_msi.capoff, coff, bytes, val);
830 error = vm_setup_pptdev_msi(ctx, vcpu, sc->psc_sel.pc_bus,
831 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
832 pi->pi_msi.addr, pi->pi_msi.msg_data,
833 pi->pi_msi.maxmsgnum);
835 err(1, "vm_setup_pptdev_msi");
839 if (msixcap_access(sc, coff)) {
840 msixcap_cfgwrite(pi, sc->psc_msix.capoff, coff, bytes, val);
841 if (pi->pi_msix.enabled) {
842 msix_table_entries = pi->pi_msix.table_count;
843 for (i = 0; i < msix_table_entries; i++) {
844 error = vm_setup_pptdev_msix(ctx, vcpu,
845 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
846 sc->psc_sel.pc_func, i,
847 pi->pi_msix.table[i].addr,
848 pi->pi_msix.table[i].msg_data,
849 pi->pi_msix.table[i].vector_control);
852 err(1, "vm_setup_pptdev_msix");
858 #ifdef LEGACY_SUPPORT
860 * If this device does not support MSI natively then we cannot let
861 * the guest disable legacy interrupts from the device. It is the
862 * legacy interrupt that is triggering the virtual MSI to the guest.
864 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
865 if (coff == PCIR_COMMAND && bytes == 2)
866 val &= ~PCIM_CMD_INTxDIS;
870 write_config(&sc->psc_sel, coff, bytes, val);
876 passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
877 uint64_t offset, int size, uint64_t value)
879 struct passthru_softc *sc;
880 struct iodev_pio_req pio;
884 if (baridx == pci_msix_table_bar(pi)) {
885 msix_table_write(ctx, vcpu, sc, offset, size, value);
887 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
888 bzero(&pio, sizeof(struct iodev_pio_req));
889 pio.access = IODEV_PIO_WRITE;
890 pio.port = sc->psc_bar[baridx].addr + offset;
894 (void)ioctl(iofd, IODEV_PIO, &pio);
899 passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
900 uint64_t offset, int size)
902 struct passthru_softc *sc;
903 struct iodev_pio_req pio;
908 if (baridx == pci_msix_table_bar(pi)) {
909 val = msix_table_read(sc, offset, size);
911 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
912 bzero(&pio, sizeof(struct iodev_pio_req));
913 pio.access = IODEV_PIO_READ;
914 pio.port = sc->psc_bar[baridx].addr + offset;
918 (void)ioctl(iofd, IODEV_PIO, &pio);
926 struct pci_devemu passthru = {
927 .pe_emu = "passthru",
928 .pe_init = passthru_init,
929 .pe_cfgwrite = passthru_cfgwrite,
930 .pe_cfgread = passthru_cfgread,
931 .pe_barwrite = passthru_write,
932 .pe_barread = passthru_read,
934 PCI_EMUL_SET(passthru);