2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/types.h>
34 #include <sys/pciio.h>
35 #include <sys/ioctl.h>
37 #include <dev/io/iodev.h>
38 #include <machine/iodev.h>
47 #include <machine/vmm.h>
51 #include "instruction_emul.h"
54 #define _PATH_DEVPCI "/dev/pci"
58 #define _PATH_DEVIO "/dev/io"
61 #define LEGACY_SUPPORT 1
63 #define MSIX_TABLE_BIR_MASK 7
64 #define MSIX_TABLE_OFFSET_MASK (~MSIX_TABLE_BIR_MASK);
65 #define MSIX_TABLE_COUNT(x) (((x) & 0x7FF) + 1)
66 #define MSIX_CAPLEN 12
68 static int pcifd = -1;
71 struct passthru_softc {
72 struct pci_devinst *psc_pi;
73 struct pcibar psc_bar[PCI_BARMAX + 1];
82 struct pcisel psc_sel;
86 msi_caplen(int msgctrl)
90 len = 10; /* minimum length of msi capability */
92 if (msgctrl & PCIM_MSICTRL_64BIT)
97 * Ignore the 'mask' and 'pending' bits in the MSI capability.
98 * We'll let the guest manipulate them directly.
100 if (msgctrl & PCIM_MSICTRL_VECTOR)
108 read_config(const struct pcisel *sel, long reg, int width)
112 bzero(&pi, sizeof(pi));
117 if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
118 return (0); /* XXX */
124 write_config(const struct pcisel *sel, long reg, int width, uint32_t data)
128 bzero(&pi, sizeof(pi));
134 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
137 #ifdef LEGACY_SUPPORT
139 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
142 struct msicap msicap;
145 pci_populate_msicap(&msicap, msgnum, nextptr);
149 * Copy the msi capability structure in the last 16 bytes of the
150 * config space. This is wrong because it could shadow something
151 * useful to the device.
153 capoff = 256 - roundup(sizeof(msicap), 4);
154 capdata = (u_char *)&msicap;
155 for (i = 0; i < sizeof(msicap); i++)
156 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
160 #endif /* LEGACY_SUPPORT */
163 cfginitmsi(struct passthru_softc *sc)
165 int ptr, capptr, cap, sts, caplen;
168 struct pci_devinst *pi;
169 struct msixcap msixcap;
170 uint32_t *msixcap_ptr;
176 * Parse the capabilities and cache the location of the MSI
177 * and MSI-X capabilities.
179 sts = read_config(&sel, PCIR_STATUS, 2);
180 if (sts & PCIM_STATUS_CAPPRESENT) {
181 ptr = read_config(&sel, PCIR_CAP_PTR, 1);
182 while (ptr != 0 && ptr != 0xff) {
183 cap = read_config(&sel, ptr + PCICAP_ID, 1);
184 if (cap == PCIY_MSI) {
186 * Copy the MSI capability into the config
187 * space of the emulated pci device
189 sc->psc_msi.capoff = ptr;
190 sc->psc_msi.msgctrl = read_config(&sel,
192 sc->psc_msi.emulated = 0;
193 caplen = msi_caplen(sc->psc_msi.msgctrl);
196 u32 = read_config(&sel, capptr, 4);
197 pci_set_cfgdata32(pi, capptr, u32);
201 } else if (cap == PCIY_MSIX) {
203 * Copy the MSI-X capability
205 sc->psc_msix.capoff = ptr;
207 msixcap_ptr = (uint32_t*) &msixcap;
210 u32 = read_config(&sel, capptr, 4);
212 pci_set_cfgdata32(pi, capptr, u32);
218 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1);
222 if (sc->psc_msix.capoff != 0) {
223 pi->pi_msix.pba_bar =
224 msixcap.pba_offset & MSIX_TABLE_BIR_MASK;
225 pi->pi_msix.pba_offset =
226 msixcap.pba_offset & MSIX_TABLE_OFFSET_MASK;
227 pi->pi_msix.table_bar =
228 msixcap.table_offset & MSIX_TABLE_BIR_MASK;
229 pi->pi_msix.table_offset =
230 msixcap.table_offset & MSIX_TABLE_OFFSET_MASK;
231 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
234 #ifdef LEGACY_SUPPORT
236 * If the passthrough device does not support MSI then craft a
237 * MSI capability for it. We link the new MSI capability at the
238 * head of the list of capabilities.
240 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
242 origptr = read_config(&sel, PCIR_CAP_PTR, 1);
243 msiptr = passthru_add_msicap(pi, 1, origptr);
244 sc->psc_msi.capoff = msiptr;
245 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
246 sc->psc_msi.emulated = 1;
247 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
251 /* Make sure one of the capabilities is present */
252 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
259 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
261 struct pci_devinst *pi;
262 struct msix_table_entry *entry;
272 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
273 index = offset / MSIX_TABLE_ENTRY_SIZE;
274 entry = &pi->pi_msix.table[index];
278 src8 = (uint8_t *)((void *)entry + entry_offset);
282 src16 = (uint16_t *)((void *)entry + entry_offset);
286 src32 = (uint32_t *)((void *)entry + entry_offset);
290 src64 = (uint64_t *)((void *)entry + entry_offset);
301 msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc,
302 uint64_t offset, int size, uint64_t data)
304 struct pci_devinst *pi;
305 struct msix_table_entry *entry;
308 uint32_t vector_control;
312 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
313 index = offset / MSIX_TABLE_ENTRY_SIZE;
314 entry = &pi->pi_msix.table[index];
316 /* Only 4 byte naturally-aligned writes are supported */
318 assert(entry_offset % 4 == 0);
320 vector_control = entry->vector_control;
321 dest = (uint32_t *)((void *)entry + entry_offset);
323 /* If MSI-X hasn't been enabled, do nothing */
324 if (pi->pi_msix.enabled) {
325 /* If the entry is masked, don't set it up */
326 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
327 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
328 error = vm_setup_msix(ctx, vcpu, sc->psc_sel.pc_bus,
331 index, entry->msg_data,
332 entry->vector_control,
339 init_msix_table(struct vmctx *ctx, struct passthru_softc *sc, uint64_t base)
345 struct pci_devinst *pi = sc->psc_pi;
348 * If the MSI-X table BAR maps memory intended for
349 * other uses, it is at least assured that the table
350 * either resides in its own page within the region,
351 * or it resides in a page shared with only the PBA.
353 if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar &&
354 ((pi->pi_msix.pba_offset - pi->pi_msix.table_offset) < 4096)) {
355 /* Need to also emulate the PBA, not supported yet */
356 printf("Unsupported MSI-X table and PBA in same page\n");
361 * May need to split the BAR into 3 regions:
362 * Before the MSI-X table, the MSI-X table, and after it
363 * XXX for now, assume that the table is not in the middle
365 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
366 pi->pi_msix.table_size = table_size;
367 idx = pi->pi_msix.table_bar;
369 /* Round up to page size */
370 table_size = (table_size + 0x1000) & ~0xFFF;
371 if (pi->pi_msix.table_offset == 0) {
372 /* Map everything after the MSI-X table */
373 start = pi->pi_bar[idx].addr + table_size;
374 len = pi->pi_bar[idx].size - table_size;
376 /* Map everything before the MSI-X table */
377 start = pi->pi_bar[idx].addr;
378 len = pi->pi_msix.table_offset;
380 return (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
381 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
382 start, len, base + table_size));
386 cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
389 struct pci_devinst *pi;
390 struct pci_bar_io bar;
391 enum pcibar_type bartype;
397 * Initialize BAR registers
399 for (i = 0; i <= PCI_BARMAX; i++) {
400 bzero(&bar, sizeof(bar));
401 bar.pbi_sel = sc->psc_sel;
402 bar.pbi_reg = PCIR_BAR(i);
404 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
407 if (PCI_BAR_IO(bar.pbi_base)) {
409 base = bar.pbi_base & PCIM_BAR_IO_BASE;
411 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
412 case PCIM_BAR_MEM_64:
413 bartype = PCIBAR_MEM64;
416 bartype = PCIBAR_MEM32;
419 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
422 /* Cache information about the "real" BAR */
423 sc->psc_bar[i].type = bartype;
424 sc->psc_bar[i].size = bar.pbi_length;
425 sc->psc_bar[i].addr = base;
427 /* Allocate the BAR in the guest I/O or MMIO space */
428 error = pci_emul_alloc_pbar(pi, i, base, bartype,
433 /* The MSI-X table needs special handling */
434 if (i == pi->pi_msix.table_bar) {
435 error = init_msix_table(ctx, sc, base);
438 } else if (bartype != PCIBAR_IO) {
439 /* Map the physical MMIO space in the guest MMIO space */
440 error = vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
441 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
442 pi->pi_bar[i].addr, pi->pi_bar[i].size, base);
448 * 64-bit BAR takes up two slots so skip the next one.
450 if (bartype == PCIBAR_MEM64) {
452 assert(i <= PCI_BARMAX);
453 sc->psc_bar[i].type = PCIBAR_MEMHI64;
460 cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
463 struct passthru_softc *sc;
468 bzero(&sc->psc_sel, sizeof(struct pcisel));
469 sc->psc_sel.pc_bus = bus;
470 sc->psc_sel.pc_dev = slot;
471 sc->psc_sel.pc_func = func;
473 if (cfginitmsi(sc) != 0)
476 if (cfginitbar(ctx, sc) != 0)
479 error = 0; /* success */
485 passthru_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
487 int bus, slot, func, error;
488 struct passthru_softc *sc;
494 pcifd = open(_PATH_DEVPCI, O_RDWR, 0);
500 iofd = open(_PATH_DEVIO, O_RDWR, 0);
506 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) != 3)
509 if (vm_assign_pptdev(ctx, bus, slot, func) != 0)
512 sc = malloc(sizeof(struct passthru_softc));
513 memset(sc, 0, sizeof(struct passthru_softc));
518 /* initialize config space */
519 if ((error = cfginit(ctx, pi, bus, slot, func)) != 0)
522 error = 0; /* success */
526 vm_unassign_pptdev(ctx, bus, slot, func);
534 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1))
541 msicap_access(struct passthru_softc *sc, int coff)
545 if (sc->psc_msi.capoff == 0)
548 caplen = msi_caplen(sc->psc_msi.msgctrl);
550 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
557 msixcap_access(struct passthru_softc *sc, int coff)
559 if (sc->psc_msix.capoff == 0)
562 return (coff >= sc->psc_msix.capoff &&
563 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
567 passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
568 int coff, int bytes, uint32_t *rv)
570 struct passthru_softc *sc;
575 * PCI BARs and MSI capability is emulated.
577 if (bar_access(coff) || msicap_access(sc, coff))
580 #ifdef LEGACY_SUPPORT
582 * Emulate PCIR_CAP_PTR if this device does not support MSI capability
585 if (sc->psc_msi.emulated) {
586 if (coff >= PCIR_CAP_PTR && coff < PCIR_CAP_PTR + 4)
591 /* Everything else just read from the device's config space */
592 *rv = read_config(&sc->psc_sel, coff, bytes);
598 passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
599 int coff, int bytes, uint32_t val)
601 int error, msix_table_entries, i;
602 struct passthru_softc *sc;
607 * PCI BARs are emulated
609 if (bar_access(coff))
613 * MSI capability is emulated
615 if (msicap_access(sc, coff)) {
616 msicap_cfgwrite(pi, sc->psc_msi.capoff, coff, bytes, val);
618 error = vm_setup_msi(ctx, vcpu, sc->psc_sel.pc_bus,
619 sc->psc_sel.pc_dev, sc->psc_sel.pc_func, pi->pi_msi.cpu,
620 pi->pi_msi.vector, pi->pi_msi.msgnum);
622 printf("vm_setup_msi returned error %d\r\n", errno);
628 if (msixcap_access(sc, coff)) {
629 msixcap_cfgwrite(pi, sc->psc_msix.capoff, coff, bytes, val);
630 if (pi->pi_msix.enabled) {
631 msix_table_entries = pi->pi_msix.table_count;
632 for (i = 0; i < msix_table_entries; i++) {
633 error = vm_setup_msix(ctx, vcpu, sc->psc_sel.pc_bus,
635 sc->psc_sel.pc_func, i,
636 pi->pi_msix.table[i].msg_data,
637 pi->pi_msix.table[i].vector_control,
638 pi->pi_msix.table[i].addr);
641 printf("vm_setup_msix returned error %d\r\n", errno);
649 #ifdef LEGACY_SUPPORT
651 * If this device does not support MSI natively then we cannot let
652 * the guest disable legacy interrupts from the device. It is the
653 * legacy interrupt that is triggering the virtual MSI to the guest.
655 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
656 if (coff == PCIR_COMMAND && bytes == 2)
657 val &= ~PCIM_CMD_INTxDIS;
661 write_config(&sc->psc_sel, coff, bytes, val);
667 passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
668 uint64_t offset, int size, uint64_t value)
670 struct passthru_softc *sc;
671 struct iodev_pio_req pio;
675 if (pi->pi_msix.enabled && pi->pi_msix.table_bar == baridx) {
676 msix_table_write(ctx, vcpu, sc, offset, size, value);
678 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
679 bzero(&pio, sizeof(struct iodev_pio_req));
680 pio.access = IODEV_PIO_WRITE;
681 pio.port = sc->psc_bar[baridx].addr + offset;
685 (void)ioctl(iofd, IODEV_PIO, &pio);
690 passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
691 uint64_t offset, int size)
693 struct passthru_softc *sc;
694 struct iodev_pio_req pio;
699 if (pi->pi_msix.enabled && pi->pi_msix.table_bar == baridx) {
700 val = msix_table_read(sc, offset, size);
702 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
703 bzero(&pio, sizeof(struct iodev_pio_req));
704 pio.access = IODEV_PIO_READ;
705 pio.port = sc->psc_bar[baridx].addr + offset;
709 (void)ioctl(iofd, IODEV_PIO, &pio);
717 struct pci_devemu passthru = {
718 .pe_emu = "passthru",
719 .pe_init = passthru_init,
720 .pe_cfgwrite = passthru_cfgwrite,
721 .pe_cfgread = passthru_cfgread,
722 .pe_barwrite = passthru_write,
723 .pe_barread = passthru_read,
725 PCI_EMUL_SET(passthru);