2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #ifndef WITHOUT_CAPSICUM
34 #include <sys/capsicum.h>
36 #include <sys/types.h>
38 #include <sys/pciio.h>
39 #include <sys/ioctl.h>
41 #include <dev/io/iodev.h>
42 #include <dev/pci/pcireg.h>
44 #include <machine/iodev.h>
55 #include <machine/vmm.h>
61 #define _PATH_DEVPCI "/dev/pci"
65 #define _PATH_DEVIO "/dev/io"
69 #define _PATH_MEM "/dev/mem"
72 #define LEGACY_SUPPORT 1
74 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
75 #define MSIX_CAPLEN 12
77 static int pcifd = -1;
79 static int memfd = -1;
81 struct passthru_softc {
82 struct pci_devinst *psc_pi;
83 struct pcibar psc_bar[PCI_BARMAX + 1];
92 struct pcisel psc_sel;
96 msi_caplen(int msgctrl)
100 len = 10; /* minimum length of msi capability */
102 if (msgctrl & PCIM_MSICTRL_64BIT)
107 * Ignore the 'mask' and 'pending' bits in the MSI capability.
108 * We'll let the guest manipulate them directly.
110 if (msgctrl & PCIM_MSICTRL_VECTOR)
118 read_config(const struct pcisel *sel, long reg, int width)
122 bzero(&pi, sizeof(pi));
127 if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
128 return (0); /* XXX */
134 write_config(const struct pcisel *sel, long reg, int width, uint32_t data)
138 bzero(&pi, sizeof(pi));
144 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
147 #ifdef LEGACY_SUPPORT
149 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
152 struct msicap msicap;
155 pci_populate_msicap(&msicap, msgnum, nextptr);
159 * Copy the msi capability structure in the last 16 bytes of the
160 * config space. This is wrong because it could shadow something
161 * useful to the device.
163 capoff = 256 - roundup(sizeof(msicap), 4);
164 capdata = (u_char *)&msicap;
165 for (i = 0; i < sizeof(msicap); i++)
166 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
170 #endif /* LEGACY_SUPPORT */
173 cfginitmsi(struct passthru_softc *sc)
175 int i, ptr, capptr, cap, sts, caplen, table_size;
178 struct pci_devinst *pi;
179 struct msixcap msixcap;
180 uint32_t *msixcap_ptr;
186 * Parse the capabilities and cache the location of the MSI
187 * and MSI-X capabilities.
189 sts = read_config(&sel, PCIR_STATUS, 2);
190 if (sts & PCIM_STATUS_CAPPRESENT) {
191 ptr = read_config(&sel, PCIR_CAP_PTR, 1);
192 while (ptr != 0 && ptr != 0xff) {
193 cap = read_config(&sel, ptr + PCICAP_ID, 1);
194 if (cap == PCIY_MSI) {
196 * Copy the MSI capability into the config
197 * space of the emulated pci device
199 sc->psc_msi.capoff = ptr;
200 sc->psc_msi.msgctrl = read_config(&sel,
202 sc->psc_msi.emulated = 0;
203 caplen = msi_caplen(sc->psc_msi.msgctrl);
206 u32 = read_config(&sel, capptr, 4);
207 pci_set_cfgdata32(pi, capptr, u32);
211 } else if (cap == PCIY_MSIX) {
213 * Copy the MSI-X capability
215 sc->psc_msix.capoff = ptr;
217 msixcap_ptr = (uint32_t*) &msixcap;
220 u32 = read_config(&sel, capptr, 4);
222 pci_set_cfgdata32(pi, capptr, u32);
228 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1);
232 if (sc->psc_msix.capoff != 0) {
233 pi->pi_msix.pba_bar =
234 msixcap.pba_info & PCIM_MSIX_BIR_MASK;
235 pi->pi_msix.pba_offset =
236 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
237 pi->pi_msix.table_bar =
238 msixcap.table_info & PCIM_MSIX_BIR_MASK;
239 pi->pi_msix.table_offset =
240 msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
241 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
242 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
244 /* Allocate the emulated MSI-X table array */
245 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
246 pi->pi_msix.table = calloc(1, table_size);
248 /* Mask all table entries */
249 for (i = 0; i < pi->pi_msix.table_count; i++) {
250 pi->pi_msix.table[i].vector_control |=
251 PCIM_MSIX_VCTRL_MASK;
255 #ifdef LEGACY_SUPPORT
257 * If the passthrough device does not support MSI then craft a
258 * MSI capability for it. We link the new MSI capability at the
259 * head of the list of capabilities.
261 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
263 origptr = read_config(&sel, PCIR_CAP_PTR, 1);
264 msiptr = passthru_add_msicap(pi, 1, origptr);
265 sc->psc_msi.capoff = msiptr;
266 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
267 sc->psc_msi.emulated = 1;
268 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
272 /* Make sure one of the capabilities is present */
273 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
280 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
282 struct pci_devinst *pi;
283 struct msix_table_entry *entry;
293 if (offset >= pi->pi_msix.pba_offset &&
294 offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
297 src8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
298 pi->pi_msix.pba_page_offset);
302 src16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
303 pi->pi_msix.pba_page_offset);
307 src32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
308 pi->pi_msix.pba_page_offset);
312 src64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
313 pi->pi_msix.pba_page_offset);
322 if (offset < pi->pi_msix.table_offset)
325 offset -= pi->pi_msix.table_offset;
326 index = offset / MSIX_TABLE_ENTRY_SIZE;
327 if (index >= pi->pi_msix.table_count)
330 entry = &pi->pi_msix.table[index];
331 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
335 src8 = (uint8_t *)((void *)entry + entry_offset);
339 src16 = (uint16_t *)((void *)entry + entry_offset);
343 src32 = (uint32_t *)((void *)entry + entry_offset);
347 src64 = (uint64_t *)((void *)entry + entry_offset);
358 msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc,
359 uint64_t offset, int size, uint64_t data)
361 struct pci_devinst *pi;
362 struct msix_table_entry *entry;
368 uint32_t vector_control;
372 if (offset >= pi->pi_msix.pba_offset &&
373 offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
376 dest8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
377 pi->pi_msix.pba_page_offset);
381 dest16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
382 pi->pi_msix.pba_page_offset);
386 dest32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
387 pi->pi_msix.pba_page_offset);
391 dest64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
392 pi->pi_msix.pba_page_offset);
401 if (offset < pi->pi_msix.table_offset)
404 offset -= pi->pi_msix.table_offset;
405 index = offset / MSIX_TABLE_ENTRY_SIZE;
406 if (index >= pi->pi_msix.table_count)
409 entry = &pi->pi_msix.table[index];
410 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
412 /* Only 4 byte naturally-aligned writes are supported */
414 assert(entry_offset % 4 == 0);
416 vector_control = entry->vector_control;
417 dest32 = (uint32_t *)((void *)entry + entry_offset);
419 /* If MSI-X hasn't been enabled, do nothing */
420 if (pi->pi_msix.enabled) {
421 /* If the entry is masked, don't set it up */
422 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
423 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
424 (void)vm_setup_pptdev_msix(ctx, vcpu,
425 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
426 sc->psc_sel.pc_func, index, entry->addr,
427 entry->msg_data, entry->vector_control);
433 init_msix_table(struct vmctx *ctx, struct passthru_softc *sc, uint64_t base)
437 size_t len, remaining;
438 uint32_t table_size, table_offset;
439 uint32_t pba_size, pba_offset;
441 struct pci_devinst *pi = sc->psc_pi;
443 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
445 b = sc->psc_sel.pc_bus;
446 s = sc->psc_sel.pc_dev;
447 f = sc->psc_sel.pc_func;
450 * If the MSI-X table BAR maps memory intended for
451 * other uses, it is at least assured that the table
452 * either resides in its own page within the region,
453 * or it resides in a page shared with only the PBA.
455 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
457 table_size = pi->pi_msix.table_offset - table_offset;
458 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
459 table_size = roundup2(table_size, 4096);
461 idx = pi->pi_msix.table_bar;
462 start = pi->pi_bar[idx].addr;
463 remaining = pi->pi_bar[idx].size;
465 if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar) {
466 pba_offset = pi->pi_msix.pba_offset;
467 pba_size = pi->pi_msix.pba_size;
468 if (pba_offset >= table_offset + table_size ||
469 table_offset >= pba_offset + pba_size) {
471 * If the PBA does not share a page with the MSI-x
472 * tables, no PBA emulation is required.
474 pi->pi_msix.pba_page = NULL;
475 pi->pi_msix.pba_page_offset = 0;
478 * The PBA overlaps with either the first or last
479 * page of the MSI-X table region. Map the
482 if (pba_offset <= table_offset)
483 pi->pi_msix.pba_page_offset = table_offset;
485 pi->pi_msix.pba_page_offset = table_offset +
487 pi->pi_msix.pba_page = mmap(NULL, 4096, PROT_READ |
488 PROT_WRITE, MAP_SHARED, memfd, start +
489 pi->pi_msix.pba_page_offset);
490 if (pi->pi_msix.pba_page == MAP_FAILED) {
492 "Failed to map PBA page for MSI-X on %d/%d/%d",
499 /* Map everything before the MSI-X table */
500 if (table_offset > 0) {
502 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
511 /* Skip the MSI-X table */
514 remaining -= table_size;
516 /* Map everything beyond the end of the MSI-X table */
519 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
528 cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
531 struct pci_devinst *pi;
532 struct pci_bar_io bar;
533 enum pcibar_type bartype;
539 * Initialize BAR registers
541 for (i = 0; i <= PCI_BARMAX; i++) {
542 bzero(&bar, sizeof(bar));
543 bar.pbi_sel = sc->psc_sel;
544 bar.pbi_reg = PCIR_BAR(i);
546 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
549 if (PCI_BAR_IO(bar.pbi_base)) {
551 base = bar.pbi_base & PCIM_BAR_IO_BASE;
553 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
554 case PCIM_BAR_MEM_64:
555 bartype = PCIBAR_MEM64;
558 bartype = PCIBAR_MEM32;
561 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
563 size = bar.pbi_length;
565 if (bartype != PCIBAR_IO) {
566 if (((base | size) & PAGE_MASK) != 0) {
567 warnx("passthru device %d/%d/%d BAR %d: "
568 "base %#lx or size %#lx not page aligned\n",
569 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
570 sc->psc_sel.pc_func, i, base, size);
575 /* Cache information about the "real" BAR */
576 sc->psc_bar[i].type = bartype;
577 sc->psc_bar[i].size = size;
578 sc->psc_bar[i].addr = base;
580 /* Allocate the BAR in the guest I/O or MMIO space */
581 error = pci_emul_alloc_pbar(pi, i, base, bartype, size);
585 /* The MSI-X table needs special handling */
586 if (i == pci_msix_table_bar(pi)) {
587 error = init_msix_table(ctx, sc, base);
590 } else if (bartype != PCIBAR_IO) {
591 /* Map the physical BAR in the guest MMIO space */
592 error = vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
593 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
594 pi->pi_bar[i].addr, pi->pi_bar[i].size, base);
600 * 64-bit BAR takes up two slots so skip the next one.
602 if (bartype == PCIBAR_MEM64) {
604 assert(i <= PCI_BARMAX);
605 sc->psc_bar[i].type = PCIBAR_MEMHI64;
612 cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
615 struct passthru_softc *sc;
620 bzero(&sc->psc_sel, sizeof(struct pcisel));
621 sc->psc_sel.pc_bus = bus;
622 sc->psc_sel.pc_dev = slot;
623 sc->psc_sel.pc_func = func;
625 if (cfginitmsi(sc) != 0) {
626 warnx("failed to initialize MSI for PCI %d/%d/%d",
631 if (cfginitbar(ctx, sc) != 0) {
632 warnx("failed to initialize BARs for PCI %d/%d/%d",
637 error = 0; /* success */
643 passthru_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
645 int bus, slot, func, error, memflags;
646 struct passthru_softc *sc;
647 #ifndef WITHOUT_CAPSICUM
649 cap_ioctl_t pci_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR };
650 cap_ioctl_t io_ioctls[] = { IODEV_PIO };
656 #ifndef WITHOUT_CAPSICUM
657 cap_rights_init(&rights, CAP_IOCTL, CAP_READ, CAP_WRITE);
660 memflags = vm_get_memflags(ctx);
661 if (!(memflags & VM_MEM_F_WIRED)) {
662 warnx("passthru requires guest memory to be wired");
667 pcifd = open(_PATH_DEVPCI, O_RDWR, 0);
669 warn("failed to open %s", _PATH_DEVPCI);
674 #ifndef WITHOUT_CAPSICUM
675 if (cap_rights_limit(pcifd, &rights) == -1 && errno != ENOSYS)
676 errx(EX_OSERR, "Unable to apply rights for sandbox");
677 if (cap_ioctls_limit(pcifd, pci_ioctls, nitems(pci_ioctls)) == -1 && errno != ENOSYS)
678 errx(EX_OSERR, "Unable to apply rights for sandbox");
682 iofd = open(_PATH_DEVIO, O_RDWR, 0);
684 warn("failed to open %s", _PATH_DEVIO);
689 #ifndef WITHOUT_CAPSICUM
690 if (cap_rights_limit(iofd, &rights) == -1 && errno != ENOSYS)
691 errx(EX_OSERR, "Unable to apply rights for sandbox");
692 if (cap_ioctls_limit(iofd, io_ioctls, nitems(io_ioctls)) == -1 && errno != ENOSYS)
693 errx(EX_OSERR, "Unable to apply rights for sandbox");
697 memfd = open(_PATH_MEM, O_RDWR, 0);
699 warn("failed to open %s", _PATH_MEM);
704 #ifndef WITHOUT_CAPSICUM
705 cap_rights_clear(&rights, CAP_IOCTL);
706 cap_rights_set(&rights, CAP_MMAP_RW);
707 if (cap_rights_limit(memfd, &rights) == -1 && errno != ENOSYS)
708 errx(EX_OSERR, "Unable to apply rights for sandbox");
712 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) != 3) {
713 warnx("invalid passthru options");
717 if (vm_assign_pptdev(ctx, bus, slot, func) != 0) {
718 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
723 sc = calloc(1, sizeof(struct passthru_softc));
728 /* initialize config space */
729 if ((error = cfginit(ctx, pi, bus, slot, func)) != 0)
732 error = 0; /* success */
736 vm_unassign_pptdev(ctx, bus, slot, func);
744 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1))
751 msicap_access(struct passthru_softc *sc, int coff)
755 if (sc->psc_msi.capoff == 0)
758 caplen = msi_caplen(sc->psc_msi.msgctrl);
760 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
767 msixcap_access(struct passthru_softc *sc, int coff)
769 if (sc->psc_msix.capoff == 0)
772 return (coff >= sc->psc_msix.capoff &&
773 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
777 passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
778 int coff, int bytes, uint32_t *rv)
780 struct passthru_softc *sc;
785 * PCI BARs and MSI capability is emulated.
787 if (bar_access(coff) || msicap_access(sc, coff))
790 #ifdef LEGACY_SUPPORT
792 * Emulate PCIR_CAP_PTR if this device does not support MSI capability
795 if (sc->psc_msi.emulated) {
796 if (coff >= PCIR_CAP_PTR && coff < PCIR_CAP_PTR + 4)
801 /* Everything else just read from the device's config space */
802 *rv = read_config(&sc->psc_sel, coff, bytes);
808 passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
809 int coff, int bytes, uint32_t val)
811 int error, msix_table_entries, i;
812 struct passthru_softc *sc;
817 * PCI BARs are emulated
819 if (bar_access(coff))
823 * MSI capability is emulated
825 if (msicap_access(sc, coff)) {
826 msicap_cfgwrite(pi, sc->psc_msi.capoff, coff, bytes, val);
828 error = vm_setup_pptdev_msi(ctx, vcpu, sc->psc_sel.pc_bus,
829 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
830 pi->pi_msi.addr, pi->pi_msi.msg_data,
831 pi->pi_msi.maxmsgnum);
833 err(1, "vm_setup_pptdev_msi");
837 if (msixcap_access(sc, coff)) {
838 msixcap_cfgwrite(pi, sc->psc_msix.capoff, coff, bytes, val);
839 if (pi->pi_msix.enabled) {
840 msix_table_entries = pi->pi_msix.table_count;
841 for (i = 0; i < msix_table_entries; i++) {
842 error = vm_setup_pptdev_msix(ctx, vcpu,
843 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
844 sc->psc_sel.pc_func, i,
845 pi->pi_msix.table[i].addr,
846 pi->pi_msix.table[i].msg_data,
847 pi->pi_msix.table[i].vector_control);
850 err(1, "vm_setup_pptdev_msix");
856 #ifdef LEGACY_SUPPORT
858 * If this device does not support MSI natively then we cannot let
859 * the guest disable legacy interrupts from the device. It is the
860 * legacy interrupt that is triggering the virtual MSI to the guest.
862 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
863 if (coff == PCIR_COMMAND && bytes == 2)
864 val &= ~PCIM_CMD_INTxDIS;
868 write_config(&sc->psc_sel, coff, bytes, val);
874 passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
875 uint64_t offset, int size, uint64_t value)
877 struct passthru_softc *sc;
878 struct iodev_pio_req pio;
882 if (baridx == pci_msix_table_bar(pi)) {
883 msix_table_write(ctx, vcpu, sc, offset, size, value);
885 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
886 bzero(&pio, sizeof(struct iodev_pio_req));
887 pio.access = IODEV_PIO_WRITE;
888 pio.port = sc->psc_bar[baridx].addr + offset;
892 (void)ioctl(iofd, IODEV_PIO, &pio);
897 passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
898 uint64_t offset, int size)
900 struct passthru_softc *sc;
901 struct iodev_pio_req pio;
906 if (baridx == pci_msix_table_bar(pi)) {
907 val = msix_table_read(sc, offset, size);
909 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
910 bzero(&pio, sizeof(struct iodev_pio_req));
911 pio.access = IODEV_PIO_READ;
912 pio.port = sc->psc_bar[baridx].addr + offset;
916 (void)ioctl(iofd, IODEV_PIO, &pio);
924 struct pci_devemu passthru = {
925 .pe_emu = "passthru",
926 .pe_init = passthru_init,
927 .pe_cfgwrite = passthru_cfgwrite,
928 .pe_cfgread = passthru_cfgread,
929 .pe_barwrite = passthru_write,
930 .pe_barread = passthru_read,
932 PCI_EMUL_SET(passthru);