2 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define PCI_USBREV 0x60 /* USB protocol revision */
35 enum { /* dsc_slotstate */
45 XHCI_ST_SLCTX_DISABLED,
46 XHCI_ST_SLCTX_DEFAULT,
47 XHCI_ST_SLCTX_ADDRESSED,
48 XHCI_ST_SLCTX_CONFIGURED
52 XHCI_ST_EPCTX_DISABLED,
53 XHCI_ST_EPCTX_RUNNING,
55 XHCI_ST_EPCTX_STOPPED,
59 #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128)
60 #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */
61 #define XHCI_MAX_SCRATCHPADS 32
62 #define XHCI_MAX_EVENTS (16 * 13)
63 #define XHCI_MAX_COMMANDS (16 * 1)
64 #define XHCI_MAX_RSEG 1
65 #define XHCI_MAX_TRANSFERS 4
66 #if USB_MAX_EP_STREAMS == 8
67 #define XHCI_MAX_STREAMS 8
68 #define XHCI_MAX_STREAMS_LOG 3
69 #elif USB_MAX_EP_STREAMS == 1
70 #define XHCI_MAX_STREAMS 1
71 #define XHCI_MAX_STREAMS_LOG 0
73 #error "The USB_MAX_EP_STREAMS value is not supported."
75 #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */
76 #define XHCI_DEV_CTX_ALIGN 64 /* bytes */
77 #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */
78 #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */
79 #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */
80 #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */
81 #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */
82 #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */
83 #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */
84 #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */
85 #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE
86 #define XHCI_TRB_ALIGN 16 /* bytes */
87 #define XHCI_TD_ALIGN 64 /* bytes */
88 #define XHCI_PAGE_SIZE 4096 /* bytes */
90 struct xhci_slot_ctx {
91 volatile uint32_t dwSctx0;
92 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
93 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF)
94 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20)
95 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF)
96 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25)
97 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1)
98 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26)
99 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1)
100 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27)
101 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F)
102 volatile uint32_t dwSctx1;
103 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF)
104 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF)
105 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16)
106 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF)
107 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24)
108 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF)
109 volatile uint32_t dwSctx2;
110 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF)
111 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF)
112 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8)
113 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF)
114 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16)
115 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3)
116 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22)
117 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF)
118 volatile uint32_t dwSctx3;
119 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF)
120 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF)
121 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27)
122 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F)
123 volatile uint32_t dwSctx4;
124 volatile uint32_t dwSctx5;
125 volatile uint32_t dwSctx6;
126 volatile uint32_t dwSctx7;
129 struct xhci_endp_ctx {
130 volatile uint32_t dwEpCtx0;
131 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7)
132 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7)
133 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8)
134 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3)
135 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10)
136 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F)
137 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15)
138 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1)
139 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16)
140 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF)
141 volatile uint32_t dwEpCtx1;
142 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1)
143 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3)
144 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3)
145 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7)
146 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7)
147 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1)
148 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8)
149 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF)
150 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16)
151 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF)
152 volatile uint64_t qwEpCtx2;
153 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1)
154 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1)
155 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
156 volatile uint32_t dwEpCtx4;
157 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF)
158 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF)
159 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16)
160 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF)
161 volatile uint32_t dwEpCtx5;
162 volatile uint32_t dwEpCtx6;
163 volatile uint32_t dwEpCtx7;
166 struct xhci_input_ctx {
167 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU
168 volatile uint32_t dwInCtx0;
169 #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n))
170 volatile uint32_t dwInCtx1;
171 #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n))
172 volatile uint32_t dwInCtx2;
173 volatile uint32_t dwInCtx3;
174 volatile uint32_t dwInCtx4;
175 volatile uint32_t dwInCtx5;
176 volatile uint32_t dwInCtx6;
177 volatile uint32_t dwInCtx7;
180 struct xhci_input_dev_ctx {
181 struct xhci_input_ctx ctx_input;
183 struct xhci_slot_ctx u_slot;
184 struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS];
188 struct xhci_dev_ctx {
190 struct xhci_slot_ctx u_slot;
191 struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS];
193 } __aligned(XHCI_DEV_CTX_ALIGN);
194 #define ctx_slot ctx_dev_slep.u_slot
195 #define ctx_ep ctx_dev_slep.u_ep
197 struct xhci_stream_ctx {
198 volatile uint64_t qwSctx0;
199 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1)
200 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1)
201 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1)
202 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7)
203 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0
204 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1
205 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2
206 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3
207 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4
208 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5
209 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6
210 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7
211 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
212 volatile uint32_t dwSctx2;
213 volatile uint32_t dwSctx3;
217 volatile uint64_t qwTrb0;
218 #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0)
219 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48)
220 volatile uint32_t dwTrb2;
221 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF)
222 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24)
223 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F)
224 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17)
225 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF)
226 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF)
227 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF)
228 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF)
229 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF)
230 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22)
231 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF)
232 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16)
234 volatile uint32_t dwTrb3;
235 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F)
236 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10)
237 #define XHCI_TRB_3_CYCLE_BIT (1U << 0)
238 #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */
239 #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */
240 #define XHCI_TRB_3_ISP_BIT (1U << 2)
241 #define XHCI_TRB_3_ED_BIT (1U << 2)
242 #define XHCI_TRB_3_NSNOOP_BIT (1U << 3)
243 #define XHCI_TRB_3_CHAIN_BIT (1U << 4)
244 #define XHCI_TRB_3_IOC_BIT (1U << 5)
245 #define XHCI_TRB_3_IDT_BIT (1U << 6)
246 #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3)
247 #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7)
248 #define XHCI_TRB_3_BEI_BIT (1U << 9)
249 #define XHCI_TRB_3_DCEP_BIT (1U << 9)
250 #define XHCI_TRB_3_PRSV_BIT (1U << 9)
251 #define XHCI_TRB_3_BSR_BIT (1U << 9)
252 #define XHCI_TRB_3_TRT_MASK (3U << 16)
253 #define XHCI_TRB_3_TRT_NONE (0U << 16)
254 #define XHCI_TRB_3_TRT_OUT (2U << 16)
255 #define XHCI_TRB_3_TRT_IN (3U << 16)
256 #define XHCI_TRB_3_DIR_IN (1U << 16)
257 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF)
258 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16)
259 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F)
260 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16)
261 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF)
262 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20)
263 #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31)
264 #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23)
265 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF)
266 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24)
269 #define XHCI_TRB_TYPE_RESERVED 0x00
270 #define XHCI_TRB_TYPE_NORMAL 0x01
271 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02
272 #define XHCI_TRB_TYPE_DATA_STAGE 0x03
273 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04
274 #define XHCI_TRB_TYPE_ISOCH 0x05
275 #define XHCI_TRB_TYPE_LINK 0x06
276 #define XHCI_TRB_TYPE_EVENT_DATA 0x07
277 #define XHCI_TRB_TYPE_NOOP 0x08
278 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09
279 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A
280 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B
281 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C
282 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D
283 #define XHCI_TRB_TYPE_RESET_EP 0x0E
284 #define XHCI_TRB_TYPE_STOP_EP 0x0F
285 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10
286 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11
287 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12
288 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13
289 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14
290 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15
291 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16
292 #define XHCI_TRB_TYPE_NOOP_CMD 0x17
295 #define XHCI_TRB_EVENT_TRANSFER 0x20
296 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21
297 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22
298 #define XHCI_TRB_EVENT_BW_REQUEST 0x23
299 #define XHCI_TRB_EVENT_DOORBELL 0x24
300 #define XHCI_TRB_EVENT_HOST_CTRL 0x25
301 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26
302 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27
305 #define XHCI_TRB_ERROR_INVALID 0x00
306 #define XHCI_TRB_ERROR_SUCCESS 0x01
307 #define XHCI_TRB_ERROR_DATA_BUF 0x02
308 #define XHCI_TRB_ERROR_BABBLE 0x03
309 #define XHCI_TRB_ERROR_XACT 0x04
310 #define XHCI_TRB_ERROR_TRB 0x05
311 #define XHCI_TRB_ERROR_STALL 0x06
312 #define XHCI_TRB_ERROR_RESOURCE 0x07
313 #define XHCI_TRB_ERROR_BANDWIDTH 0x08
314 #define XHCI_TRB_ERROR_NO_SLOTS 0x09
315 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A
316 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B
317 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C
318 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D
319 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E
320 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F
321 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10
322 #define XHCI_TRB_ERROR_PARAMETER 0x11
323 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12
324 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13
325 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14
326 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15
327 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16
328 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17
329 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18
330 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19
331 #define XHCI_TRB_ERROR_STOPPED 0x1A
332 #define XHCI_TRB_ERROR_LENGTH 0x1B
333 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D
334 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F
335 #define XHCI_TRB_ERROR_EVENT_LOST 0x20
336 #define XHCI_TRB_ERROR_UNDEFINED 0x21
337 #define XHCI_TRB_ERROR_INVALID_SID 0x22
338 #define XHCI_TRB_ERROR_SEC_BW 0x23
339 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24
342 struct xhci_dev_endpoint_trbs {
343 struct xhci_trb trb[(XHCI_MAX_STREAMS *
344 XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS];
347 struct xhci_event_ring_seg {
348 volatile uint64_t qwEvrsTablePtr;
349 volatile uint32_t dwEvrsTableSize;
350 volatile uint32_t dwEvrsReserved;
353 #endif /* _PCI_XHCI_H_ */