2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Hudson River Trading LLC
5 * Written by: John H. Baldwin <jhb@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <machine/vmm.h>
48 static pthread_mutex_t pm_lock = PTHREAD_MUTEX_INITIALIZER;
49 static struct mevent *power_button;
50 static sig_t old_power_handler;
52 static unsigned gpe0_active;
53 static unsigned gpe0_enabled;
54 static const unsigned gpe0_valid = (1u << GPE_VMGENC);
57 * Reset Control register at I/O port 0xcf9. Bit 2 forces a system
58 * reset when it transitions from 0 to 1. Bit 1 selects the type of
59 * reset to attempt: 0 selects a "soft" reset, and 1 selects a "hard"
63 reset_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
64 uint32_t *eax, void *arg)
68 static uint8_t reset_control;
77 /* Treat hard and soft resets the same. */
78 if (reset_control & 0x4) {
79 error = vm_suspend(ctx, VM_SUSPEND_RESET);
80 assert(error == 0 || errno == EALREADY);
85 INOUT_PORT(reset_reg, 0xCF9, IOPORT_F_INOUT, reset_handler);
88 * ACPI's SCI is a level-triggered interrupt.
90 static int sci_active;
93 sci_assert(struct vmctx *ctx)
98 vm_isa_assert_irq(ctx, SCI_INT, SCI_INT);
103 sci_deassert(struct vmctx *ctx)
108 vm_isa_deassert_irq(ctx, SCI_INT, SCI_INT);
113 * Power Management 1 Event Registers
115 * The only power management event supported is a power button upon
118 static uint16_t pm1_enable, pm1_status;
120 #define PM1_TMR_STS 0x0001
121 #define PM1_BM_STS 0x0010
122 #define PM1_GBL_STS 0x0020
123 #define PM1_PWRBTN_STS 0x0100
124 #define PM1_SLPBTN_STS 0x0200
125 #define PM1_RTC_STS 0x0400
126 #define PM1_WAK_STS 0x8000
128 #define PM1_TMR_EN 0x0001
129 #define PM1_GBL_EN 0x0020
130 #define PM1_PWRBTN_EN 0x0100
131 #define PM1_SLPBTN_EN 0x0200
132 #define PM1_RTC_EN 0x0400
135 sci_update(struct vmctx *ctx)
139 /* See if the SCI should be active or not. */
141 if ((pm1_enable & PM1_TMR_EN) && (pm1_status & PM1_TMR_STS))
143 if ((pm1_enable & PM1_GBL_EN) && (pm1_status & PM1_GBL_STS))
145 if ((pm1_enable & PM1_PWRBTN_EN) && (pm1_status & PM1_PWRBTN_STS))
147 if ((pm1_enable & PM1_SLPBTN_EN) && (pm1_status & PM1_SLPBTN_STS))
149 if ((pm1_enable & PM1_RTC_EN) && (pm1_status & PM1_RTC_STS))
151 if ((gpe0_enabled & gpe0_active) != 0)
161 pm1_status_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
162 uint32_t *eax, void *arg)
168 pthread_mutex_lock(&pm_lock);
173 * Writes are only permitted to clear certain bits by
174 * writing 1 to those flags.
176 pm1_status &= ~(*eax & (PM1_WAK_STS | PM1_RTC_STS |
177 PM1_SLPBTN_STS | PM1_PWRBTN_STS | PM1_BM_STS));
180 pthread_mutex_unlock(&pm_lock);
185 pm1_enable_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
186 uint32_t *eax, void *arg)
192 pthread_mutex_lock(&pm_lock);
197 * Only permit certain bits to be set. We never use
198 * the global lock, but ACPI-CA whines profusely if it
201 pm1_enable = *eax & (PM1_RTC_EN | PM1_PWRBTN_EN | PM1_GBL_EN);
204 pthread_mutex_unlock(&pm_lock);
207 INOUT_PORT(pm1_status, PM1A_EVT_ADDR, IOPORT_F_INOUT, pm1_status_handler);
208 INOUT_PORT(pm1_enable, PM1A_EVT_ADDR + 2, IOPORT_F_INOUT, pm1_enable_handler);
211 power_button_handler(int signal, enum ev_type type, void *arg)
216 pthread_mutex_lock(&pm_lock);
217 if (!(pm1_status & PM1_PWRBTN_STS)) {
218 pm1_status |= PM1_PWRBTN_STS;
221 pthread_mutex_unlock(&pm_lock);
225 * Power Management 1 Control Register
227 * This is mostly unimplemented except that we wish to handle writes that
228 * set SPL_EN to handle S5 (soft power off).
230 static uint16_t pm1_control;
232 #define PM1_SCI_EN 0x0001
233 #define PM1_SLP_TYP 0x1c00
234 #define PM1_SLP_EN 0x2000
235 #define PM1_ALWAYS_ZERO 0xc003
238 pm1_control_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
239 uint32_t *eax, void *arg)
249 * Various bits are write-only or reserved, so force them
250 * to zero in pm1_control. Always preserve SCI_EN as OSPM
251 * can never change it.
253 pm1_control = (pm1_control & PM1_SCI_EN) |
254 (*eax & ~(PM1_SLP_EN | PM1_ALWAYS_ZERO));
257 * If SLP_EN is set, check for S5. Bhyve's _S5_ method
258 * says that '5' should be stored in SLP_TYP for S5.
260 if (*eax & PM1_SLP_EN) {
261 if ((pm1_control & PM1_SLP_TYP) >> 10 == 5) {
262 error = vm_suspend(ctx, VM_SUSPEND_POWEROFF);
263 assert(error == 0 || errno == EALREADY);
269 INOUT_PORT(pm1_control, PM1A_CNT_ADDR, IOPORT_F_INOUT, pm1_control_handler);
270 SYSRES_IO(PM1A_EVT_ADDR, 8);
273 acpi_raise_gpe(struct vmctx *ctx, unsigned bit)
277 assert(bit < (IO_GPE0_LEN * (8 / 2)));
279 assert((mask & ~gpe0_valid) == 0);
281 pthread_mutex_lock(&pm_lock);
284 pthread_mutex_unlock(&pm_lock);
288 gpe0_sts(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
289 uint32_t *eax, void *arg)
292 * ACPI 6.2 specifies the GPE register blocks are accessed
298 pthread_mutex_lock(&pm_lock);
303 gpe0_active &= ~(*eax & gpe0_valid);
306 pthread_mutex_unlock(&pm_lock);
309 INOUT_PORT(gpe0_sts, IO_GPE0_STS, IOPORT_F_INOUT, gpe0_sts);
312 gpe0_en(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
313 uint32_t *eax, void *arg)
318 pthread_mutex_lock(&pm_lock);
322 gpe0_enabled = (*eax & gpe0_valid);
325 pthread_mutex_unlock(&pm_lock);
328 INOUT_PORT(gpe0_en, IO_GPE0_EN, IOPORT_F_INOUT, gpe0_en);
331 * ACPI SMI Command Register
333 * This write-only register is used to enable and disable ACPI.
336 smi_cmd_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
337 uint32_t *eax, void *arg)
344 pthread_mutex_lock(&pm_lock);
346 case BHYVE_ACPI_ENABLE:
347 pm1_control |= PM1_SCI_EN;
348 if (power_button == NULL) {
349 power_button = mevent_add(SIGTERM, EVF_SIGNAL,
350 power_button_handler, ctx);
351 old_power_handler = signal(SIGTERM, SIG_IGN);
354 case BHYVE_ACPI_DISABLE:
355 pm1_control &= ~PM1_SCI_EN;
356 if (power_button != NULL) {
357 mevent_delete(power_button);
359 signal(SIGTERM, old_power_handler);
363 pthread_mutex_unlock(&pm_lock);
366 INOUT_PORT(smi_cmd, SMI_CMD, IOPORT_F_OUT, smi_cmd_handler);
367 SYSRES_IO(SMI_CMD, 1);
370 sci_init(struct vmctx *ctx)
374 * Mark ACPI's SCI as level trigger and bump its use count
375 * in the PIRQ router.
377 pci_irq_use(SCI_INT);
378 vm_isa_set_irq_trigger(ctx, SCI_INT, LEVEL_TRIGGER);