2 * Copyright (c) 2014 Neel Natu <neel@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/_iovec.h>
35 #include <x86/segments.h>
36 #include <x86/specialreg.h>
37 #include <machine/vmm.h>
38 #include <machine/vmm_instruction_emul.h>
51 * Using 'struct i386tss' is tempting but causes myriad sign extension
52 * issues because all of its fields are defined as signed integers.
94 CTASSERT(sizeof(struct tss32) == 104);
96 #define SEL_START(sel) (((sel) & ~0x7))
97 #define SEL_LIMIT(sel) (((sel) | 0x7))
98 #define TSS_BUSY(type) (((type) & 0x2) != 0)
101 GETREG(struct vmctx *ctx, int vcpu, int reg)
106 error = vm_get_register(ctx, vcpu, reg, &val);
112 SETREG(struct vmctx *ctx, int vcpu, int reg, uint64_t val)
116 error = vm_set_register(ctx, vcpu, reg, val);
120 static struct seg_desc
121 usd_to_seg_desc(struct user_segment_descriptor *usd)
123 struct seg_desc seg_desc;
125 seg_desc.base = (u_int)USD_GETBASE(usd);
127 seg_desc.limit = (u_int)(USD_GETLIMIT(usd) << 12) | 0xfff;
129 seg_desc.limit = (u_int)USD_GETLIMIT(usd);
130 seg_desc.access = usd->sd_type | usd->sd_dpl << 5 | usd->sd_p << 7;
131 seg_desc.access |= usd->sd_xx << 12;
132 seg_desc.access |= usd->sd_def32 << 14;
133 seg_desc.access |= usd->sd_gran << 15;
139 * Inject an exception with an error code that is a segment selector.
140 * The format of the error code is described in section 6.13, "Error Code",
141 * Intel SDM volume 3.
143 * Bit 0 (EXT) denotes whether the exception occurred during delivery
144 * of an external event like an interrupt.
146 * Bit 1 (IDT) indicates whether the selector points to a gate descriptor
149 * Bit 2(GDT/LDT) has the usual interpretation of Table Indicator (TI).
152 sel_exception(struct vmctx *ctx, int vcpu, int vector, uint16_t sel, int ext)
155 * Bit 2 from the selector is retained as-is in the error code.
157 * Bit 1 can be safely cleared because none of the selectors
158 * encountered during task switch emulation refer to a task
161 * Bit 0 is set depending on the value of 'ext'.
166 vm_inject_fault(ctx, vcpu, vector, 1, sel);
170 * Return 0 if the selector 'sel' in within the limits of the GDT/LDT
171 * and non-zero otherwise.
174 desc_table_limit_check(struct vmctx *ctx, int vcpu, uint16_t sel)
177 uint32_t limit, access;
180 reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;
181 error = vm_get_desc(ctx, vcpu, reg, &base, &limit, &access);
184 if (reg == VM_REG_GUEST_LDTR) {
185 if (SEG_DESC_UNUSABLE(access) || !SEG_DESC_PRESENT(access))
189 if (limit < SEL_LIMIT(sel))
196 * Read/write the segment descriptor 'desc' into the GDT/LDT slot referenced
197 * by the selector 'sel'.
199 * Returns 0 on success.
200 * Returns 1 if an exception was injected into the guest.
201 * Returns -1 otherwise.
204 desc_table_rw(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
205 uint16_t sel, struct user_segment_descriptor *desc, bool doread)
209 uint32_t limit, access;
212 reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;
213 error = vm_get_desc(ctx, vcpu, reg, &base, &limit, &access);
215 assert(limit >= SEL_LIMIT(sel));
217 error = vm_copy_setup(ctx, vcpu, paging, base + SEL_START(sel),
218 sizeof(*desc), doread ? PROT_READ : PROT_WRITE, iov, nitems(iov));
221 vm_copyin(ctx, vcpu, iov, desc, sizeof(*desc));
223 vm_copyout(ctx, vcpu, desc, iov, sizeof(*desc));
229 desc_table_read(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
230 uint16_t sel, struct user_segment_descriptor *desc)
232 return (desc_table_rw(ctx, vcpu, paging, sel, desc, true));
236 desc_table_write(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
237 uint16_t sel, struct user_segment_descriptor *desc)
239 return (desc_table_rw(ctx, vcpu, paging, sel, desc, false));
243 * Read the TSS descriptor referenced by 'sel' into 'desc'.
245 * Returns 0 on success.
246 * Returns 1 if an exception was injected into the guest.
247 * Returns -1 otherwise.
250 read_tss_descriptor(struct vmctx *ctx, int vcpu, struct vm_task_switch *ts,
251 uint16_t sel, struct user_segment_descriptor *desc)
253 struct vm_guest_paging sup_paging;
257 assert(IDXSEL(sel) != 0);
259 /* Fetch the new TSS descriptor */
260 if (desc_table_limit_check(ctx, vcpu, sel)) {
261 if (ts->reason == TSR_IRET)
262 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
264 sel_exception(ctx, vcpu, IDT_GP, sel, ts->ext);
268 sup_paging = ts->paging;
269 sup_paging.cpl = 0; /* implicit supervisor mode */
270 error = desc_table_read(ctx, vcpu, &sup_paging, sel, desc);
275 code_desc(int sd_type)
277 /* code descriptor */
278 return ((sd_type & 0x18) == 0x18);
282 stack_desc(int sd_type)
284 /* writable data descriptor */
285 return ((sd_type & 0x1A) == 0x12);
289 data_desc(int sd_type)
291 /* data descriptor or a readable code descriptor */
292 return ((sd_type & 0x18) == 0x10 || (sd_type & 0x1A) == 0x1A);
296 ldt_desc(int sd_type)
299 return (sd_type == SDT_SYSLDT);
303 * Validate the descriptor 'seg_desc' associated with 'segment'.
305 * Returns 0 on success.
306 * Returns 1 if an exception was injected into the guest.
307 * Returns -1 otherwise.
310 validate_seg_desc(struct vmctx *ctx, int vcpu, struct vm_task_switch *ts,
311 int segment, struct seg_desc *seg_desc)
313 struct vm_guest_paging sup_paging;
314 struct user_segment_descriptor usd;
318 bool ldtseg, codeseg, stackseg, dataseg, conforming;
320 ldtseg = codeseg = stackseg = dataseg = false;
322 case VM_REG_GUEST_LDTR:
325 case VM_REG_GUEST_CS:
328 case VM_REG_GUEST_SS:
331 case VM_REG_GUEST_DS:
332 case VM_REG_GUEST_ES:
333 case VM_REG_GUEST_FS:
334 case VM_REG_GUEST_GS:
341 /* Get the segment selector */
342 sel = GETREG(ctx, vcpu, segment);
344 /* LDT selector must point into the GDT */
345 if (ldtseg && ISLDT(sel)) {
346 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
350 /* Descriptor table limit check */
351 if (desc_table_limit_check(ctx, vcpu, sel)) {
352 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
357 if (IDXSEL(sel) == 0) {
358 /* Code and stack segment selectors cannot be NULL */
359 if (codeseg || stackseg) {
360 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
365 seg_desc->access = 0x10000; /* unusable */
369 /* Read the descriptor from the GDT/LDT */
370 sup_paging = ts->paging;
371 sup_paging.cpl = 0; /* implicit supervisor mode */
372 error = desc_table_read(ctx, vcpu, &sup_paging, sel, &usd);
376 /* Verify that the descriptor type is compatible with the segment */
377 if ((ldtseg && !ldt_desc(usd.sd_type)) ||
378 (codeseg && !code_desc(usd.sd_type)) ||
379 (dataseg && !data_desc(usd.sd_type)) ||
380 (stackseg && !stack_desc(usd.sd_type))) {
381 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
385 /* Segment must be marked present */
393 sel_exception(ctx, vcpu, idtvec, sel, ts->ext);
397 cs = GETREG(ctx, vcpu, VM_REG_GUEST_CS);
398 cpl = cs & SEL_RPL_MASK;
399 rpl = sel & SEL_RPL_MASK;
402 if (stackseg && (rpl != cpl || dpl != cpl)) {
403 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
408 conforming = (usd.sd_type & 0x4) ? true : false;
409 if ((conforming && (cpl < dpl)) ||
410 (!conforming && (cpl != dpl))) {
411 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
418 * A data segment is always non-conforming except when it's
419 * descriptor is a readable, conforming code segment.
421 if (code_desc(usd.sd_type) && (usd.sd_type & 0x4) != 0)
426 if (!conforming && (rpl > dpl || cpl > dpl)) {
427 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
431 *seg_desc = usd_to_seg_desc(&usd);
436 tss32_save(struct vmctx *ctx, int vcpu, struct vm_task_switch *task_switch,
437 uint32_t eip, struct tss32 *tss, struct iovec *iov)
440 /* General purpose registers */
441 tss->tss_eax = GETREG(ctx, vcpu, VM_REG_GUEST_RAX);
442 tss->tss_ecx = GETREG(ctx, vcpu, VM_REG_GUEST_RCX);
443 tss->tss_edx = GETREG(ctx, vcpu, VM_REG_GUEST_RDX);
444 tss->tss_ebx = GETREG(ctx, vcpu, VM_REG_GUEST_RBX);
445 tss->tss_esp = GETREG(ctx, vcpu, VM_REG_GUEST_RSP);
446 tss->tss_ebp = GETREG(ctx, vcpu, VM_REG_GUEST_RBP);
447 tss->tss_esi = GETREG(ctx, vcpu, VM_REG_GUEST_RSI);
448 tss->tss_edi = GETREG(ctx, vcpu, VM_REG_GUEST_RDI);
450 /* Segment selectors */
451 tss->tss_es = GETREG(ctx, vcpu, VM_REG_GUEST_ES);
452 tss->tss_cs = GETREG(ctx, vcpu, VM_REG_GUEST_CS);
453 tss->tss_ss = GETREG(ctx, vcpu, VM_REG_GUEST_SS);
454 tss->tss_ds = GETREG(ctx, vcpu, VM_REG_GUEST_DS);
455 tss->tss_fs = GETREG(ctx, vcpu, VM_REG_GUEST_FS);
456 tss->tss_gs = GETREG(ctx, vcpu, VM_REG_GUEST_GS);
459 tss->tss_eflags = GETREG(ctx, vcpu, VM_REG_GUEST_RFLAGS);
460 if (task_switch->reason == TSR_IRET)
461 tss->tss_eflags &= ~PSL_NT;
464 /* Copy updated old TSS into guest memory */
465 vm_copyout(ctx, vcpu, tss, iov, sizeof(struct tss32));
469 update_seg_desc(struct vmctx *ctx, int vcpu, int reg, struct seg_desc *sd)
473 error = vm_set_desc(ctx, vcpu, reg, sd->base, sd->limit, sd->access);
478 * Update the vcpu registers to reflect the state of the new task.
480 * Returns 0 on success.
481 * Returns 1 if an exception was injected into the guest.
482 * Returns -1 otherwise.
485 tss32_restore(struct vmctx *ctx, int vcpu, struct vm_task_switch *ts,
486 uint16_t ot_sel, struct tss32 *tss, struct iovec *iov)
488 struct seg_desc seg_desc, seg_desc2;
489 uint64_t *pdpte, maxphyaddr, reserved;
495 if (ts->reason != TSR_IRET && ts->reason != TSR_JMP) {
496 tss->tss_link = ot_sel;
500 eflags = tss->tss_eflags;
505 SETREG(ctx, vcpu, VM_REG_GUEST_LDTR, tss->tss_ldt);
508 if (ts->paging.paging_mode != PAGING_MODE_FLAT) {
509 if (ts->paging.paging_mode == PAGING_MODE_PAE) {
511 * XXX Assuming 36-bit MAXPHYADDR.
513 maxphyaddr = (1UL << 36) - 1;
514 pdpte = paddr_guest2host(ctx, tss->tss_cr3 & ~0x1f, 32);
515 for (i = 0; i < 4; i++) {
516 /* Check reserved bits if the PDPTE is valid */
517 if (!(pdpte[i] & 0x1))
520 * Bits 2:1, 8:5 and bits above the processor's
521 * maximum physical address are reserved.
523 reserved = ~maxphyaddr | 0x1E6;
524 if (pdpte[i] & reserved) {
525 vm_inject_gp(ctx, vcpu);
529 SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE0, pdpte[0]);
530 SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE1, pdpte[1]);
531 SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE2, pdpte[2]);
532 SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE3, pdpte[3]);
534 SETREG(ctx, vcpu, VM_REG_GUEST_CR3, tss->tss_cr3);
535 ts->paging.cr3 = tss->tss_cr3;
539 SETREG(ctx, vcpu, VM_REG_GUEST_RFLAGS, eflags);
540 SETREG(ctx, vcpu, VM_REG_GUEST_RIP, tss->tss_eip);
542 /* General purpose registers */
543 SETREG(ctx, vcpu, VM_REG_GUEST_RAX, tss->tss_eax);
544 SETREG(ctx, vcpu, VM_REG_GUEST_RCX, tss->tss_ecx);
545 SETREG(ctx, vcpu, VM_REG_GUEST_RDX, tss->tss_edx);
546 SETREG(ctx, vcpu, VM_REG_GUEST_RBX, tss->tss_ebx);
547 SETREG(ctx, vcpu, VM_REG_GUEST_RSP, tss->tss_esp);
548 SETREG(ctx, vcpu, VM_REG_GUEST_RBP, tss->tss_ebp);
549 SETREG(ctx, vcpu, VM_REG_GUEST_RSI, tss->tss_esi);
550 SETREG(ctx, vcpu, VM_REG_GUEST_RDI, tss->tss_edi);
552 /* Segment selectors */
553 SETREG(ctx, vcpu, VM_REG_GUEST_ES, tss->tss_es);
554 SETREG(ctx, vcpu, VM_REG_GUEST_CS, tss->tss_cs);
555 SETREG(ctx, vcpu, VM_REG_GUEST_SS, tss->tss_ss);
556 SETREG(ctx, vcpu, VM_REG_GUEST_DS, tss->tss_ds);
557 SETREG(ctx, vcpu, VM_REG_GUEST_FS, tss->tss_fs);
558 SETREG(ctx, vcpu, VM_REG_GUEST_GS, tss->tss_gs);
561 * If this is a nested task then write out the new TSS to update
562 * the previous link field.
565 vm_copyout(ctx, vcpu, tss, iov, sizeof(*tss));
567 /* Validate segment descriptors */
568 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_LDTR, &seg_desc);
571 update_seg_desc(ctx, vcpu, VM_REG_GUEST_LDTR, &seg_desc);
574 * Section "Checks on Guest Segment Registers", Intel SDM, Vol 3.
576 * The SS and CS attribute checks on VM-entry are inter-dependent so
577 * we need to make sure that both segments are valid before updating
578 * either of them. This ensures that the VMCS state can pass the
579 * VM-entry checks so the guest can handle any exception injected
580 * during task switch emulation.
582 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_CS, &seg_desc);
585 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_SS, &seg_desc2);
588 update_seg_desc(ctx, vcpu, VM_REG_GUEST_CS, &seg_desc);
589 update_seg_desc(ctx, vcpu, VM_REG_GUEST_SS, &seg_desc2);
590 ts->paging.cpl = tss->tss_cs & SEL_RPL_MASK;
592 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_DS, &seg_desc);
595 update_seg_desc(ctx, vcpu, VM_REG_GUEST_DS, &seg_desc);
597 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_ES, &seg_desc);
600 update_seg_desc(ctx, vcpu, VM_REG_GUEST_ES, &seg_desc);
602 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_FS, &seg_desc);
605 update_seg_desc(ctx, vcpu, VM_REG_GUEST_FS, &seg_desc);
607 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_GS, &seg_desc);
610 update_seg_desc(ctx, vcpu, VM_REG_GUEST_GS, &seg_desc);
616 * Push an error code on the stack of the new task. This is needed if the
617 * task switch was triggered by a hardware exception that causes an error
618 * code to be saved (e.g. #PF).
620 * Returns 0 on success.
621 * Returns 1 if an exception was injected into the guest.
622 * Returns -1 otherwise.
625 push_errcode(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
626 int task_type, uint32_t errcode)
629 struct seg_desc seg_desc;
630 int stacksize, bytes, error;
631 uint64_t gla, cr0, rflags;
635 cr0 = GETREG(ctx, vcpu, VM_REG_GUEST_CR0);
636 rflags = GETREG(ctx, vcpu, VM_REG_GUEST_RFLAGS);
637 stacksel = GETREG(ctx, vcpu, VM_REG_GUEST_SS);
639 error = vm_get_desc(ctx, vcpu, VM_REG_GUEST_SS, &seg_desc.base,
640 &seg_desc.limit, &seg_desc.access);
644 * Section "Error Code" in the Intel SDM vol 3: the error code is
645 * pushed on the stack as a doubleword or word (depending on the
646 * default interrupt, trap or task gate size).
648 if (task_type == SDT_SYS386BSY || task_type == SDT_SYS386TSS)
654 * PUSH instruction from Intel SDM vol 2: the 'B' flag in the
655 * stack-segment descriptor determines the size of the stack
656 * pointer outside of 64-bit mode.
658 if (SEG_DESC_DEF32(seg_desc.access))
663 esp = GETREG(ctx, vcpu, VM_REG_GUEST_RSP);
666 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS,
667 &seg_desc, esp, bytes, stacksize, PROT_WRITE, &gla)) {
668 sel_exception(ctx, vcpu, IDT_SS, stacksel, 1);
672 if (vie_alignment_check(paging->cpl, bytes, cr0, rflags, gla)) {
673 vm_inject_ac(ctx, vcpu, 1);
677 error = vm_copy_setup(ctx, vcpu, paging, gla, bytes, PROT_WRITE,
682 vm_copyout(ctx, vcpu, &errcode, iov, bytes);
683 SETREG(ctx, vcpu, VM_REG_GUEST_RSP, esp);
688 * Evaluate return value from helper functions and potentially return to
691 * +1: an exception was injected into the guest vcpu
692 * -1: unrecoverable/programming error
696 assert(((x) == 0) || ((x) == 1) || ((x) == -1)); \
698 return (VMEXIT_ABORT); \
700 return (VMEXIT_CONTINUE); \
704 vmexit_task_switch(struct vmctx *ctx, struct vm_exit *vmexit, int *pvcpu)
707 struct tss32 oldtss, newtss;
708 struct vm_task_switch *task_switch;
709 struct vm_guest_paging *paging, sup_paging;
710 struct user_segment_descriptor nt_desc, ot_desc;
711 struct iovec nt_iov[2], ot_iov[2];
712 uint64_t cr0, ot_base;
713 uint32_t eip, ot_lim, access;
714 int error, ext, minlimit, nt_type, ot_type, vcpu;
715 enum task_switch_reason reason;
716 uint16_t nt_sel, ot_sel;
718 task_switch = &vmexit->u.task_switch;
719 nt_sel = task_switch->tsssel;
720 ext = vmexit->u.task_switch.ext;
721 reason = vmexit->u.task_switch.reason;
722 paging = &vmexit->u.task_switch.paging;
725 assert(paging->cpu_mode == CPU_MODE_PROTECTED);
728 * Section 4.6, "Access Rights" in Intel SDM Vol 3.
729 * The following page table accesses are implicitly supervisor mode:
730 * - accesses to GDT or LDT to load segment descriptors
731 * - accesses to the task state segment during task switch
733 sup_paging = *paging;
734 sup_paging.cpl = 0; /* implicit supervisor mode */
736 /* Fetch the new TSS descriptor */
737 error = read_tss_descriptor(ctx, vcpu, task_switch, nt_sel, &nt_desc);
740 nt = usd_to_seg_desc(&nt_desc);
742 /* Verify the type of the new TSS */
743 nt_type = SEG_DESC_TYPE(nt.access);
744 if (nt_type != SDT_SYS386BSY && nt_type != SDT_SYS386TSS &&
745 nt_type != SDT_SYS286BSY && nt_type != SDT_SYS286TSS) {
746 sel_exception(ctx, vcpu, IDT_TS, nt_sel, ext);
750 /* TSS descriptor must have present bit set */
751 if (!SEG_DESC_PRESENT(nt.access)) {
752 sel_exception(ctx, vcpu, IDT_NP, nt_sel, ext);
757 * TSS must have a minimum length of 104 bytes for a 32-bit TSS and
758 * 44 bytes for a 16-bit TSS.
760 if (nt_type == SDT_SYS386BSY || nt_type == SDT_SYS386TSS)
762 else if (nt_type == SDT_SYS286BSY || nt_type == SDT_SYS286TSS)
767 assert(minlimit > 0);
768 if (nt.limit < minlimit) {
769 sel_exception(ctx, vcpu, IDT_TS, nt_sel, ext);
773 /* TSS must be busy if task switch is due to IRET */
774 if (reason == TSR_IRET && !TSS_BUSY(nt_type)) {
775 sel_exception(ctx, vcpu, IDT_TS, nt_sel, ext);
780 * TSS must be available (not busy) if task switch reason is
781 * CALL, JMP, exception or interrupt.
783 if (reason != TSR_IRET && TSS_BUSY(nt_type)) {
784 sel_exception(ctx, vcpu, IDT_GP, nt_sel, ext);
788 /* Fetch the new TSS */
789 error = vm_copy_setup(ctx, vcpu, &sup_paging, nt.base, minlimit + 1,
790 PROT_READ | PROT_WRITE, nt_iov, nitems(nt_iov));
792 vm_copyin(ctx, vcpu, nt_iov, &newtss, minlimit + 1);
794 /* Get the old TSS selector from the guest's task register */
795 ot_sel = GETREG(ctx, vcpu, VM_REG_GUEST_TR);
796 if (ISLDT(ot_sel) || IDXSEL(ot_sel) == 0) {
798 * This might happen if a task switch was attempted without
799 * ever loading the task register with LTR. In this case the
800 * TR would contain the values from power-on:
801 * (sel = 0, base = 0, limit = 0xffff).
803 sel_exception(ctx, vcpu, IDT_TS, ot_sel, task_switch->ext);
807 /* Get the old TSS base and limit from the guest's task register */
808 error = vm_get_desc(ctx, vcpu, VM_REG_GUEST_TR, &ot_base, &ot_lim,
811 assert(!SEG_DESC_UNUSABLE(access) && SEG_DESC_PRESENT(access));
812 ot_type = SEG_DESC_TYPE(access);
813 assert(ot_type == SDT_SYS386BSY || ot_type == SDT_SYS286BSY);
815 /* Fetch the old TSS descriptor */
816 error = read_tss_descriptor(ctx, vcpu, task_switch, ot_sel, &ot_desc);
819 /* Get the old TSS */
820 error = vm_copy_setup(ctx, vcpu, &sup_paging, ot_base, minlimit + 1,
821 PROT_READ | PROT_WRITE, ot_iov, nitems(ot_iov));
823 vm_copyin(ctx, vcpu, ot_iov, &oldtss, minlimit + 1);
826 * Clear the busy bit in the old TSS descriptor if the task switch
827 * due to an IRET or JMP instruction.
829 if (reason == TSR_IRET || reason == TSR_JMP) {
830 ot_desc.sd_type &= ~0x2;
831 error = desc_table_write(ctx, vcpu, &sup_paging, ot_sel,
836 if (nt_type == SDT_SYS286BSY || nt_type == SDT_SYS286TSS) {
837 fprintf(stderr, "Task switch to 16-bit TSS not supported\n");
838 return (VMEXIT_ABORT);
841 /* Save processor state in old TSS */
842 eip = vmexit->rip + vmexit->inst_length;
843 tss32_save(ctx, vcpu, task_switch, eip, &oldtss, ot_iov);
846 * If the task switch was triggered for any reason other than IRET
847 * then set the busy bit in the new TSS descriptor.
849 if (reason != TSR_IRET) {
850 nt_desc.sd_type |= 0x2;
851 error = desc_table_write(ctx, vcpu, &sup_paging, nt_sel,
856 /* Update task register to point at the new TSS */
857 SETREG(ctx, vcpu, VM_REG_GUEST_TR, nt_sel);
859 /* Update the hidden descriptor state of the task register */
860 nt = usd_to_seg_desc(&nt_desc);
861 update_seg_desc(ctx, vcpu, VM_REG_GUEST_TR, &nt);
864 cr0 = GETREG(ctx, vcpu, VM_REG_GUEST_CR0);
865 SETREG(ctx, vcpu, VM_REG_GUEST_CR0, cr0 | CR0_TS);
868 * We are now committed to the task switch. Any exceptions encountered
869 * after this point will be handled in the context of the new task and
870 * the saved instruction pointer will belong to the new task.
872 vmexit->rip = newtss.tss_eip;
873 vmexit->inst_length = 0;
875 /* Load processor state from new TSS */
876 error = tss32_restore(ctx, vcpu, task_switch, ot_sel, &newtss, nt_iov);
880 * Section "Interrupt Tasks" in Intel SDM, Vol 3: if an exception
881 * caused an error code to be generated, this error code is copied
882 * to the stack of the new task.
884 if (task_switch->errcode_valid) {
885 assert(task_switch->ext);
886 assert(task_switch->reason == TSR_IDT_GATE);
887 error = push_errcode(ctx, vcpu, &task_switch->paging, nt_type,
888 task_switch->errcode);
893 * Treatment of virtual-NMI blocking if NMI is delivered through
896 * Section "Architectural State Before A VM Exit", Intel SDM, Vol3:
897 * If the virtual NMIs VM-execution control is 1, VM entry injects
898 * an NMI, and delivery of the NMI causes a task switch that causes
899 * a VM exit, virtual-NMI blocking is in effect before the VM exit
902 * Thus, virtual-NMI blocking is in effect at the time of the task
907 * Treatment of virtual-NMI unblocking on IRET from NMI handler task.
909 * Section "Changes to Instruction Behavior in VMX Non-Root Operation"
910 * If "virtual NMIs" control is 1 IRET removes any virtual-NMI blocking.
911 * This unblocking of virtual-NMI occurs even if IRET causes a fault.
913 * Thus, virtual-NMI blocking is cleared at the time of the task switch
918 * If the task switch was triggered by an event delivered through
919 * the IDT then extinguish the pending event from the vcpu's
922 if (task_switch->reason == TSR_IDT_GATE) {
923 error = vm_set_intinfo(ctx, vcpu, 0);
928 * XXX should inject debug exception if 'T' bit is 1
931 return (VMEXIT_CONTINUE);