2 * Copyright (c) 2012 NetApp, Inc.
3 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <dev/ic/ns16550.h>
35 #ifndef WITHOUT_CAPSICUM
36 #include <sys/capsicum.h>
37 #include <capsicum_helpers.h>
54 #include "uart_emul.h"
56 #define COM1_BASE 0x3F8
58 #define COM2_BASE 0x2F8
61 #define DEFAULT_RCLK 1843200
62 #define DEFAULT_BAUD 9600
64 #define FCR_RX_MASK 0xC0
69 #define MSR_DELTA_MASK 0x0f
72 #define REG_SCR com_scr
77 static bool uart_stdio; /* stdio in use for i/o */
78 static struct termios tio_stdio_orig;
85 { COM1_BASE, COM1_IRQ, false},
86 { COM2_BASE, COM2_IRQ, false},
89 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
93 int rindex; /* index to read from */
94 int windex; /* index to write to */
95 int num; /* number of characters in the fifo */
96 int size; /* size of the fifo */
101 int fd; /* tty device file descriptor */
102 struct termios tio_orig, tio_new; /* I/O Terminals */
106 pthread_mutex_t mtx; /* protects all softc elements */
107 uint8_t data; /* Data register (R/W) */
108 uint8_t ier; /* Interrupt enable register (R/W) */
109 uint8_t lcr; /* Line control register (R/W) */
110 uint8_t mcr; /* Modem control register (R/W) */
111 uint8_t lsr; /* Line status register (R/W) */
112 uint8_t msr; /* Modem status register (R/W) */
113 uint8_t fcr; /* FIFO control register (W) */
114 uint8_t scr; /* Scratch register (R/W) */
116 uint8_t dll; /* Baudrate divisor latch LSB */
117 uint8_t dlh; /* Baudrate divisor latch MSB */
123 bool thre_int_pending; /* THRE interrupt pending */
126 uart_intr_func_t intr_assert;
127 uart_intr_func_t intr_deassert;
130 static void uart_drain(int fd, enum ev_type ev, void *arg);
136 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
140 ttyopen(struct ttyfd *tf)
143 tcgetattr(tf->fd, &tf->tio_orig);
145 tf->tio_new = tf->tio_orig;
146 cfmakeraw(&tf->tio_new);
147 tf->tio_new.c_cflag |= CLOCAL;
148 tcsetattr(tf->fd, TCSANOW, &tf->tio_new);
150 if (tf->fd == STDIN_FILENO) {
151 tio_stdio_orig = tf->tio_orig;
157 ttyread(struct ttyfd *tf)
161 if (read(tf->fd, &rb, 1) == 1)
168 ttywrite(struct ttyfd *tf, unsigned char wb)
171 (void)write(tf->fd, &wb, 1);
175 rxfifo_reset(struct uart_softc *sc, int size)
183 bzero(fifo, sizeof(struct fifo));
186 if (sc->tty.opened) {
188 * Flush any unread input from the tty buffer.
191 nread = read(sc->tty.fd, flushbuf, sizeof(flushbuf));
192 if (nread != sizeof(flushbuf))
197 * Enable mevent to trigger when new characters are available
200 error = mevent_enable(sc->mev);
206 rxfifo_available(struct uart_softc *sc)
211 return (fifo->num < fifo->size);
215 rxfifo_putchar(struct uart_softc *sc, uint8_t ch)
222 if (fifo->num < fifo->size) {
223 fifo->buf[fifo->windex] = ch;
224 fifo->windex = (fifo->windex + 1) % fifo->size;
226 if (!rxfifo_available(sc)) {
227 if (sc->tty.opened) {
229 * Disable mevent callback if the FIFO is full.
231 error = mevent_disable(sc->mev);
241 rxfifo_getchar(struct uart_softc *sc)
244 int c, error, wasfull;
249 if (!rxfifo_available(sc))
251 c = fifo->buf[fifo->rindex];
252 fifo->rindex = (fifo->rindex + 1) % fifo->size;
255 if (sc->tty.opened) {
256 error = mevent_enable(sc->mev);
266 rxfifo_numchars(struct uart_softc *sc)
268 struct fifo *fifo = &sc->rxfifo;
274 uart_opentty(struct uart_softc *sc)
278 sc->mev = mevent_add(sc->tty.fd, EVF_READ, uart_drain, sc);
279 assert(sc->mev != NULL);
283 modem_status(uint8_t mcr)
287 if (mcr & MCR_LOOPBACK) {
289 * In the loopback mode certain bits from the MCR are
290 * reflected back into MSR.
303 * Always assert DCD and DSR so tty open doesn't block
304 * even if CLOCAL is turned off.
306 msr = MSR_DCD | MSR_DSR;
308 assert((msr & MSR_DELTA_MASK) == 0);
314 * The IIR returns a prioritized interrupt reason:
315 * - receive data available
316 * - transmit holding register empty
317 * - modem status change
319 * Return an interrupt reason if one is available.
322 uart_intr_reason(struct uart_softc *sc)
325 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
327 else if (rxfifo_numchars(sc) > 0 && (sc->ier & IER_ERXRDY) != 0)
329 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
331 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
338 uart_reset(struct uart_softc *sc)
342 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
344 sc->dlh = divisor >> 16;
345 sc->msr = modem_status(sc->mcr);
347 rxfifo_reset(sc, 1); /* no fifo until enabled by software */
351 * Toggle the COM port's intr pin depending on whether or not we have an
352 * interrupt condition to report to the processor.
355 uart_toggle_intr(struct uart_softc *sc)
359 intr_reason = uart_intr_reason(sc);
361 if (intr_reason == IIR_NOPEND)
362 (*sc->intr_deassert)(sc->arg);
364 (*sc->intr_assert)(sc->arg);
368 uart_drain(int fd, enum ev_type ev, void *arg)
370 struct uart_softc *sc;
375 assert(fd == sc->tty.fd);
376 assert(ev == EVF_READ);
379 * This routine is called in the context of the mevent thread
380 * to take out the softc lock to protect against concurrent
381 * access from a vCPU i/o exit
383 pthread_mutex_lock(&sc->mtx);
385 if ((sc->mcr & MCR_LOOPBACK) != 0) {
386 (void) ttyread(&sc->tty);
388 while (rxfifo_available(sc) &&
389 ((ch = ttyread(&sc->tty)) != -1)) {
390 rxfifo_putchar(sc, ch);
392 uart_toggle_intr(sc);
395 pthread_mutex_unlock(&sc->mtx);
399 uart_write(struct uart_softc *sc, int offset, uint8_t value)
404 pthread_mutex_lock(&sc->mtx);
407 * Take care of the special case DLAB accesses first
409 if ((sc->lcr & LCR_DLAB) != 0) {
410 if (offset == REG_DLL) {
415 if (offset == REG_DLH) {
423 if (sc->mcr & MCR_LOOPBACK) {
424 if (rxfifo_putchar(sc, value) != 0)
426 } else if (sc->tty.opened) {
427 ttywrite(&sc->tty, value);
428 } /* else drop on floor */
429 sc->thre_int_pending = true;
433 * Apply mask so that bits 4-7 are 0
434 * Also enables bits 0-3 only if they're 1
436 sc->ier = value & 0x0F;
440 * When moving from FIFO and 16450 mode and vice versa,
441 * the FIFO contents are reset.
443 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
444 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
445 rxfifo_reset(sc, fifosz);
449 * The FCR_ENABLE bit must be '1' for the programming
450 * of other FCR bits to be effective.
452 if ((value & FCR_ENABLE) == 0) {
455 if ((value & FCR_RCV_RST) != 0)
456 rxfifo_reset(sc, FIFOSZ);
459 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
466 /* Apply mask so that bits 5-7 are 0 */
467 sc->mcr = value & 0x1F;
468 msr = modem_status(sc->mcr);
471 * Detect if there has been any change between the
472 * previous and the new value of MSR. If there is
473 * then assert the appropriate MSR delta bit.
475 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
477 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
479 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
481 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
485 * Update the value of MSR while retaining the delta
488 sc->msr &= MSR_DELTA_MASK;
493 * Line status register is not meant to be written to
494 * during normal operation.
499 * As far as I can tell MSR is a read-only register.
510 uart_toggle_intr(sc);
511 pthread_mutex_unlock(&sc->mtx);
515 uart_read(struct uart_softc *sc, int offset)
517 uint8_t iir, intr_reason, reg;
519 pthread_mutex_lock(&sc->mtx);
522 * Take care of the special case DLAB accesses first
524 if ((sc->lcr & LCR_DLAB) != 0) {
525 if (offset == REG_DLL) {
530 if (offset == REG_DLH) {
538 reg = rxfifo_getchar(sc);
544 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
546 intr_reason = uart_intr_reason(sc);
549 * Deal with side effects of reading the IIR register
551 if (intr_reason == IIR_TXRDY)
552 sc->thre_int_pending = false;
565 /* Transmitter is always ready for more data */
566 sc->lsr |= LSR_TEMT | LSR_THRE;
568 /* Check for new receive data */
569 if (rxfifo_numchars(sc) > 0)
570 sc->lsr |= LSR_RXRDY;
572 sc->lsr &= ~LSR_RXRDY;
576 /* The LSR_OE bit is cleared on LSR read */
581 * MSR delta bits are cleared on read
584 sc->msr &= ~MSR_DELTA_MASK;
595 uart_toggle_intr(sc);
596 pthread_mutex_unlock(&sc->mtx);
602 uart_legacy_alloc(int which, int *baseaddr, int *irq)
605 if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
608 uart_lres[which].inuse = true;
609 *baseaddr = uart_lres[which].baseaddr;
610 *irq = uart_lres[which].irq;
616 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
619 struct uart_softc *sc;
621 sc = calloc(1, sizeof(struct uart_softc));
624 sc->intr_assert = intr_assert;
625 sc->intr_deassert = intr_deassert;
627 pthread_mutex_init(&sc->mtx, NULL);
635 uart_tty_backend(struct uart_softc *sc, const char *opts)
642 fd = open(opts, O_RDWR | O_NONBLOCK);
643 if (fd > 0 && isatty(fd)) {
645 sc->tty.opened = true;
653 uart_set_backend(struct uart_softc *sc, const char *opts)
656 #ifndef WITHOUT_CAPSICUM
658 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
666 if (strcmp("stdio", opts) == 0) {
668 sc->tty.fd = STDIN_FILENO;
669 sc->tty.opened = true;
673 } else if (uart_tty_backend(sc, opts) == 0) {
677 /* Make the backend file descriptor non-blocking */
679 retval = fcntl(sc->tty.fd, F_SETFL, O_NONBLOCK);
681 #ifndef WITHOUT_CAPSICUM
682 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ, CAP_WRITE);
683 if (cap_rights_limit(sc->tty.fd, &rights) == -1 && errno != ENOSYS)
684 errx(EX_OSERR, "Unable to apply rights for sandbox");
685 if (cap_ioctls_limit(sc->tty.fd, cmds, nitems(cmds)) == -1 && errno != ENOSYS)
686 errx(EX_OSERR, "Unable to apply rights for sandbox");
688 if (caph_limit_stdin() == -1 && errno != ENOSYS)
689 errx(EX_OSERR, "Unable to apply rights for sandbox");