2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 NetApp, Inc.
5 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #include <dev/ic/ns16550.h>
37 #ifndef WITHOUT_CAPSICUM
38 #include <sys/capsicum.h>
39 #include <capsicum_helpers.h>
42 #include <machine/vmm_snapshot.h>
58 #include "uart_emul.h"
61 #define COM1_BASE 0x3F8
63 #define COM2_BASE 0x2F8
66 #define DEFAULT_RCLK 1843200
67 #define DEFAULT_BAUD 9600
69 #define FCR_RX_MASK 0xC0
74 #define MSR_DELTA_MASK 0x0f
77 #define REG_SCR com_scr
82 static bool uart_stdio; /* stdio in use for i/o */
83 static struct termios tio_stdio_orig;
90 { COM1_BASE, COM1_IRQ, false},
91 { COM2_BASE, COM2_IRQ, false},
94 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
98 int rindex; /* index to read from */
99 int windex; /* index to write to */
100 int num; /* number of characters in the fifo */
101 int size; /* size of the fifo */
106 int rfd; /* fd for reading */
107 int wfd; /* fd for writing, may be == rfd */
111 pthread_mutex_t mtx; /* protects all softc elements */
112 uint8_t data; /* Data register (R/W) */
113 uint8_t ier; /* Interrupt enable register (R/W) */
114 uint8_t lcr; /* Line control register (R/W) */
115 uint8_t mcr; /* Modem control register (R/W) */
116 uint8_t lsr; /* Line status register (R/W) */
117 uint8_t msr; /* Modem status register (R/W) */
118 uint8_t fcr; /* FIFO control register (W) */
119 uint8_t scr; /* Scratch register (R/W) */
121 uint8_t dll; /* Baudrate divisor latch LSB */
122 uint8_t dlh; /* Baudrate divisor latch MSB */
128 bool thre_int_pending; /* THRE interrupt pending */
131 uart_intr_func_t intr_assert;
132 uart_intr_func_t intr_deassert;
135 static void uart_drain(int fd, enum ev_type ev, void *arg);
141 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
145 ttyopen(struct ttyfd *tf)
147 struct termios orig, new;
149 tcgetattr(tf->rfd, &orig);
152 new.c_cflag |= CLOCAL;
153 tcsetattr(tf->rfd, TCSANOW, &new);
155 tio_stdio_orig = orig;
162 ttyread(struct ttyfd *tf)
166 if (read(tf->rfd, &rb, 1) == 1)
173 ttywrite(struct ttyfd *tf, unsigned char wb)
176 (void)write(tf->wfd, &wb, 1);
180 rxfifo_reset(struct uart_softc *sc, int size)
188 bzero(fifo, sizeof(struct fifo));
191 if (sc->tty.opened) {
193 * Flush any unread input from the tty buffer.
196 nread = read(sc->tty.rfd, flushbuf, sizeof(flushbuf));
197 if (nread != sizeof(flushbuf))
202 * Enable mevent to trigger when new characters are available
205 error = mevent_enable(sc->mev);
211 rxfifo_available(struct uart_softc *sc)
216 return (fifo->num < fifo->size);
220 rxfifo_putchar(struct uart_softc *sc, uint8_t ch)
227 if (fifo->num < fifo->size) {
228 fifo->buf[fifo->windex] = ch;
229 fifo->windex = (fifo->windex + 1) % fifo->size;
231 if (!rxfifo_available(sc)) {
232 if (sc->tty.opened) {
234 * Disable mevent callback if the FIFO is full.
236 error = mevent_disable(sc->mev);
246 rxfifo_getchar(struct uart_softc *sc)
249 int c, error, wasfull;
254 if (!rxfifo_available(sc))
256 c = fifo->buf[fifo->rindex];
257 fifo->rindex = (fifo->rindex + 1) % fifo->size;
260 if (sc->tty.opened) {
261 error = mevent_enable(sc->mev);
271 rxfifo_numchars(struct uart_softc *sc)
273 struct fifo *fifo = &sc->rxfifo;
279 uart_opentty(struct uart_softc *sc)
283 sc->mev = mevent_add(sc->tty.rfd, EVF_READ, uart_drain, sc);
284 assert(sc->mev != NULL);
288 modem_status(uint8_t mcr)
292 if (mcr & MCR_LOOPBACK) {
294 * In the loopback mode certain bits from the MCR are
295 * reflected back into MSR.
308 * Always assert DCD and DSR so tty open doesn't block
309 * even if CLOCAL is turned off.
311 msr = MSR_DCD | MSR_DSR;
313 assert((msr & MSR_DELTA_MASK) == 0);
319 * The IIR returns a prioritized interrupt reason:
320 * - receive data available
321 * - transmit holding register empty
322 * - modem status change
324 * Return an interrupt reason if one is available.
327 uart_intr_reason(struct uart_softc *sc)
330 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
332 else if (rxfifo_numchars(sc) > 0 && (sc->ier & IER_ERXRDY) != 0)
334 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
336 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
343 uart_reset(struct uart_softc *sc)
347 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
349 sc->dlh = divisor >> 16;
350 sc->msr = modem_status(sc->mcr);
352 rxfifo_reset(sc, 1); /* no fifo until enabled by software */
356 * Toggle the COM port's intr pin depending on whether or not we have an
357 * interrupt condition to report to the processor.
360 uart_toggle_intr(struct uart_softc *sc)
364 intr_reason = uart_intr_reason(sc);
366 if (intr_reason == IIR_NOPEND)
367 (*sc->intr_deassert)(sc->arg);
369 (*sc->intr_assert)(sc->arg);
373 uart_drain(int fd, enum ev_type ev, void *arg)
375 struct uart_softc *sc;
380 assert(fd == sc->tty.rfd);
381 assert(ev == EVF_READ);
384 * This routine is called in the context of the mevent thread
385 * to take out the softc lock to protect against concurrent
386 * access from a vCPU i/o exit
388 pthread_mutex_lock(&sc->mtx);
390 if ((sc->mcr & MCR_LOOPBACK) != 0) {
391 (void) ttyread(&sc->tty);
393 while (rxfifo_available(sc) &&
394 ((ch = ttyread(&sc->tty)) != -1)) {
395 rxfifo_putchar(sc, ch);
397 uart_toggle_intr(sc);
400 pthread_mutex_unlock(&sc->mtx);
404 uart_write(struct uart_softc *sc, int offset, uint8_t value)
409 pthread_mutex_lock(&sc->mtx);
412 * Take care of the special case DLAB accesses first
414 if ((sc->lcr & LCR_DLAB) != 0) {
415 if (offset == REG_DLL) {
420 if (offset == REG_DLH) {
428 if (sc->mcr & MCR_LOOPBACK) {
429 if (rxfifo_putchar(sc, value) != 0)
431 } else if (sc->tty.opened) {
432 ttywrite(&sc->tty, value);
433 } /* else drop on floor */
434 sc->thre_int_pending = true;
437 /* Set pending when IER_ETXRDY is raised (edge-triggered). */
438 if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0)
439 sc->thre_int_pending = true;
441 * Apply mask so that bits 4-7 are 0
442 * Also enables bits 0-3 only if they're 1
444 sc->ier = value & 0x0F;
448 * When moving from FIFO and 16450 mode and vice versa,
449 * the FIFO contents are reset.
451 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
452 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
453 rxfifo_reset(sc, fifosz);
457 * The FCR_ENABLE bit must be '1' for the programming
458 * of other FCR bits to be effective.
460 if ((value & FCR_ENABLE) == 0) {
463 if ((value & FCR_RCV_RST) != 0)
464 rxfifo_reset(sc, FIFOSZ);
467 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
474 /* Apply mask so that bits 5-7 are 0 */
475 sc->mcr = value & 0x1F;
476 msr = modem_status(sc->mcr);
479 * Detect if there has been any change between the
480 * previous and the new value of MSR. If there is
481 * then assert the appropriate MSR delta bit.
483 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
485 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
487 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
489 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
493 * Update the value of MSR while retaining the delta
496 sc->msr &= MSR_DELTA_MASK;
501 * Line status register is not meant to be written to
502 * during normal operation.
507 * As far as I can tell MSR is a read-only register.
518 uart_toggle_intr(sc);
519 pthread_mutex_unlock(&sc->mtx);
523 uart_read(struct uart_softc *sc, int offset)
525 uint8_t iir, intr_reason, reg;
527 pthread_mutex_lock(&sc->mtx);
530 * Take care of the special case DLAB accesses first
532 if ((sc->lcr & LCR_DLAB) != 0) {
533 if (offset == REG_DLL) {
538 if (offset == REG_DLH) {
546 reg = rxfifo_getchar(sc);
552 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
554 intr_reason = uart_intr_reason(sc);
557 * Deal with side effects of reading the IIR register
559 if (intr_reason == IIR_TXRDY)
560 sc->thre_int_pending = false;
573 /* Transmitter is always ready for more data */
574 sc->lsr |= LSR_TEMT | LSR_THRE;
576 /* Check for new receive data */
577 if (rxfifo_numchars(sc) > 0)
578 sc->lsr |= LSR_RXRDY;
580 sc->lsr &= ~LSR_RXRDY;
584 /* The LSR_OE bit is cleared on LSR read */
589 * MSR delta bits are cleared on read
592 sc->msr &= ~MSR_DELTA_MASK;
603 uart_toggle_intr(sc);
604 pthread_mutex_unlock(&sc->mtx);
610 uart_legacy_alloc(int which, int *baseaddr, int *irq)
613 if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
616 uart_lres[which].inuse = true;
617 *baseaddr = uart_lres[which].baseaddr;
618 *irq = uart_lres[which].irq;
624 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
627 struct uart_softc *sc;
629 sc = calloc(1, sizeof(struct uart_softc));
632 sc->intr_assert = intr_assert;
633 sc->intr_deassert = intr_deassert;
635 pthread_mutex_init(&sc->mtx, NULL);
643 uart_stdio_backend(struct uart_softc *sc)
645 #ifndef WITHOUT_CAPSICUM
647 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
653 sc->tty.rfd = STDIN_FILENO;
654 sc->tty.wfd = STDOUT_FILENO;
655 sc->tty.opened = true;
657 if (fcntl(sc->tty.rfd, F_SETFL, O_NONBLOCK) != 0)
659 if (fcntl(sc->tty.wfd, F_SETFL, O_NONBLOCK) != 0)
662 #ifndef WITHOUT_CAPSICUM
663 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ);
664 if (caph_rights_limit(sc->tty.rfd, &rights) == -1)
665 errx(EX_OSERR, "Unable to apply rights for sandbox");
666 if (caph_ioctls_limit(sc->tty.rfd, cmds, nitems(cmds)) == -1)
667 errx(EX_OSERR, "Unable to apply rights for sandbox");
676 uart_tty_backend(struct uart_softc *sc, const char *opts)
678 #ifndef WITHOUT_CAPSICUM
680 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
684 fd = open(opts, O_RDWR | O_NONBLOCK);
693 sc->tty.rfd = sc->tty.wfd = fd;
694 sc->tty.opened = true;
696 #ifndef WITHOUT_CAPSICUM
697 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ, CAP_WRITE);
698 if (caph_rights_limit(fd, &rights) == -1)
699 errx(EX_OSERR, "Unable to apply rights for sandbox");
700 if (caph_ioctls_limit(fd, cmds, nitems(cmds)) == -1)
701 errx(EX_OSERR, "Unable to apply rights for sandbox");
708 uart_set_backend(struct uart_softc *sc, const char *opts)
715 if (strcmp("stdio", opts) == 0)
716 retval = uart_stdio_backend(sc);
718 retval = uart_tty_backend(sc, opts);
725 #ifdef BHYVE_SNAPSHOT
727 uart_snapshot(struct uart_softc *sc, struct vm_snapshot_meta *meta)
731 SNAPSHOT_VAR_OR_LEAVE(sc->data, meta, ret, done);
732 SNAPSHOT_VAR_OR_LEAVE(sc->ier, meta, ret, done);
733 SNAPSHOT_VAR_OR_LEAVE(sc->lcr, meta, ret, done);
734 SNAPSHOT_VAR_OR_LEAVE(sc->mcr, meta, ret, done);
735 SNAPSHOT_VAR_OR_LEAVE(sc->lsr, meta, ret, done);
736 SNAPSHOT_VAR_OR_LEAVE(sc->msr, meta, ret, done);
737 SNAPSHOT_VAR_OR_LEAVE(sc->fcr, meta, ret, done);
738 SNAPSHOT_VAR_OR_LEAVE(sc->scr, meta, ret, done);
740 SNAPSHOT_VAR_OR_LEAVE(sc->dll, meta, ret, done);
741 SNAPSHOT_VAR_OR_LEAVE(sc->dlh, meta, ret, done);
743 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.rindex, meta, ret, done);
744 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.windex, meta, ret, done);
745 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.num, meta, ret, done);
746 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.size, meta, ret, done);
747 SNAPSHOT_BUF_OR_LEAVE(sc->rxfifo.buf, sizeof(sc->rxfifo.buf),
750 sc->thre_int_pending = 1;