2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 NetApp, Inc.
5 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #include <dev/ic/ns16550.h>
37 #ifndef WITHOUT_CAPSICUM
38 #include <sys/capsicum.h>
39 #include <capsicum_helpers.h>
42 #include <machine/vmm_snapshot.h>
58 #include "uart_emul.h"
61 #define COM1_BASE 0x3F8
63 #define COM2_BASE 0x2F8
65 #define COM3_BASE 0x3E8
67 #define COM4_BASE 0x2E8
70 #define DEFAULT_RCLK 1843200
71 #define DEFAULT_BAUD 9600
73 #define FCR_RX_MASK 0xC0
78 #define MSR_DELTA_MASK 0x0f
81 #define REG_SCR com_scr
86 static bool uart_stdio; /* stdio in use for i/o */
87 static struct termios tio_stdio_orig;
94 { COM1_BASE, COM1_IRQ, false},
95 { COM2_BASE, COM2_IRQ, false},
96 { COM3_BASE, COM3_IRQ, false},
97 { COM4_BASE, COM4_IRQ, false},
100 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
104 int rindex; /* index to read from */
105 int windex; /* index to write to */
106 int num; /* number of characters in the fifo */
107 int size; /* size of the fifo */
112 int rfd; /* fd for reading */
113 int wfd; /* fd for writing, may be == rfd */
117 pthread_mutex_t mtx; /* protects all softc elements */
118 uint8_t data; /* Data register (R/W) */
119 uint8_t ier; /* Interrupt enable register (R/W) */
120 uint8_t lcr; /* Line control register (R/W) */
121 uint8_t mcr; /* Modem control register (R/W) */
122 uint8_t lsr; /* Line status register (R/W) */
123 uint8_t msr; /* Modem status register (R/W) */
124 uint8_t fcr; /* FIFO control register (W) */
125 uint8_t scr; /* Scratch register (R/W) */
127 uint8_t dll; /* Baudrate divisor latch LSB */
128 uint8_t dlh; /* Baudrate divisor latch MSB */
134 bool thre_int_pending; /* THRE interrupt pending */
137 uart_intr_func_t intr_assert;
138 uart_intr_func_t intr_deassert;
141 static void uart_drain(int fd, enum ev_type ev, void *arg);
147 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
151 ttyopen(struct ttyfd *tf)
153 struct termios orig, new;
155 tcgetattr(tf->rfd, &orig);
158 new.c_cflag |= CLOCAL;
159 tcsetattr(tf->rfd, TCSANOW, &new);
161 tio_stdio_orig = orig;
168 ttyread(struct ttyfd *tf)
172 if (read(tf->rfd, &rb, 1) == 1)
179 ttywrite(struct ttyfd *tf, unsigned char wb)
182 (void)write(tf->wfd, &wb, 1);
186 rxfifo_reset(struct uart_softc *sc, int size)
194 bzero(fifo, sizeof(struct fifo));
197 if (sc->tty.opened) {
199 * Flush any unread input from the tty buffer.
202 nread = read(sc->tty.rfd, flushbuf, sizeof(flushbuf));
203 if (nread != sizeof(flushbuf))
208 * Enable mevent to trigger when new characters are available
211 error = mevent_enable(sc->mev);
217 rxfifo_available(struct uart_softc *sc)
222 return (fifo->num < fifo->size);
226 rxfifo_putchar(struct uart_softc *sc, uint8_t ch)
233 if (fifo->num < fifo->size) {
234 fifo->buf[fifo->windex] = ch;
235 fifo->windex = (fifo->windex + 1) % fifo->size;
237 if (!rxfifo_available(sc)) {
238 if (sc->tty.opened) {
240 * Disable mevent callback if the FIFO is full.
242 error = mevent_disable(sc->mev);
252 rxfifo_getchar(struct uart_softc *sc)
255 int c, error, wasfull;
260 if (!rxfifo_available(sc))
262 c = fifo->buf[fifo->rindex];
263 fifo->rindex = (fifo->rindex + 1) % fifo->size;
266 if (sc->tty.opened) {
267 error = mevent_enable(sc->mev);
277 rxfifo_numchars(struct uart_softc *sc)
279 struct fifo *fifo = &sc->rxfifo;
285 uart_opentty(struct uart_softc *sc)
289 sc->mev = mevent_add(sc->tty.rfd, EVF_READ, uart_drain, sc);
290 assert(sc->mev != NULL);
294 modem_status(uint8_t mcr)
298 if (mcr & MCR_LOOPBACK) {
300 * In the loopback mode certain bits from the MCR are
301 * reflected back into MSR.
314 * Always assert DCD and DSR so tty open doesn't block
315 * even if CLOCAL is turned off.
317 msr = MSR_DCD | MSR_DSR;
319 assert((msr & MSR_DELTA_MASK) == 0);
325 * The IIR returns a prioritized interrupt reason:
326 * - receive data available
327 * - transmit holding register empty
328 * - modem status change
330 * Return an interrupt reason if one is available.
333 uart_intr_reason(struct uart_softc *sc)
336 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
338 else if (rxfifo_numchars(sc) > 0 && (sc->ier & IER_ERXRDY) != 0)
340 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
342 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
349 uart_reset(struct uart_softc *sc)
353 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
355 sc->dlh = divisor >> 16;
356 sc->msr = modem_status(sc->mcr);
358 rxfifo_reset(sc, 1); /* no fifo until enabled by software */
362 * Toggle the COM port's intr pin depending on whether or not we have an
363 * interrupt condition to report to the processor.
366 uart_toggle_intr(struct uart_softc *sc)
370 intr_reason = uart_intr_reason(sc);
372 if (intr_reason == IIR_NOPEND)
373 (*sc->intr_deassert)(sc->arg);
375 (*sc->intr_assert)(sc->arg);
379 uart_drain(int fd, enum ev_type ev, void *arg)
381 struct uart_softc *sc;
386 assert(fd == sc->tty.rfd);
387 assert(ev == EVF_READ);
390 * This routine is called in the context of the mevent thread
391 * to take out the softc lock to protect against concurrent
392 * access from a vCPU i/o exit
394 pthread_mutex_lock(&sc->mtx);
396 if ((sc->mcr & MCR_LOOPBACK) != 0) {
397 (void) ttyread(&sc->tty);
399 while (rxfifo_available(sc) &&
400 ((ch = ttyread(&sc->tty)) != -1)) {
401 rxfifo_putchar(sc, ch);
403 uart_toggle_intr(sc);
406 pthread_mutex_unlock(&sc->mtx);
410 uart_write(struct uart_softc *sc, int offset, uint8_t value)
415 pthread_mutex_lock(&sc->mtx);
418 * Take care of the special case DLAB accesses first
420 if ((sc->lcr & LCR_DLAB) != 0) {
421 if (offset == REG_DLL) {
426 if (offset == REG_DLH) {
434 if (sc->mcr & MCR_LOOPBACK) {
435 if (rxfifo_putchar(sc, value) != 0)
437 } else if (sc->tty.opened) {
438 ttywrite(&sc->tty, value);
439 } /* else drop on floor */
440 sc->thre_int_pending = true;
443 /* Set pending when IER_ETXRDY is raised (edge-triggered). */
444 if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0)
445 sc->thre_int_pending = true;
447 * Apply mask so that bits 4-7 are 0
448 * Also enables bits 0-3 only if they're 1
450 sc->ier = value & 0x0F;
454 * When moving from FIFO and 16450 mode and vice versa,
455 * the FIFO contents are reset.
457 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
458 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
459 rxfifo_reset(sc, fifosz);
463 * The FCR_ENABLE bit must be '1' for the programming
464 * of other FCR bits to be effective.
466 if ((value & FCR_ENABLE) == 0) {
469 if ((value & FCR_RCV_RST) != 0)
470 rxfifo_reset(sc, FIFOSZ);
473 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
480 /* Apply mask so that bits 5-7 are 0 */
481 sc->mcr = value & 0x1F;
482 msr = modem_status(sc->mcr);
485 * Detect if there has been any change between the
486 * previous and the new value of MSR. If there is
487 * then assert the appropriate MSR delta bit.
489 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
491 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
493 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
495 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
499 * Update the value of MSR while retaining the delta
502 sc->msr &= MSR_DELTA_MASK;
507 * Line status register is not meant to be written to
508 * during normal operation.
513 * As far as I can tell MSR is a read-only register.
524 uart_toggle_intr(sc);
525 pthread_mutex_unlock(&sc->mtx);
529 uart_read(struct uart_softc *sc, int offset)
531 uint8_t iir, intr_reason, reg;
533 pthread_mutex_lock(&sc->mtx);
536 * Take care of the special case DLAB accesses first
538 if ((sc->lcr & LCR_DLAB) != 0) {
539 if (offset == REG_DLL) {
544 if (offset == REG_DLH) {
552 reg = rxfifo_getchar(sc);
558 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
560 intr_reason = uart_intr_reason(sc);
563 * Deal with side effects of reading the IIR register
565 if (intr_reason == IIR_TXRDY)
566 sc->thre_int_pending = false;
579 /* Transmitter is always ready for more data */
580 sc->lsr |= LSR_TEMT | LSR_THRE;
582 /* Check for new receive data */
583 if (rxfifo_numchars(sc) > 0)
584 sc->lsr |= LSR_RXRDY;
586 sc->lsr &= ~LSR_RXRDY;
590 /* The LSR_OE bit is cleared on LSR read */
595 * MSR delta bits are cleared on read
598 sc->msr &= ~MSR_DELTA_MASK;
609 uart_toggle_intr(sc);
610 pthread_mutex_unlock(&sc->mtx);
616 uart_legacy_alloc(int which, int *baseaddr, int *irq)
619 if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
622 uart_lres[which].inuse = true;
623 *baseaddr = uart_lres[which].baseaddr;
624 *irq = uart_lres[which].irq;
630 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
633 struct uart_softc *sc;
635 sc = calloc(1, sizeof(struct uart_softc));
638 sc->intr_assert = intr_assert;
639 sc->intr_deassert = intr_deassert;
641 pthread_mutex_init(&sc->mtx, NULL);
649 uart_stdio_backend(struct uart_softc *sc)
651 #ifndef WITHOUT_CAPSICUM
653 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
659 sc->tty.rfd = STDIN_FILENO;
660 sc->tty.wfd = STDOUT_FILENO;
661 sc->tty.opened = true;
663 if (fcntl(sc->tty.rfd, F_SETFL, O_NONBLOCK) != 0)
665 if (fcntl(sc->tty.wfd, F_SETFL, O_NONBLOCK) != 0)
668 #ifndef WITHOUT_CAPSICUM
669 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ);
670 if (caph_rights_limit(sc->tty.rfd, &rights) == -1)
671 errx(EX_OSERR, "Unable to apply rights for sandbox");
672 if (caph_ioctls_limit(sc->tty.rfd, cmds, nitems(cmds)) == -1)
673 errx(EX_OSERR, "Unable to apply rights for sandbox");
682 uart_tty_backend(struct uart_softc *sc, const char *path)
684 #ifndef WITHOUT_CAPSICUM
686 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
690 fd = open(path, O_RDWR | O_NONBLOCK);
699 sc->tty.rfd = sc->tty.wfd = fd;
700 sc->tty.opened = true;
702 #ifndef WITHOUT_CAPSICUM
703 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ, CAP_WRITE);
704 if (caph_rights_limit(fd, &rights) == -1)
705 errx(EX_OSERR, "Unable to apply rights for sandbox");
706 if (caph_ioctls_limit(fd, cmds, nitems(cmds)) == -1)
707 errx(EX_OSERR, "Unable to apply rights for sandbox");
714 uart_set_backend(struct uart_softc *sc, const char *device)
721 if (strcmp("stdio", device) == 0)
722 retval = uart_stdio_backend(sc);
724 retval = uart_tty_backend(sc, device);
731 #ifdef BHYVE_SNAPSHOT
733 uart_snapshot(struct uart_softc *sc, struct vm_snapshot_meta *meta)
737 SNAPSHOT_VAR_OR_LEAVE(sc->data, meta, ret, done);
738 SNAPSHOT_VAR_OR_LEAVE(sc->ier, meta, ret, done);
739 SNAPSHOT_VAR_OR_LEAVE(sc->lcr, meta, ret, done);
740 SNAPSHOT_VAR_OR_LEAVE(sc->mcr, meta, ret, done);
741 SNAPSHOT_VAR_OR_LEAVE(sc->lsr, meta, ret, done);
742 SNAPSHOT_VAR_OR_LEAVE(sc->msr, meta, ret, done);
743 SNAPSHOT_VAR_OR_LEAVE(sc->fcr, meta, ret, done);
744 SNAPSHOT_VAR_OR_LEAVE(sc->scr, meta, ret, done);
746 SNAPSHOT_VAR_OR_LEAVE(sc->dll, meta, ret, done);
747 SNAPSHOT_VAR_OR_LEAVE(sc->dlh, meta, ret, done);
749 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.rindex, meta, ret, done);
750 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.windex, meta, ret, done);
751 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.num, meta, ret, done);
752 SNAPSHOT_VAR_OR_LEAVE(sc->rxfifo.size, meta, ret, done);
753 SNAPSHOT_BUF_OR_LEAVE(sc->rxfifo.buf, sizeof(sc->rxfifo.buf),
756 sc->thre_int_pending = 1;