2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 NetApp, Inc.
5 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #include <dev/ic/ns16550.h>
37 #ifndef WITHOUT_CAPSICUM
38 #include <sys/capsicum.h>
39 #include <capsicum_helpers.h>
56 #include "uart_emul.h"
58 #define COM1_BASE 0x3F8
60 #define COM2_BASE 0x2F8
63 #define DEFAULT_RCLK 1843200
64 #define DEFAULT_BAUD 9600
66 #define FCR_RX_MASK 0xC0
71 #define MSR_DELTA_MASK 0x0f
74 #define REG_SCR com_scr
79 static bool uart_stdio; /* stdio in use for i/o */
80 static struct termios tio_stdio_orig;
87 { COM1_BASE, COM1_IRQ, false},
88 { COM2_BASE, COM2_IRQ, false},
91 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
95 int rindex; /* index to read from */
96 int windex; /* index to write to */
97 int num; /* number of characters in the fifo */
98 int size; /* size of the fifo */
103 int fd; /* tty device file descriptor */
104 struct termios tio_orig, tio_new; /* I/O Terminals */
108 pthread_mutex_t mtx; /* protects all softc elements */
109 uint8_t data; /* Data register (R/W) */
110 uint8_t ier; /* Interrupt enable register (R/W) */
111 uint8_t lcr; /* Line control register (R/W) */
112 uint8_t mcr; /* Modem control register (R/W) */
113 uint8_t lsr; /* Line status register (R/W) */
114 uint8_t msr; /* Modem status register (R/W) */
115 uint8_t fcr; /* FIFO control register (W) */
116 uint8_t scr; /* Scratch register (R/W) */
118 uint8_t dll; /* Baudrate divisor latch LSB */
119 uint8_t dlh; /* Baudrate divisor latch MSB */
125 bool thre_int_pending; /* THRE interrupt pending */
128 uart_intr_func_t intr_assert;
129 uart_intr_func_t intr_deassert;
132 static void uart_drain(int fd, enum ev_type ev, void *arg);
138 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
142 ttyopen(struct ttyfd *tf)
145 tcgetattr(tf->fd, &tf->tio_orig);
147 tf->tio_new = tf->tio_orig;
148 cfmakeraw(&tf->tio_new);
149 tf->tio_new.c_cflag |= CLOCAL;
150 tcsetattr(tf->fd, TCSANOW, &tf->tio_new);
152 if (tf->fd == STDIN_FILENO) {
153 tio_stdio_orig = tf->tio_orig;
159 ttyread(struct ttyfd *tf)
163 if (read(tf->fd, &rb, 1) == 1)
170 ttywrite(struct ttyfd *tf, unsigned char wb)
173 (void)write(tf->fd, &wb, 1);
177 rxfifo_reset(struct uart_softc *sc, int size)
185 bzero(fifo, sizeof(struct fifo));
188 if (sc->tty.opened) {
190 * Flush any unread input from the tty buffer.
193 nread = read(sc->tty.fd, flushbuf, sizeof(flushbuf));
194 if (nread != sizeof(flushbuf))
199 * Enable mevent to trigger when new characters are available
202 error = mevent_enable(sc->mev);
208 rxfifo_available(struct uart_softc *sc)
213 return (fifo->num < fifo->size);
217 rxfifo_putchar(struct uart_softc *sc, uint8_t ch)
224 if (fifo->num < fifo->size) {
225 fifo->buf[fifo->windex] = ch;
226 fifo->windex = (fifo->windex + 1) % fifo->size;
228 if (!rxfifo_available(sc)) {
229 if (sc->tty.opened) {
231 * Disable mevent callback if the FIFO is full.
233 error = mevent_disable(sc->mev);
243 rxfifo_getchar(struct uart_softc *sc)
246 int c, error, wasfull;
251 if (!rxfifo_available(sc))
253 c = fifo->buf[fifo->rindex];
254 fifo->rindex = (fifo->rindex + 1) % fifo->size;
257 if (sc->tty.opened) {
258 error = mevent_enable(sc->mev);
268 rxfifo_numchars(struct uart_softc *sc)
270 struct fifo *fifo = &sc->rxfifo;
276 uart_opentty(struct uart_softc *sc)
280 sc->mev = mevent_add(sc->tty.fd, EVF_READ, uart_drain, sc);
281 assert(sc->mev != NULL);
285 modem_status(uint8_t mcr)
289 if (mcr & MCR_LOOPBACK) {
291 * In the loopback mode certain bits from the MCR are
292 * reflected back into MSR.
305 * Always assert DCD and DSR so tty open doesn't block
306 * even if CLOCAL is turned off.
308 msr = MSR_DCD | MSR_DSR;
310 assert((msr & MSR_DELTA_MASK) == 0);
316 * The IIR returns a prioritized interrupt reason:
317 * - receive data available
318 * - transmit holding register empty
319 * - modem status change
321 * Return an interrupt reason if one is available.
324 uart_intr_reason(struct uart_softc *sc)
327 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
329 else if (rxfifo_numchars(sc) > 0 && (sc->ier & IER_ERXRDY) != 0)
331 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
333 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
340 uart_reset(struct uart_softc *sc)
344 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
346 sc->dlh = divisor >> 16;
347 sc->msr = modem_status(sc->mcr);
349 rxfifo_reset(sc, 1); /* no fifo until enabled by software */
353 * Toggle the COM port's intr pin depending on whether or not we have an
354 * interrupt condition to report to the processor.
357 uart_toggle_intr(struct uart_softc *sc)
361 intr_reason = uart_intr_reason(sc);
363 if (intr_reason == IIR_NOPEND)
364 (*sc->intr_deassert)(sc->arg);
366 (*sc->intr_assert)(sc->arg);
370 uart_drain(int fd, enum ev_type ev, void *arg)
372 struct uart_softc *sc;
377 assert(fd == sc->tty.fd);
378 assert(ev == EVF_READ);
381 * This routine is called in the context of the mevent thread
382 * to take out the softc lock to protect against concurrent
383 * access from a vCPU i/o exit
385 pthread_mutex_lock(&sc->mtx);
387 if ((sc->mcr & MCR_LOOPBACK) != 0) {
388 (void) ttyread(&sc->tty);
390 while (rxfifo_available(sc) &&
391 ((ch = ttyread(&sc->tty)) != -1)) {
392 rxfifo_putchar(sc, ch);
394 uart_toggle_intr(sc);
397 pthread_mutex_unlock(&sc->mtx);
401 uart_write(struct uart_softc *sc, int offset, uint8_t value)
406 pthread_mutex_lock(&sc->mtx);
409 * Take care of the special case DLAB accesses first
411 if ((sc->lcr & LCR_DLAB) != 0) {
412 if (offset == REG_DLL) {
417 if (offset == REG_DLH) {
425 if (sc->mcr & MCR_LOOPBACK) {
426 if (rxfifo_putchar(sc, value) != 0)
428 } else if (sc->tty.opened) {
429 ttywrite(&sc->tty, value);
430 } /* else drop on floor */
431 sc->thre_int_pending = true;
435 * Apply mask so that bits 4-7 are 0
436 * Also enables bits 0-3 only if they're 1
438 sc->ier = value & 0x0F;
442 * When moving from FIFO and 16450 mode and vice versa,
443 * the FIFO contents are reset.
445 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
446 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
447 rxfifo_reset(sc, fifosz);
451 * The FCR_ENABLE bit must be '1' for the programming
452 * of other FCR bits to be effective.
454 if ((value & FCR_ENABLE) == 0) {
457 if ((value & FCR_RCV_RST) != 0)
458 rxfifo_reset(sc, FIFOSZ);
461 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
468 /* Apply mask so that bits 5-7 are 0 */
469 sc->mcr = value & 0x1F;
470 msr = modem_status(sc->mcr);
473 * Detect if there has been any change between the
474 * previous and the new value of MSR. If there is
475 * then assert the appropriate MSR delta bit.
477 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
479 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
481 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
483 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
487 * Update the value of MSR while retaining the delta
490 sc->msr &= MSR_DELTA_MASK;
495 * Line status register is not meant to be written to
496 * during normal operation.
501 * As far as I can tell MSR is a read-only register.
512 uart_toggle_intr(sc);
513 pthread_mutex_unlock(&sc->mtx);
517 uart_read(struct uart_softc *sc, int offset)
519 uint8_t iir, intr_reason, reg;
521 pthread_mutex_lock(&sc->mtx);
524 * Take care of the special case DLAB accesses first
526 if ((sc->lcr & LCR_DLAB) != 0) {
527 if (offset == REG_DLL) {
532 if (offset == REG_DLH) {
540 reg = rxfifo_getchar(sc);
546 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
548 intr_reason = uart_intr_reason(sc);
551 * Deal with side effects of reading the IIR register
553 if (intr_reason == IIR_TXRDY)
554 sc->thre_int_pending = false;
567 /* Transmitter is always ready for more data */
568 sc->lsr |= LSR_TEMT | LSR_THRE;
570 /* Check for new receive data */
571 if (rxfifo_numchars(sc) > 0)
572 sc->lsr |= LSR_RXRDY;
574 sc->lsr &= ~LSR_RXRDY;
578 /* The LSR_OE bit is cleared on LSR read */
583 * MSR delta bits are cleared on read
586 sc->msr &= ~MSR_DELTA_MASK;
597 uart_toggle_intr(sc);
598 pthread_mutex_unlock(&sc->mtx);
604 uart_legacy_alloc(int which, int *baseaddr, int *irq)
607 if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
610 uart_lres[which].inuse = true;
611 *baseaddr = uart_lres[which].baseaddr;
612 *irq = uart_lres[which].irq;
618 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
621 struct uart_softc *sc;
623 sc = calloc(1, sizeof(struct uart_softc));
626 sc->intr_assert = intr_assert;
627 sc->intr_deassert = intr_deassert;
629 pthread_mutex_init(&sc->mtx, NULL);
637 uart_tty_backend(struct uart_softc *sc, const char *opts)
644 fd = open(opts, O_RDWR | O_NONBLOCK);
645 if (fd > 0 && isatty(fd)) {
647 sc->tty.opened = true;
655 uart_set_backend(struct uart_softc *sc, const char *opts)
658 #ifndef WITHOUT_CAPSICUM
660 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
668 if (strcmp("stdio", opts) == 0) {
670 sc->tty.fd = STDIN_FILENO;
671 sc->tty.opened = true;
675 } else if (uart_tty_backend(sc, opts) == 0) {
679 /* Make the backend file descriptor non-blocking */
681 retval = fcntl(sc->tty.fd, F_SETFL, O_NONBLOCK);
684 #ifndef WITHOUT_CAPSICUM
685 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ,
687 if (cap_rights_limit(sc->tty.fd, &rights) == -1 &&
689 errx(EX_OSERR, "Unable to apply rights for sandbox");
690 if (cap_ioctls_limit(sc->tty.fd, cmds, nitems(cmds)) == -1 &&
692 errx(EX_OSERR, "Unable to apply rights for sandbox");
694 if (caph_limit_stdin() == -1 && errno != ENOSYS)
696 "Unable to apply rights for sandbox");