2 * Copyright (c) 2012 NetApp, Inc.
3 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <dev/ic/ns16550.h>
35 #ifndef WITHOUT_CAPSICUM
36 #include <sys/capsicum.h>
53 #include "uart_emul.h"
55 #define COM1_BASE 0x3F8
57 #define COM2_BASE 0x2F8
60 #define DEFAULT_RCLK 1843200
61 #define DEFAULT_BAUD 9600
63 #define FCR_RX_MASK 0xC0
68 #define MSR_DELTA_MASK 0x0f
71 #define REG_SCR com_scr
76 static bool uart_stdio; /* stdio in use for i/o */
77 static struct termios tio_stdio_orig;
84 { COM1_BASE, COM1_IRQ, false},
85 { COM2_BASE, COM2_IRQ, false},
88 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
92 int rindex; /* index to read from */
93 int windex; /* index to write to */
94 int num; /* number of characters in the fifo */
95 int size; /* size of the fifo */
100 int fd; /* tty device file descriptor */
101 struct termios tio_orig, tio_new; /* I/O Terminals */
105 pthread_mutex_t mtx; /* protects all softc elements */
106 uint8_t data; /* Data register (R/W) */
107 uint8_t ier; /* Interrupt enable register (R/W) */
108 uint8_t lcr; /* Line control register (R/W) */
109 uint8_t mcr; /* Modem control register (R/W) */
110 uint8_t lsr; /* Line status register (R/W) */
111 uint8_t msr; /* Modem status register (R/W) */
112 uint8_t fcr; /* FIFO control register (W) */
113 uint8_t scr; /* Scratch register (R/W) */
115 uint8_t dll; /* Baudrate divisor latch LSB */
116 uint8_t dlh; /* Baudrate divisor latch MSB */
122 bool thre_int_pending; /* THRE interrupt pending */
125 uart_intr_func_t intr_assert;
126 uart_intr_func_t intr_deassert;
129 static void uart_drain(int fd, enum ev_type ev, void *arg);
135 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
139 ttyopen(struct ttyfd *tf)
142 tcgetattr(tf->fd, &tf->tio_orig);
144 tf->tio_new = tf->tio_orig;
145 cfmakeraw(&tf->tio_new);
146 tf->tio_new.c_cflag |= CLOCAL;
147 tcsetattr(tf->fd, TCSANOW, &tf->tio_new);
149 if (tf->fd == STDIN_FILENO) {
150 tio_stdio_orig = tf->tio_orig;
156 ttyread(struct ttyfd *tf)
160 if (read(tf->fd, &rb, 1) == 1)
167 ttywrite(struct ttyfd *tf, unsigned char wb)
170 (void)write(tf->fd, &wb, 1);
174 rxfifo_reset(struct uart_softc *sc, int size)
182 bzero(fifo, sizeof(struct fifo));
185 if (sc->tty.opened) {
187 * Flush any unread input from the tty buffer.
190 nread = read(sc->tty.fd, flushbuf, sizeof(flushbuf));
191 if (nread != sizeof(flushbuf))
196 * Enable mevent to trigger when new characters are available
199 error = mevent_enable(sc->mev);
205 rxfifo_available(struct uart_softc *sc)
210 return (fifo->num < fifo->size);
214 rxfifo_putchar(struct uart_softc *sc, uint8_t ch)
221 if (fifo->num < fifo->size) {
222 fifo->buf[fifo->windex] = ch;
223 fifo->windex = (fifo->windex + 1) % fifo->size;
225 if (!rxfifo_available(sc)) {
226 if (sc->tty.opened) {
228 * Disable mevent callback if the FIFO is full.
230 error = mevent_disable(sc->mev);
240 rxfifo_getchar(struct uart_softc *sc)
243 int c, error, wasfull;
248 if (!rxfifo_available(sc))
250 c = fifo->buf[fifo->rindex];
251 fifo->rindex = (fifo->rindex + 1) % fifo->size;
254 if (sc->tty.opened) {
255 error = mevent_enable(sc->mev);
265 rxfifo_numchars(struct uart_softc *sc)
267 struct fifo *fifo = &sc->rxfifo;
273 uart_opentty(struct uart_softc *sc)
277 sc->mev = mevent_add(sc->tty.fd, EVF_READ, uart_drain, sc);
278 assert(sc->mev != NULL);
282 modem_status(uint8_t mcr)
286 if (mcr & MCR_LOOPBACK) {
288 * In the loopback mode certain bits from the MCR are
289 * reflected back into MSR.
302 * Always assert DCD and DSR so tty open doesn't block
303 * even if CLOCAL is turned off.
305 msr = MSR_DCD | MSR_DSR;
307 assert((msr & MSR_DELTA_MASK) == 0);
313 * The IIR returns a prioritized interrupt reason:
314 * - receive data available
315 * - transmit holding register empty
316 * - modem status change
318 * Return an interrupt reason if one is available.
321 uart_intr_reason(struct uart_softc *sc)
324 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
326 else if (rxfifo_numchars(sc) > 0 && (sc->ier & IER_ERXRDY) != 0)
328 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
330 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
337 uart_reset(struct uart_softc *sc)
341 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
343 sc->dlh = divisor >> 16;
344 sc->msr = modem_status(sc->mcr);
346 rxfifo_reset(sc, 1); /* no fifo until enabled by software */
350 * Toggle the COM port's intr pin depending on whether or not we have an
351 * interrupt condition to report to the processor.
354 uart_toggle_intr(struct uart_softc *sc)
358 intr_reason = uart_intr_reason(sc);
360 if (intr_reason == IIR_NOPEND)
361 (*sc->intr_deassert)(sc->arg);
363 (*sc->intr_assert)(sc->arg);
367 uart_drain(int fd, enum ev_type ev, void *arg)
369 struct uart_softc *sc;
374 assert(fd == sc->tty.fd);
375 assert(ev == EVF_READ);
378 * This routine is called in the context of the mevent thread
379 * to take out the softc lock to protect against concurrent
380 * access from a vCPU i/o exit
382 pthread_mutex_lock(&sc->mtx);
384 if ((sc->mcr & MCR_LOOPBACK) != 0) {
385 (void) ttyread(&sc->tty);
387 while (rxfifo_available(sc) &&
388 ((ch = ttyread(&sc->tty)) != -1)) {
389 rxfifo_putchar(sc, ch);
391 uart_toggle_intr(sc);
394 pthread_mutex_unlock(&sc->mtx);
398 uart_write(struct uart_softc *sc, int offset, uint8_t value)
403 pthread_mutex_lock(&sc->mtx);
406 * Take care of the special case DLAB accesses first
408 if ((sc->lcr & LCR_DLAB) != 0) {
409 if (offset == REG_DLL) {
414 if (offset == REG_DLH) {
422 if (sc->mcr & MCR_LOOPBACK) {
423 if (rxfifo_putchar(sc, value) != 0)
425 } else if (sc->tty.opened) {
426 ttywrite(&sc->tty, value);
427 } /* else drop on floor */
428 sc->thre_int_pending = true;
432 * Apply mask so that bits 4-7 are 0
433 * Also enables bits 0-3 only if they're 1
435 sc->ier = value & 0x0F;
439 * When moving from FIFO and 16450 mode and vice versa,
440 * the FIFO contents are reset.
442 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
443 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
444 rxfifo_reset(sc, fifosz);
448 * The FCR_ENABLE bit must be '1' for the programming
449 * of other FCR bits to be effective.
451 if ((value & FCR_ENABLE) == 0) {
454 if ((value & FCR_RCV_RST) != 0)
455 rxfifo_reset(sc, FIFOSZ);
458 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
465 /* Apply mask so that bits 5-7 are 0 */
466 sc->mcr = value & 0x1F;
467 msr = modem_status(sc->mcr);
470 * Detect if there has been any change between the
471 * previous and the new value of MSR. If there is
472 * then assert the appropriate MSR delta bit.
474 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
476 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
478 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
480 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
484 * Update the value of MSR while retaining the delta
487 sc->msr &= MSR_DELTA_MASK;
492 * Line status register is not meant to be written to
493 * during normal operation.
498 * As far as I can tell MSR is a read-only register.
509 uart_toggle_intr(sc);
510 pthread_mutex_unlock(&sc->mtx);
514 uart_read(struct uart_softc *sc, int offset)
516 uint8_t iir, intr_reason, reg;
518 pthread_mutex_lock(&sc->mtx);
521 * Take care of the special case DLAB accesses first
523 if ((sc->lcr & LCR_DLAB) != 0) {
524 if (offset == REG_DLL) {
529 if (offset == REG_DLH) {
537 reg = rxfifo_getchar(sc);
543 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
545 intr_reason = uart_intr_reason(sc);
548 * Deal with side effects of reading the IIR register
550 if (intr_reason == IIR_TXRDY)
551 sc->thre_int_pending = false;
564 /* Transmitter is always ready for more data */
565 sc->lsr |= LSR_TEMT | LSR_THRE;
567 /* Check for new receive data */
568 if (rxfifo_numchars(sc) > 0)
569 sc->lsr |= LSR_RXRDY;
571 sc->lsr &= ~LSR_RXRDY;
575 /* The LSR_OE bit is cleared on LSR read */
580 * MSR delta bits are cleared on read
583 sc->msr &= ~MSR_DELTA_MASK;
594 uart_toggle_intr(sc);
595 pthread_mutex_unlock(&sc->mtx);
601 uart_legacy_alloc(int which, int *baseaddr, int *irq)
604 if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
607 uart_lres[which].inuse = true;
608 *baseaddr = uart_lres[which].baseaddr;
609 *irq = uart_lres[which].irq;
615 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
618 struct uart_softc *sc;
620 sc = calloc(1, sizeof(struct uart_softc));
623 sc->intr_assert = intr_assert;
624 sc->intr_deassert = intr_deassert;
626 pthread_mutex_init(&sc->mtx, NULL);
634 uart_tty_backend(struct uart_softc *sc, const char *opts)
641 fd = open(opts, O_RDWR | O_NONBLOCK);
642 if (fd > 0 && isatty(fd)) {
644 sc->tty.opened = true;
652 uart_set_backend(struct uart_softc *sc, const char *opts)
655 #ifndef WITHOUT_CAPSICUM
657 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
658 cap_ioctl_t sicmds[] = { TIOCGETA, TIOCGWINSZ };
666 if (strcmp("stdio", opts) == 0) {
668 sc->tty.fd = STDIN_FILENO;
669 sc->tty.opened = true;
673 } else if (uart_tty_backend(sc, opts) == 0) {
677 /* Make the backend file descriptor non-blocking */
679 retval = fcntl(sc->tty.fd, F_SETFL, O_NONBLOCK);
681 #ifndef WITHOUT_CAPSICUM
682 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ, CAP_WRITE);
683 if (cap_rights_limit(sc->tty.fd, &rights) == -1 && errno != ENOSYS)
684 errx(EX_OSERR, "Unable to apply rights for sandbox");
685 if (cap_ioctls_limit(sc->tty.fd, cmds, nitems(cmds)) == -1 && errno != ENOSYS)
686 errx(EX_OSERR, "Unable to apply rights for sandbox");
688 cap_rights_init(&rights, CAP_FCNTL, CAP_FSTAT, CAP_IOCTL, CAP_READ);
689 if (cap_rights_limit(STDIN_FILENO, &rights) == -1 && errno != ENOSYS)
690 errx(EX_OSERR, "Unable to apply rights for sandbox");
691 if (cap_ioctls_limit(STDIN_FILENO, sicmds, nitems(sicmds)) == -1 && errno != ENOSYS)
692 errx(EX_OSERR, "Unable to apply rights for sandbox");
693 if (cap_fcntls_limit(STDIN_FILENO, CAP_FCNTL_GETFL) == -1 && errno != ENOSYS)
694 errx(EX_OSERR, "Unable to apply rights for sandbox");