2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 NetApp, Inc.
5 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #include <dev/ic/ns16550.h>
37 #ifndef WITHOUT_CAPSICUM
38 #include <sys/capsicum.h>
39 #include <capsicum_helpers.h>
56 #include "uart_emul.h"
59 #define COM1_BASE 0x3F8
61 #define COM2_BASE 0x2F8
64 #define DEFAULT_RCLK 1843200
65 #define DEFAULT_BAUD 9600
67 #define FCR_RX_MASK 0xC0
72 #define MSR_DELTA_MASK 0x0f
75 #define REG_SCR com_scr
80 static bool uart_stdio; /* stdio in use for i/o */
81 static struct termios tio_stdio_orig;
88 { COM1_BASE, COM1_IRQ, false},
89 { COM2_BASE, COM2_IRQ, false},
92 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
96 int rindex; /* index to read from */
97 int windex; /* index to write to */
98 int num; /* number of characters in the fifo */
99 int size; /* size of the fifo */
104 int rfd; /* fd for reading */
105 int wfd; /* fd for writing, may be == rfd */
109 pthread_mutex_t mtx; /* protects all softc elements */
110 uint8_t data; /* Data register (R/W) */
111 uint8_t ier; /* Interrupt enable register (R/W) */
112 uint8_t lcr; /* Line control register (R/W) */
113 uint8_t mcr; /* Modem control register (R/W) */
114 uint8_t lsr; /* Line status register (R/W) */
115 uint8_t msr; /* Modem status register (R/W) */
116 uint8_t fcr; /* FIFO control register (W) */
117 uint8_t scr; /* Scratch register (R/W) */
119 uint8_t dll; /* Baudrate divisor latch LSB */
120 uint8_t dlh; /* Baudrate divisor latch MSB */
126 bool thre_int_pending; /* THRE interrupt pending */
129 uart_intr_func_t intr_assert;
130 uart_intr_func_t intr_deassert;
133 static void uart_drain(int fd, enum ev_type ev, void *arg);
139 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
143 ttyopen(struct ttyfd *tf)
145 struct termios orig, new;
147 tcgetattr(tf->rfd, &orig);
150 new.c_cflag |= CLOCAL;
151 tcsetattr(tf->rfd, TCSANOW, &new);
153 tio_stdio_orig = orig;
160 ttyread(struct ttyfd *tf)
164 if (read(tf->rfd, &rb, 1) == 1)
171 ttywrite(struct ttyfd *tf, unsigned char wb)
174 (void)write(tf->wfd, &wb, 1);
178 rxfifo_reset(struct uart_softc *sc, int size)
186 bzero(fifo, sizeof(struct fifo));
189 if (sc->tty.opened) {
191 * Flush any unread input from the tty buffer.
194 nread = read(sc->tty.rfd, flushbuf, sizeof(flushbuf));
195 if (nread != sizeof(flushbuf))
200 * Enable mevent to trigger when new characters are available
203 error = mevent_enable(sc->mev);
209 rxfifo_available(struct uart_softc *sc)
214 return (fifo->num < fifo->size);
218 rxfifo_putchar(struct uart_softc *sc, uint8_t ch)
225 if (fifo->num < fifo->size) {
226 fifo->buf[fifo->windex] = ch;
227 fifo->windex = (fifo->windex + 1) % fifo->size;
229 if (!rxfifo_available(sc)) {
230 if (sc->tty.opened) {
232 * Disable mevent callback if the FIFO is full.
234 error = mevent_disable(sc->mev);
244 rxfifo_getchar(struct uart_softc *sc)
247 int c, error, wasfull;
252 if (!rxfifo_available(sc))
254 c = fifo->buf[fifo->rindex];
255 fifo->rindex = (fifo->rindex + 1) % fifo->size;
258 if (sc->tty.opened) {
259 error = mevent_enable(sc->mev);
269 rxfifo_numchars(struct uart_softc *sc)
271 struct fifo *fifo = &sc->rxfifo;
277 uart_opentty(struct uart_softc *sc)
281 sc->mev = mevent_add(sc->tty.rfd, EVF_READ, uart_drain, sc);
282 assert(sc->mev != NULL);
286 modem_status(uint8_t mcr)
290 if (mcr & MCR_LOOPBACK) {
292 * In the loopback mode certain bits from the MCR are
293 * reflected back into MSR.
306 * Always assert DCD and DSR so tty open doesn't block
307 * even if CLOCAL is turned off.
309 msr = MSR_DCD | MSR_DSR;
311 assert((msr & MSR_DELTA_MASK) == 0);
317 * The IIR returns a prioritized interrupt reason:
318 * - receive data available
319 * - transmit holding register empty
320 * - modem status change
322 * Return an interrupt reason if one is available.
325 uart_intr_reason(struct uart_softc *sc)
328 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
330 else if (rxfifo_numchars(sc) > 0 && (sc->ier & IER_ERXRDY) != 0)
332 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
334 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
341 uart_reset(struct uart_softc *sc)
345 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
347 sc->dlh = divisor >> 16;
348 sc->msr = modem_status(sc->mcr);
350 rxfifo_reset(sc, 1); /* no fifo until enabled by software */
354 * Toggle the COM port's intr pin depending on whether or not we have an
355 * interrupt condition to report to the processor.
358 uart_toggle_intr(struct uart_softc *sc)
362 intr_reason = uart_intr_reason(sc);
364 if (intr_reason == IIR_NOPEND)
365 (*sc->intr_deassert)(sc->arg);
367 (*sc->intr_assert)(sc->arg);
371 uart_drain(int fd, enum ev_type ev, void *arg)
373 struct uart_softc *sc;
378 assert(fd == sc->tty.rfd);
379 assert(ev == EVF_READ);
382 * This routine is called in the context of the mevent thread
383 * to take out the softc lock to protect against concurrent
384 * access from a vCPU i/o exit
386 pthread_mutex_lock(&sc->mtx);
388 if ((sc->mcr & MCR_LOOPBACK) != 0) {
389 (void) ttyread(&sc->tty);
391 while (rxfifo_available(sc) &&
392 ((ch = ttyread(&sc->tty)) != -1)) {
393 rxfifo_putchar(sc, ch);
395 uart_toggle_intr(sc);
398 pthread_mutex_unlock(&sc->mtx);
402 uart_write(struct uart_softc *sc, int offset, uint8_t value)
407 pthread_mutex_lock(&sc->mtx);
410 * Take care of the special case DLAB accesses first
412 if ((sc->lcr & LCR_DLAB) != 0) {
413 if (offset == REG_DLL) {
418 if (offset == REG_DLH) {
426 if (sc->mcr & MCR_LOOPBACK) {
427 if (rxfifo_putchar(sc, value) != 0)
429 } else if (sc->tty.opened) {
430 ttywrite(&sc->tty, value);
431 } /* else drop on floor */
432 sc->thre_int_pending = true;
435 /* Set pending when IER_ETXRDY is raised (edge-triggered). */
436 if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0)
437 sc->thre_int_pending = true;
439 * Apply mask so that bits 4-7 are 0
440 * Also enables bits 0-3 only if they're 1
442 sc->ier = value & 0x0F;
446 * When moving from FIFO and 16450 mode and vice versa,
447 * the FIFO contents are reset.
449 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
450 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
451 rxfifo_reset(sc, fifosz);
455 * The FCR_ENABLE bit must be '1' for the programming
456 * of other FCR bits to be effective.
458 if ((value & FCR_ENABLE) == 0) {
461 if ((value & FCR_RCV_RST) != 0)
462 rxfifo_reset(sc, FIFOSZ);
465 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
472 /* Apply mask so that bits 5-7 are 0 */
473 sc->mcr = value & 0x1F;
474 msr = modem_status(sc->mcr);
477 * Detect if there has been any change between the
478 * previous and the new value of MSR. If there is
479 * then assert the appropriate MSR delta bit.
481 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
483 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
485 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
487 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
491 * Update the value of MSR while retaining the delta
494 sc->msr &= MSR_DELTA_MASK;
499 * Line status register is not meant to be written to
500 * during normal operation.
505 * As far as I can tell MSR is a read-only register.
516 uart_toggle_intr(sc);
517 pthread_mutex_unlock(&sc->mtx);
521 uart_read(struct uart_softc *sc, int offset)
523 uint8_t iir, intr_reason, reg;
525 pthread_mutex_lock(&sc->mtx);
528 * Take care of the special case DLAB accesses first
530 if ((sc->lcr & LCR_DLAB) != 0) {
531 if (offset == REG_DLL) {
536 if (offset == REG_DLH) {
544 reg = rxfifo_getchar(sc);
550 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
552 intr_reason = uart_intr_reason(sc);
555 * Deal with side effects of reading the IIR register
557 if (intr_reason == IIR_TXRDY)
558 sc->thre_int_pending = false;
571 /* Transmitter is always ready for more data */
572 sc->lsr |= LSR_TEMT | LSR_THRE;
574 /* Check for new receive data */
575 if (rxfifo_numchars(sc) > 0)
576 sc->lsr |= LSR_RXRDY;
578 sc->lsr &= ~LSR_RXRDY;
582 /* The LSR_OE bit is cleared on LSR read */
587 * MSR delta bits are cleared on read
590 sc->msr &= ~MSR_DELTA_MASK;
601 uart_toggle_intr(sc);
602 pthread_mutex_unlock(&sc->mtx);
608 uart_legacy_alloc(int which, int *baseaddr, int *irq)
611 if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
614 uart_lres[which].inuse = true;
615 *baseaddr = uart_lres[which].baseaddr;
616 *irq = uart_lres[which].irq;
622 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
625 struct uart_softc *sc;
627 sc = calloc(1, sizeof(struct uart_softc));
630 sc->intr_assert = intr_assert;
631 sc->intr_deassert = intr_deassert;
633 pthread_mutex_init(&sc->mtx, NULL);
641 uart_stdio_backend(struct uart_softc *sc)
643 #ifndef WITHOUT_CAPSICUM
645 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
651 sc->tty.rfd = STDIN_FILENO;
652 sc->tty.wfd = STDOUT_FILENO;
653 sc->tty.opened = true;
655 if (fcntl(sc->tty.rfd, F_SETFL, O_NONBLOCK) != 0)
657 if (fcntl(sc->tty.wfd, F_SETFL, O_NONBLOCK) != 0)
660 #ifndef WITHOUT_CAPSICUM
661 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ);
662 if (caph_rights_limit(sc->tty.rfd, &rights) == -1)
663 errx(EX_OSERR, "Unable to apply rights for sandbox");
664 if (caph_ioctls_limit(sc->tty.rfd, cmds, nitems(cmds)) == -1)
665 errx(EX_OSERR, "Unable to apply rights for sandbox");
674 uart_tty_backend(struct uart_softc *sc, const char *opts)
676 #ifndef WITHOUT_CAPSICUM
678 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
682 fd = open(opts, O_RDWR | O_NONBLOCK);
691 sc->tty.rfd = sc->tty.wfd = fd;
692 sc->tty.opened = true;
694 #ifndef WITHOUT_CAPSICUM
695 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ, CAP_WRITE);
696 if (caph_rights_limit(fd, &rights) == -1)
697 errx(EX_OSERR, "Unable to apply rights for sandbox");
698 if (caph_ioctls_limit(fd, cmds, nitems(cmds)) == -1)
699 errx(EX_OSERR, "Unable to apply rights for sandbox");
706 uart_set_backend(struct uart_softc *sc, const char *opts)
713 if (strcmp("stdio", opts) == 0)
714 retval = uart_stdio_backend(sc);
716 retval = uart_tty_backend(sc, opts);