2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 NetApp, Inc.
5 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/types.h>
36 #include <dev/ic/ns16550.h>
37 #ifndef WITHOUT_CAPSICUM
38 #include <sys/capsicum.h>
39 #include <capsicum_helpers.h>
56 #include "uart_emul.h"
58 #define COM1_BASE 0x3F8
60 #define COM2_BASE 0x2F8
63 #define DEFAULT_RCLK 1843200
64 #define DEFAULT_BAUD 9600
66 #define FCR_RX_MASK 0xC0
71 #define MSR_DELTA_MASK 0x0f
74 #define REG_SCR com_scr
79 static bool uart_stdio; /* stdio in use for i/o */
80 static struct termios tio_stdio_orig;
87 { COM1_BASE, COM1_IRQ, false},
88 { COM2_BASE, COM2_IRQ, false},
91 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
95 int rindex; /* index to read from */
96 int windex; /* index to write to */
97 int num; /* number of characters in the fifo */
98 int size; /* size of the fifo */
103 int rfd; /* fd for reading */
104 int wfd; /* fd for writing, may be == rfd */
108 pthread_mutex_t mtx; /* protects all softc elements */
109 uint8_t data; /* Data register (R/W) */
110 uint8_t ier; /* Interrupt enable register (R/W) */
111 uint8_t lcr; /* Line control register (R/W) */
112 uint8_t mcr; /* Modem control register (R/W) */
113 uint8_t lsr; /* Line status register (R/W) */
114 uint8_t msr; /* Modem status register (R/W) */
115 uint8_t fcr; /* FIFO control register (W) */
116 uint8_t scr; /* Scratch register (R/W) */
118 uint8_t dll; /* Baudrate divisor latch LSB */
119 uint8_t dlh; /* Baudrate divisor latch MSB */
125 bool thre_int_pending; /* THRE interrupt pending */
128 uart_intr_func_t intr_assert;
129 uart_intr_func_t intr_deassert;
132 static void uart_drain(int fd, enum ev_type ev, void *arg);
138 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
142 ttyopen(struct ttyfd *tf)
144 struct termios orig, new;
146 tcgetattr(tf->rfd, &orig);
149 new.c_cflag |= CLOCAL;
150 tcsetattr(tf->rfd, TCSANOW, &new);
152 tio_stdio_orig = orig;
158 ttyread(struct ttyfd *tf)
162 if (read(tf->rfd, &rb, 1) == 1)
169 ttywrite(struct ttyfd *tf, unsigned char wb)
172 (void)write(tf->wfd, &wb, 1);
176 rxfifo_reset(struct uart_softc *sc, int size)
184 bzero(fifo, sizeof(struct fifo));
187 if (sc->tty.opened) {
189 * Flush any unread input from the tty buffer.
192 nread = read(sc->tty.rfd, flushbuf, sizeof(flushbuf));
193 if (nread != sizeof(flushbuf))
198 * Enable mevent to trigger when new characters are available
201 error = mevent_enable(sc->mev);
207 rxfifo_available(struct uart_softc *sc)
212 return (fifo->num < fifo->size);
216 rxfifo_putchar(struct uart_softc *sc, uint8_t ch)
223 if (fifo->num < fifo->size) {
224 fifo->buf[fifo->windex] = ch;
225 fifo->windex = (fifo->windex + 1) % fifo->size;
227 if (!rxfifo_available(sc)) {
228 if (sc->tty.opened) {
230 * Disable mevent callback if the FIFO is full.
232 error = mevent_disable(sc->mev);
242 rxfifo_getchar(struct uart_softc *sc)
245 int c, error, wasfull;
250 if (!rxfifo_available(sc))
252 c = fifo->buf[fifo->rindex];
253 fifo->rindex = (fifo->rindex + 1) % fifo->size;
256 if (sc->tty.opened) {
257 error = mevent_enable(sc->mev);
267 rxfifo_numchars(struct uart_softc *sc)
269 struct fifo *fifo = &sc->rxfifo;
275 uart_opentty(struct uart_softc *sc)
279 sc->mev = mevent_add(sc->tty.rfd, EVF_READ, uart_drain, sc);
280 assert(sc->mev != NULL);
284 modem_status(uint8_t mcr)
288 if (mcr & MCR_LOOPBACK) {
290 * In the loopback mode certain bits from the MCR are
291 * reflected back into MSR.
304 * Always assert DCD and DSR so tty open doesn't block
305 * even if CLOCAL is turned off.
307 msr = MSR_DCD | MSR_DSR;
309 assert((msr & MSR_DELTA_MASK) == 0);
315 * The IIR returns a prioritized interrupt reason:
316 * - receive data available
317 * - transmit holding register empty
318 * - modem status change
320 * Return an interrupt reason if one is available.
323 uart_intr_reason(struct uart_softc *sc)
326 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
328 else if (rxfifo_numchars(sc) > 0 && (sc->ier & IER_ERXRDY) != 0)
330 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
332 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
339 uart_reset(struct uart_softc *sc)
343 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
345 sc->dlh = divisor >> 16;
346 sc->msr = modem_status(sc->mcr);
348 rxfifo_reset(sc, 1); /* no fifo until enabled by software */
352 * Toggle the COM port's intr pin depending on whether or not we have an
353 * interrupt condition to report to the processor.
356 uart_toggle_intr(struct uart_softc *sc)
360 intr_reason = uart_intr_reason(sc);
362 if (intr_reason == IIR_NOPEND)
363 (*sc->intr_deassert)(sc->arg);
365 (*sc->intr_assert)(sc->arg);
369 uart_drain(int fd, enum ev_type ev, void *arg)
371 struct uart_softc *sc;
376 assert(fd == sc->tty.rfd);
377 assert(ev == EVF_READ);
380 * This routine is called in the context of the mevent thread
381 * to take out the softc lock to protect against concurrent
382 * access from a vCPU i/o exit
384 pthread_mutex_lock(&sc->mtx);
386 if ((sc->mcr & MCR_LOOPBACK) != 0) {
387 (void) ttyread(&sc->tty);
389 while (rxfifo_available(sc) &&
390 ((ch = ttyread(&sc->tty)) != -1)) {
391 rxfifo_putchar(sc, ch);
393 uart_toggle_intr(sc);
396 pthread_mutex_unlock(&sc->mtx);
400 uart_write(struct uart_softc *sc, int offset, uint8_t value)
405 pthread_mutex_lock(&sc->mtx);
408 * Take care of the special case DLAB accesses first
410 if ((sc->lcr & LCR_DLAB) != 0) {
411 if (offset == REG_DLL) {
416 if (offset == REG_DLH) {
424 if (sc->mcr & MCR_LOOPBACK) {
425 if (rxfifo_putchar(sc, value) != 0)
427 } else if (sc->tty.opened) {
428 ttywrite(&sc->tty, value);
429 } /* else drop on floor */
430 sc->thre_int_pending = true;
433 /* Set pending when IER_ETXRDY is raised (edge-triggered). */
434 if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0)
435 sc->thre_int_pending = true;
437 * Apply mask so that bits 4-7 are 0
438 * Also enables bits 0-3 only if they're 1
440 sc->ier = value & 0x0F;
444 * When moving from FIFO and 16450 mode and vice versa,
445 * the FIFO contents are reset.
447 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
448 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
449 rxfifo_reset(sc, fifosz);
453 * The FCR_ENABLE bit must be '1' for the programming
454 * of other FCR bits to be effective.
456 if ((value & FCR_ENABLE) == 0) {
459 if ((value & FCR_RCV_RST) != 0)
460 rxfifo_reset(sc, FIFOSZ);
463 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
470 /* Apply mask so that bits 5-7 are 0 */
471 sc->mcr = value & 0x1F;
472 msr = modem_status(sc->mcr);
475 * Detect if there has been any change between the
476 * previous and the new value of MSR. If there is
477 * then assert the appropriate MSR delta bit.
479 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
481 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
483 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
485 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
489 * Update the value of MSR while retaining the delta
492 sc->msr &= MSR_DELTA_MASK;
497 * Line status register is not meant to be written to
498 * during normal operation.
503 * As far as I can tell MSR is a read-only register.
514 uart_toggle_intr(sc);
515 pthread_mutex_unlock(&sc->mtx);
519 uart_read(struct uart_softc *sc, int offset)
521 uint8_t iir, intr_reason, reg;
523 pthread_mutex_lock(&sc->mtx);
526 * Take care of the special case DLAB accesses first
528 if ((sc->lcr & LCR_DLAB) != 0) {
529 if (offset == REG_DLL) {
534 if (offset == REG_DLH) {
542 reg = rxfifo_getchar(sc);
548 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
550 intr_reason = uart_intr_reason(sc);
553 * Deal with side effects of reading the IIR register
555 if (intr_reason == IIR_TXRDY)
556 sc->thre_int_pending = false;
569 /* Transmitter is always ready for more data */
570 sc->lsr |= LSR_TEMT | LSR_THRE;
572 /* Check for new receive data */
573 if (rxfifo_numchars(sc) > 0)
574 sc->lsr |= LSR_RXRDY;
576 sc->lsr &= ~LSR_RXRDY;
580 /* The LSR_OE bit is cleared on LSR read */
585 * MSR delta bits are cleared on read
588 sc->msr &= ~MSR_DELTA_MASK;
599 uart_toggle_intr(sc);
600 pthread_mutex_unlock(&sc->mtx);
606 uart_legacy_alloc(int which, int *baseaddr, int *irq)
609 if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
612 uart_lres[which].inuse = true;
613 *baseaddr = uart_lres[which].baseaddr;
614 *irq = uart_lres[which].irq;
620 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
623 struct uart_softc *sc;
625 sc = calloc(1, sizeof(struct uart_softc));
628 sc->intr_assert = intr_assert;
629 sc->intr_deassert = intr_deassert;
631 pthread_mutex_init(&sc->mtx, NULL);
639 uart_stdio_backend(struct uart_softc *sc)
641 #ifndef WITHOUT_CAPSICUM
643 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
649 sc->tty.rfd = STDIN_FILENO;
650 sc->tty.wfd = STDOUT_FILENO;
651 sc->tty.opened = true;
653 if (fcntl(sc->tty.rfd, F_SETFL, O_NONBLOCK) != 0)
655 if (fcntl(sc->tty.wfd, F_SETFL, O_NONBLOCK) != 0)
658 #ifndef WITHOUT_CAPSICUM
659 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ);
660 if (caph_rights_limit(sc->tty.rfd, &rights) == -1)
661 errx(EX_OSERR, "Unable to apply rights for sandbox");
662 if (caph_ioctls_limit(sc->tty.rfd, cmds, nitems(cmds)) == -1)
663 errx(EX_OSERR, "Unable to apply rights for sandbox");
672 uart_tty_backend(struct uart_softc *sc, const char *opts)
674 #ifndef WITHOUT_CAPSICUM
676 cap_ioctl_t cmds[] = { TIOCGETA, TIOCSETA, TIOCGWINSZ };
680 fd = open(opts, O_RDWR | O_NONBLOCK);
681 if (fd < 0 || !isatty(fd))
684 sc->tty.rfd = sc->tty.wfd = fd;
685 sc->tty.opened = true;
687 #ifndef WITHOUT_CAPSICUM
688 cap_rights_init(&rights, CAP_EVENT, CAP_IOCTL, CAP_READ, CAP_WRITE);
689 if (caph_rights_limit(fd, &rights) == -1)
690 errx(EX_OSERR, "Unable to apply rights for sandbox");
691 if (caph_ioctls_limit(fd, cmds, nitems(cmds)) == -1)
692 errx(EX_OSERR, "Unable to apply rights for sandbox");
699 uart_set_backend(struct uart_softc *sc, const char *opts)
706 if (strcmp("stdio", opts) == 0)
707 retval = uart_stdio_backend(sc);
709 retval = uart_tty_backend(sc, opts);