2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
41 #include <machine/vmm.h>
50 #define MB (1024 * 1024UL)
58 struct bhyvegc_image *gc_image;
74 uint8_t seq_clock_mode;
88 uint8_t crtc_mode_ctrl;
89 uint8_t crtc_horiz_total;
90 uint8_t crtc_horiz_disp_end;
91 uint8_t crtc_start_horiz_blank;
92 uint8_t crtc_end_horiz_blank;
93 uint8_t crtc_start_horiz_retrace;
94 uint8_t crtc_end_horiz_retrace;
95 uint8_t crtc_vert_total;
96 uint8_t crtc_overflow;
97 uint8_t crtc_present_row_scan;
98 uint8_t crtc_max_scan_line;
99 uint8_t crtc_cursor_start;
100 uint8_t crtc_cursor_on;
101 uint8_t crtc_cursor_end;
102 uint8_t crtc_start_addr_high;
103 uint8_t crtc_start_addr_low;
104 uint16_t crtc_start_addr;
105 uint8_t crtc_cursor_loc_low;
106 uint8_t crtc_cursor_loc_high;
107 uint16_t crtc_cursor_loc;
108 uint8_t crtc_vert_retrace_start;
109 uint8_t crtc_vert_retrace_end;
110 uint8_t crtc_vert_disp_end;
112 uint8_t crtc_underline_loc;
113 uint8_t crtc_start_vert_blank;
114 uint8_t crtc_end_vert_blank;
115 uint8_t crtc_line_compare;
119 * Graphics Controller
123 uint8_t gc_set_reset;
124 uint8_t gc_enb_set_reset;
125 uint8_t gc_color_compare;
128 uint8_t gc_read_map_sel;
130 bool gc_mode_c4; /* chain 4 */
131 bool gc_mode_oe; /* odd/even */
132 uint8_t gc_mode_rm; /* read mode */
133 uint8_t gc_mode_wm; /* write mode */
135 uint8_t gc_misc_gm; /* graphics mode */
136 uint8_t gc_misc_mm; /* memory map */
137 uint8_t gc_color_dont_care;
146 * Attribute Controller
151 uint8_t atc_palette[16];
153 uint8_t atc_overscan_color;
154 uint8_t atc_color_plane_enb;
155 uint8_t atc_horiz_pixel_panning;
156 uint8_t atc_color_select;
157 uint8_t atc_color_select_45;
158 uint8_t atc_color_select_67;
166 uint8_t dac_rd_index;
167 uint8_t dac_rd_subindex;
168 uint8_t dac_wr_index;
169 uint8_t dac_wr_subindex;
170 uint8_t dac_palette[3 * 256];
171 uint32_t dac_palette_rgb[256];
176 vga_in_reset(struct vga_softc *sc)
178 return (((sc->vga_seq.seq_clock_mode & SEQ_CM_SO) != 0) ||
179 ((sc->vga_seq.seq_reset & SEQ_RESET_ASYNC) == 0) ||
180 ((sc->vga_seq.seq_reset & SEQ_RESET_SYNC) == 0) ||
181 ((sc->vga_crtc.crtc_mode_ctrl & CRTC_MC_TE) == 0));
185 vga_check_size(struct bhyvegc *gc, struct vga_softc *sc)
187 int old_width, old_height;
189 if (vga_in_reset(sc))
192 //old_width = sc->gc_width;
193 //old_height = sc->gc_height;
194 old_width = sc->gc_image->width;
195 old_height = sc->gc_image->height;
198 * Horizontal Display End: For text modes this is the number
199 * of characters. For graphics modes this is the number of
200 * pixels per scanlines divided by the number of pixels per
203 sc->gc_width = (sc->vga_crtc.crtc_horiz_disp_end + 1) *
204 sc->vga_seq.seq_cm_dots;
206 sc->gc_height = (sc->vga_crtc.crtc_vert_disp_end |
207 (((sc->vga_crtc.crtc_overflow & CRTC_OF_VDE8) >> CRTC_OF_VDE8_SHIFT) << 8) |
208 (((sc->vga_crtc.crtc_overflow & CRTC_OF_VDE9) >> CRTC_OF_VDE9_SHIFT) << 9)) + 1;
210 if (old_width != sc->gc_width || old_height != sc->gc_height)
211 bhyvegc_resize(gc, sc->gc_width, sc->gc_height);
215 vga_get_pixel(struct vga_softc *sc, int x, int y)
222 offset = (y * sc->gc_width / 8) + (x / 8);
225 data = (((sc->vga_ram[offset + 0 * 64*KB] >> bit) & 0x1) << 0) |
226 (((sc->vga_ram[offset + 1 * 64*KB] >> bit) & 0x1) << 1) |
227 (((sc->vga_ram[offset + 2 * 64*KB] >> bit) & 0x1) << 2) |
228 (((sc->vga_ram[offset + 3 * 64*KB] >> bit) & 0x1) << 3);
230 data &= sc->vga_atc.atc_color_plane_enb;
232 if (sc->vga_atc.atc_mode & ATC_MC_IPS) {
233 idx = sc->vga_atc.atc_palette[data] & 0x0f;
234 idx |= sc->vga_atc.atc_color_select_45;
236 idx = sc->vga_atc.atc_palette[data];
238 idx |= sc->vga_atc.atc_color_select_67;
240 return (sc->vga_dac.dac_palette_rgb[idx]);
244 vga_render_graphics(struct vga_softc *sc)
248 for (y = 0; y < sc->gc_height; y++) {
249 for (x = 0; x < sc->gc_width; x++) {
252 offset = y * sc->gc_width + x;
253 sc->gc_image->data[offset] = vga_get_pixel(sc, x, y);
259 vga_get_text_pixel(struct vga_softc *sc, int x, int y)
261 int dots, offset, bit, font_offset;
262 uint8_t ch, attr, font;
265 dots = sc->vga_seq.seq_cm_dots;
267 offset = 2 * sc->vga_crtc.crtc_start_addr;
268 offset += (y / 16 * sc->gc_width / dots) * 2 + (x / dots) * 2;
270 bit = 7 - (x % dots > 7 ? 7 : x % dots);
272 ch = sc->vga_ram[offset + 0 * 64*KB];
273 attr = sc->vga_ram[offset + 1 * 64*KB];
275 if (sc->vga_crtc.crtc_cursor_on &&
276 (offset == (sc->vga_crtc.crtc_cursor_loc * 2)) &&
277 ((y % 16) >= (sc->vga_crtc.crtc_cursor_start & CRTC_CS_CS)) &&
278 ((y % 16) <= (sc->vga_crtc.crtc_cursor_end & CRTC_CE_CE))) {
279 idx = sc->vga_atc.atc_palette[attr & 0xf];
280 return (sc->vga_dac.dac_palette_rgb[idx]);
283 if ((sc->vga_seq.seq_mm & SEQ_MM_EM) &&
284 sc->vga_seq.seq_cmap_pri_off != sc->vga_seq.seq_cmap_sec_off) {
286 font_offset = sc->vga_seq.seq_cmap_pri_off +
289 font_offset = sc->vga_seq.seq_cmap_sec_off +
293 font_offset = (ch << 5) + y % 16;
296 font = sc->vga_ram[font_offset + 2 * 64*KB];
298 if (font & (1 << bit))
299 idx = sc->vga_atc.atc_palette[attr & 0xf];
301 idx = sc->vga_atc.atc_palette[attr >> 4];
303 return (sc->vga_dac.dac_palette_rgb[idx]);
307 vga_render_text(struct vga_softc *sc)
311 for (y = 0; y < sc->gc_height; y++) {
312 for (x = 0; x < sc->gc_width; x++) {
315 offset = y * sc->gc_width + x;
316 sc->gc_image->data[offset] = vga_get_text_pixel(sc, x, y);
322 vga_render(struct bhyvegc *gc, void *arg)
324 struct vga_softc *sc = arg;
326 vga_check_size(gc, sc);
328 if (vga_in_reset(sc)) {
329 memset(sc->gc_image->data, 0,
330 sc->gc_image->width * sc->gc_image->height *
335 if (sc->vga_gc.gc_misc_gm && (sc->vga_atc.atc_mode & ATC_MC_GA))
336 vga_render_graphics(sc);
342 vga_mem_rd_handler(struct vmctx *ctx, uint64_t addr, void *arg1)
344 struct vga_softc *sc = arg1;
349 switch (sc->vga_gc.gc_misc_mm) {
352 * extended mode: base 0xa0000 size 128k
355 offset &= (128 * KB - 1);
359 * EGA/VGA mode: base 0xa0000 size 64k
362 offset &= (64 * KB - 1);
366 * monochrome text mode: base 0xb0000 size 32kb
371 * color text mode and CGA: base 0xb8000 size 32kb
374 offset &= (32 * KB - 1);
379 sc->vga_gc.gc_latch0 = sc->vga_ram[offset + 0*64*KB];
380 sc->vga_gc.gc_latch1 = sc->vga_ram[offset + 1*64*KB];
381 sc->vga_gc.gc_latch2 = sc->vga_ram[offset + 2*64*KB];
382 sc->vga_gc.gc_latch3 = sc->vga_ram[offset + 3*64*KB];
384 if (sc->vga_gc.gc_mode_rm) {
389 map_sel = sc->vga_gc.gc_read_map_sel;
390 if (sc->vga_gc.gc_mode_oe) {
391 map_sel |= (offset & 1);
395 /* read mode 0: return the byte from the selected plane. */
396 offset += map_sel * 64*KB;
398 return (sc->vga_ram[offset]);
402 vga_mem_wr_handler(struct vmctx *ctx, uint64_t addr, uint8_t val, void *arg1)
404 struct vga_softc *sc = arg1;
405 uint8_t c0, c1, c2, c3;
406 uint8_t m0, m1, m2, m3;
408 uint8_t enb_set_reset;
413 switch (sc->vga_gc.gc_misc_mm) {
416 * extended mode: base 0xa0000 size 128kb
419 offset &= (128 * KB - 1);
423 * EGA/VGA mode: base 0xa0000 size 64kb
426 offset &= (64 * KB - 1);
430 * monochrome text mode: base 0xb0000 size 32kb
435 * color text mode and CGA: base 0xb8000 size 32kb
438 offset &= (32 * KB - 1);
442 set_reset = sc->vga_gc.gc_set_reset;
443 enb_set_reset = sc->vga_gc.gc_enb_set_reset;
445 c0 = sc->vga_gc.gc_latch0;
446 c1 = sc->vga_gc.gc_latch1;
447 c2 = sc->vga_gc.gc_latch2;
448 c3 = sc->vga_gc.gc_latch3;
450 switch (sc->vga_gc.gc_mode_wm) {
453 mask = sc->vga_gc.gc_bit_mask;
455 val = (val >> sc->vga_gc.gc_rotate) |
456 (val << (8 - sc->vga_gc.gc_rotate));
458 switch (sc->vga_gc.gc_op) {
459 case 0x00: /* replace */
460 m0 = (set_reset & 1) ? mask : 0x00;
461 m1 = (set_reset & 2) ? mask : 0x00;
462 m2 = (set_reset & 4) ? mask : 0x00;
463 m3 = (set_reset & 8) ? mask : 0x00;
465 c0 = (enb_set_reset & 1) ? (c0 & ~mask) : (val & mask);
466 c1 = (enb_set_reset & 2) ? (c1 & ~mask) : (val & mask);
467 c2 = (enb_set_reset & 4) ? (c2 & ~mask) : (val & mask);
468 c3 = (enb_set_reset & 8) ? (c3 & ~mask) : (val & mask);
476 m0 = set_reset & 1 ? 0xff : ~mask;
477 m1 = set_reset & 2 ? 0xff : ~mask;
478 m2 = set_reset & 4 ? 0xff : ~mask;
479 m3 = set_reset & 8 ? 0xff : ~mask;
481 c0 = enb_set_reset & 1 ? c0 & m0 : val & m0;
482 c1 = enb_set_reset & 2 ? c1 & m1 : val & m1;
483 c2 = enb_set_reset & 4 ? c2 & m2 : val & m2;
484 c3 = enb_set_reset & 8 ? c3 & m3 : val & m3;
487 m0 = set_reset & 1 ? mask : 0x00;
488 m1 = set_reset & 2 ? mask : 0x00;
489 m2 = set_reset & 4 ? mask : 0x00;
490 m3 = set_reset & 8 ? mask : 0x00;
492 c0 = enb_set_reset & 1 ? c0 | m0 : val | m0;
493 c1 = enb_set_reset & 2 ? c1 | m1 : val | m1;
494 c2 = enb_set_reset & 4 ? c2 | m2 : val | m2;
495 c3 = enb_set_reset & 8 ? c3 | m3 : val | m3;
498 m0 = set_reset & 1 ? mask : 0x00;
499 m1 = set_reset & 2 ? mask : 0x00;
500 m2 = set_reset & 4 ? mask : 0x00;
501 m3 = set_reset & 8 ? mask : 0x00;
503 c0 = enb_set_reset & 1 ? c0 ^ m0 : val ^ m0;
504 c1 = enb_set_reset & 2 ? c1 ^ m1 : val ^ m1;
505 c2 = enb_set_reset & 4 ? c2 ^ m2 : val ^ m2;
506 c3 = enb_set_reset & 8 ? c3 ^ m3 : val ^ m3;
515 mask = sc->vga_gc.gc_bit_mask;
517 switch (sc->vga_gc.gc_op) {
518 case 0x00: /* replace */
519 m0 = (val & 1 ? 0xff : 0x00) & mask;
520 m1 = (val & 2 ? 0xff : 0x00) & mask;
521 m2 = (val & 4 ? 0xff : 0x00) & mask;
522 m3 = (val & 8 ? 0xff : 0x00) & mask;
535 m0 = (val & 1 ? 0xff : 0x00) | ~mask;
536 m1 = (val & 2 ? 0xff : 0x00) | ~mask;
537 m2 = (val & 4 ? 0xff : 0x00) | ~mask;
538 m3 = (val & 8 ? 0xff : 0x00) | ~mask;
546 m0 = (val & 1 ? 0xff : 0x00) & mask;
547 m1 = (val & 2 ? 0xff : 0x00) & mask;
548 m2 = (val & 4 ? 0xff : 0x00) & mask;
549 m3 = (val & 8 ? 0xff : 0x00) & mask;
557 m0 = (val & 1 ? 0xff : 0x00) & mask;
558 m1 = (val & 2 ? 0xff : 0x00) & mask;
559 m2 = (val & 4 ? 0xff : 0x00) & mask;
560 m3 = (val & 8 ? 0xff : 0x00) & mask;
571 mask = sc->vga_gc.gc_bit_mask & val;
573 val = (val >> sc->vga_gc.gc_rotate) |
574 (val << (8 - sc->vga_gc.gc_rotate));
576 switch (sc->vga_gc.gc_op) {
577 case 0x00: /* replace */
578 m0 = (set_reset & 1 ? 0xff : 0x00) & mask;
579 m1 = (set_reset & 2 ? 0xff : 0x00) & mask;
580 m2 = (set_reset & 4 ? 0xff : 0x00) & mask;
581 m3 = (set_reset & 8 ? 0xff : 0x00) & mask;
594 m0 = (set_reset & 1 ? 0xff : 0x00) | ~mask;
595 m1 = (set_reset & 2 ? 0xff : 0x00) | ~mask;
596 m2 = (set_reset & 4 ? 0xff : 0x00) | ~mask;
597 m3 = (set_reset & 8 ? 0xff : 0x00) | ~mask;
605 m0 = (set_reset & 1 ? 0xff : 0x00) & mask;
606 m1 = (set_reset & 2 ? 0xff : 0x00) & mask;
607 m2 = (set_reset & 4 ? 0xff : 0x00) & mask;
608 m3 = (set_reset & 8 ? 0xff : 0x00) & mask;
616 m0 = (set_reset & 1 ? 0xff : 0x00) & mask;
617 m1 = (set_reset & 2 ? 0xff : 0x00) & mask;
618 m2 = (set_reset & 4 ? 0xff : 0x00) & mask;
619 m3 = (set_reset & 8 ? 0xff : 0x00) & mask;
630 if (sc->vga_gc.gc_mode_oe) {
633 if (sc->vga_seq.seq_map_mask & 2)
634 sc->vga_ram[offset + 1*64*KB] = c1;
635 if (sc->vga_seq.seq_map_mask & 8)
636 sc->vga_ram[offset + 3*64*KB] = c3;
638 if (sc->vga_seq.seq_map_mask & 1)
639 sc->vga_ram[offset + 0*64*KB] = c0;
640 if (sc->vga_seq.seq_map_mask & 4)
641 sc->vga_ram[offset + 2*64*KB] = c2;
644 if (sc->vga_seq.seq_map_mask & 1)
645 sc->vga_ram[offset + 0*64*KB] = c0;
646 if (sc->vga_seq.seq_map_mask & 2)
647 sc->vga_ram[offset + 1*64*KB] = c1;
648 if (sc->vga_seq.seq_map_mask & 4)
649 sc->vga_ram[offset + 2*64*KB] = c2;
650 if (sc->vga_seq.seq_map_mask & 8)
651 sc->vga_ram[offset + 3*64*KB] = c3;
656 vga_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
657 int size, uint64_t *val, void *arg1, long arg2)
659 if (dir == MEM_F_WRITE) {
662 vga_mem_wr_handler(ctx, addr, *val, arg1);
665 vga_mem_wr_handler(ctx, addr, *val, arg1);
666 vga_mem_wr_handler(ctx, addr + 1, *val >> 8, arg1);
669 vga_mem_wr_handler(ctx, addr, *val, arg1);
670 vga_mem_wr_handler(ctx, addr + 1, *val >> 8, arg1);
671 vga_mem_wr_handler(ctx, addr + 2, *val >> 16, arg1);
672 vga_mem_wr_handler(ctx, addr + 3, *val >> 24, arg1);
675 vga_mem_wr_handler(ctx, addr, *val, arg1);
676 vga_mem_wr_handler(ctx, addr + 1, *val >> 8, arg1);
677 vga_mem_wr_handler(ctx, addr + 2, *val >> 16, arg1);
678 vga_mem_wr_handler(ctx, addr + 3, *val >> 24, arg1);
679 vga_mem_wr_handler(ctx, addr + 4, *val >> 32, arg1);
680 vga_mem_wr_handler(ctx, addr + 5, *val >> 40, arg1);
681 vga_mem_wr_handler(ctx, addr + 6, *val >> 48, arg1);
682 vga_mem_wr_handler(ctx, addr + 7, *val >> 56, arg1);
688 *val = vga_mem_rd_handler(ctx, addr, arg1);
691 *val = vga_mem_rd_handler(ctx, addr, arg1);
692 *val |= vga_mem_rd_handler(ctx, addr + 1, arg1) << 8;
695 *val = vga_mem_rd_handler(ctx, addr, arg1);
696 *val |= vga_mem_rd_handler(ctx, addr + 1, arg1) << 8;
697 *val |= vga_mem_rd_handler(ctx, addr + 2, arg1) << 16;
698 *val |= vga_mem_rd_handler(ctx, addr + 3, arg1) << 24;
701 *val = vga_mem_rd_handler(ctx, addr, arg1);
702 *val |= vga_mem_rd_handler(ctx, addr + 1, arg1) << 8;
703 *val |= vga_mem_rd_handler(ctx, addr + 2, arg1) << 16;
704 *val |= vga_mem_rd_handler(ctx, addr + 3, arg1) << 24;
705 *val |= vga_mem_rd_handler(ctx, addr + 4, arg1) << 32;
706 *val |= vga_mem_rd_handler(ctx, addr + 5, arg1) << 40;
707 *val |= vga_mem_rd_handler(ctx, addr + 6, arg1) << 48;
708 *val |= vga_mem_rd_handler(ctx, addr + 7, arg1) << 56;
717 vga_port_in_handler(struct vmctx *ctx, int in, int port, int bytes,
718 uint8_t *val, void *arg)
720 struct vga_softc *sc = arg;
723 case CRTC_IDX_MONO_PORT:
724 case CRTC_IDX_COLOR_PORT:
725 *val = sc->vga_crtc.crtc_index;
727 case CRTC_DATA_MONO_PORT:
728 case CRTC_DATA_COLOR_PORT:
729 switch (sc->vga_crtc.crtc_index) {
730 case CRTC_HORIZ_TOTAL:
731 *val = sc->vga_crtc.crtc_horiz_total;
733 case CRTC_HORIZ_DISP_END:
734 *val = sc->vga_crtc.crtc_horiz_disp_end;
736 case CRTC_START_HORIZ_BLANK:
737 *val = sc->vga_crtc.crtc_start_horiz_blank;
739 case CRTC_END_HORIZ_BLANK:
740 *val = sc->vga_crtc.crtc_end_horiz_blank;
742 case CRTC_START_HORIZ_RETRACE:
743 *val = sc->vga_crtc.crtc_start_horiz_retrace;
745 case CRTC_END_HORIZ_RETRACE:
746 *val = sc->vga_crtc.crtc_end_horiz_retrace;
748 case CRTC_VERT_TOTAL:
749 *val = sc->vga_crtc.crtc_vert_total;
752 *val = sc->vga_crtc.crtc_overflow;
754 case CRTC_PRESET_ROW_SCAN:
755 *val = sc->vga_crtc.crtc_present_row_scan;
757 case CRTC_MAX_SCAN_LINE:
758 *val = sc->vga_crtc.crtc_max_scan_line;
760 case CRTC_CURSOR_START:
761 *val = sc->vga_crtc.crtc_cursor_start;
763 case CRTC_CURSOR_END:
764 *val = sc->vga_crtc.crtc_cursor_end;
766 case CRTC_START_ADDR_HIGH:
767 *val = sc->vga_crtc.crtc_start_addr_high;
769 case CRTC_START_ADDR_LOW:
770 *val = sc->vga_crtc.crtc_start_addr_low;
772 case CRTC_CURSOR_LOC_HIGH:
773 *val = sc->vga_crtc.crtc_cursor_loc_high;
775 case CRTC_CURSOR_LOC_LOW:
776 *val = sc->vga_crtc.crtc_cursor_loc_low;
778 case CRTC_VERT_RETRACE_START:
779 *val = sc->vga_crtc.crtc_vert_retrace_start;
781 case CRTC_VERT_RETRACE_END:
782 *val = sc->vga_crtc.crtc_vert_retrace_end;
784 case CRTC_VERT_DISP_END:
785 *val = sc->vga_crtc.crtc_vert_disp_end;
788 *val = sc->vga_crtc.crtc_offset;
790 case CRTC_UNDERLINE_LOC:
791 *val = sc->vga_crtc.crtc_underline_loc;
793 case CRTC_START_VERT_BLANK:
794 *val = sc->vga_crtc.crtc_start_vert_blank;
796 case CRTC_END_VERT_BLANK:
797 *val = sc->vga_crtc.crtc_end_vert_blank;
799 case CRTC_MODE_CONTROL:
800 *val = sc->vga_crtc.crtc_mode_ctrl;
802 case CRTC_LINE_COMPARE:
803 *val = sc->vga_crtc.crtc_line_compare;
806 //printf("XXX VGA CRTC: inb 0x%04x at index %d\n", port, sc->vga_crtc.crtc_index);
812 *val = sc->vga_atc.atc_index;
815 switch (sc->vga_atc.atc_index) {
816 case ATC_PALETTE0 ... ATC_PALETTE15:
817 *val = sc->vga_atc.atc_palette[sc->vga_atc.atc_index];
819 case ATC_MODE_CONTROL:
820 *val = sc->vga_atc.atc_mode;
822 case ATC_OVERSCAN_COLOR:
823 *val = sc->vga_atc.atc_overscan_color;
825 case ATC_COLOR_PLANE_ENABLE:
826 *val = sc->vga_atc.atc_color_plane_enb;
828 case ATC_HORIZ_PIXEL_PANNING:
829 *val = sc->vga_atc.atc_horiz_pixel_panning;
831 case ATC_COLOR_SELECT:
832 *val = sc->vga_atc.atc_color_select;
835 //printf("XXX VGA ATC inb 0x%04x at index %d\n", port , sc->vga_atc.atc_index);
841 *val = sc->vga_seq.seq_index;
844 switch (sc->vga_seq.seq_index) {
846 *val = sc->vga_seq.seq_reset;
848 case SEQ_CLOCKING_MODE:
849 *val = sc->vga_seq.seq_clock_mode;
852 *val = sc->vga_seq.seq_map_mask;
854 case SEQ_CHAR_MAP_SELECT:
855 *val = sc->vga_seq.seq_cmap_sel;
857 case SEQ_MEMORY_MODE:
858 *val = sc->vga_seq.seq_mm;
861 //printf("XXX VGA SEQ: inb 0x%04x at index %d\n", port, sc->vga_seq.seq_index);
867 *val = sc->vga_dac.dac_palette[3 * sc->vga_dac.dac_rd_index +
868 sc->vga_dac.dac_rd_subindex];
869 sc->vga_dac.dac_rd_subindex++;
870 if (sc->vga_dac.dac_rd_subindex == 3) {
871 sc->vga_dac.dac_rd_index++;
872 sc->vga_dac.dac_rd_subindex = 0;
876 *val = sc->vga_gc.gc_index;
879 switch (sc->vga_gc.gc_index) {
881 *val = sc->vga_gc.gc_set_reset;
883 case GC_ENABLE_SET_RESET:
884 *val = sc->vga_gc.gc_enb_set_reset;
886 case GC_COLOR_COMPARE:
887 *val = sc->vga_gc.gc_color_compare;
890 *val = sc->vga_gc.gc_rotate;
892 case GC_READ_MAP_SELECT:
893 *val = sc->vga_gc.gc_read_map_sel;
896 *val = sc->vga_gc.gc_mode;
898 case GC_MISCELLANEOUS:
899 *val = sc->vga_gc.gc_misc;
901 case GC_COLOR_DONT_CARE:
902 *val = sc->vga_gc.gc_color_dont_care;
905 *val = sc->vga_gc.gc_bit_mask;
908 //printf("XXX VGA GC: inb 0x%04x at index %d\n", port, sc->vga_crtc.crtc_index);
913 case GEN_MISC_OUTPUT_PORT:
916 case GEN_INPUT_STS0_PORT:
919 case GEN_INPUT_STS1_MONO_PORT:
920 case GEN_INPUT_STS1_COLOR_PORT:
921 sc->vga_atc.atc_flipflop = 0;
922 sc->vga_sts1 = GEN_IS1_VR | GEN_IS1_DE;
923 //sc->vga_sts1 ^= (GEN_IS1_VR | GEN_IS1_DE);
926 case GEN_FEATURE_CTRL_PORT:
927 // OpenBSD calls this with bytes = 1
935 printf("XXX vga_port_in_handler() unhandled port 0x%x\n", port);
944 vga_port_out_handler(struct vmctx *ctx, int in, int port, int bytes,
945 uint8_t val, void *arg)
947 struct vga_softc *sc = arg;
950 case CRTC_IDX_MONO_PORT:
951 case CRTC_IDX_COLOR_PORT:
952 sc->vga_crtc.crtc_index = val;
954 case CRTC_DATA_MONO_PORT:
955 case CRTC_DATA_COLOR_PORT:
956 switch (sc->vga_crtc.crtc_index) {
957 case CRTC_HORIZ_TOTAL:
958 sc->vga_crtc.crtc_horiz_total = val;
960 case CRTC_HORIZ_DISP_END:
961 sc->vga_crtc.crtc_horiz_disp_end = val;
963 case CRTC_START_HORIZ_BLANK:
964 sc->vga_crtc.crtc_start_horiz_blank = val;
966 case CRTC_END_HORIZ_BLANK:
967 sc->vga_crtc.crtc_end_horiz_blank = val;
969 case CRTC_START_HORIZ_RETRACE:
970 sc->vga_crtc.crtc_start_horiz_retrace = val;
972 case CRTC_END_HORIZ_RETRACE:
973 sc->vga_crtc.crtc_end_horiz_retrace = val;
975 case CRTC_VERT_TOTAL:
976 sc->vga_crtc.crtc_vert_total = val;
979 sc->vga_crtc.crtc_overflow = val;
981 case CRTC_PRESET_ROW_SCAN:
982 sc->vga_crtc.crtc_present_row_scan = val;
984 case CRTC_MAX_SCAN_LINE:
985 sc->vga_crtc.crtc_max_scan_line = val;
987 case CRTC_CURSOR_START:
988 sc->vga_crtc.crtc_cursor_start = val;
989 sc->vga_crtc.crtc_cursor_on = (val & CRTC_CS_CO) == 0;
991 case CRTC_CURSOR_END:
992 sc->vga_crtc.crtc_cursor_end = val;
994 case CRTC_START_ADDR_HIGH:
995 sc->vga_crtc.crtc_start_addr_high = val;
996 sc->vga_crtc.crtc_start_addr &= 0x00ff;
997 sc->vga_crtc.crtc_start_addr |= (val << 8);
999 case CRTC_START_ADDR_LOW:
1000 sc->vga_crtc.crtc_start_addr_low = val;
1001 sc->vga_crtc.crtc_start_addr &= 0xff00;
1002 sc->vga_crtc.crtc_start_addr |= (val & 0xff);
1004 case CRTC_CURSOR_LOC_HIGH:
1005 sc->vga_crtc.crtc_cursor_loc_high = val;
1006 sc->vga_crtc.crtc_cursor_loc &= 0x00ff;
1007 sc->vga_crtc.crtc_cursor_loc |= (val << 8);
1009 case CRTC_CURSOR_LOC_LOW:
1010 sc->vga_crtc.crtc_cursor_loc_low = val;
1011 sc->vga_crtc.crtc_cursor_loc &= 0xff00;
1012 sc->vga_crtc.crtc_cursor_loc |= (val & 0xff);
1014 case CRTC_VERT_RETRACE_START:
1015 sc->vga_crtc.crtc_vert_retrace_start = val;
1017 case CRTC_VERT_RETRACE_END:
1018 sc->vga_crtc.crtc_vert_retrace_end = val;
1020 case CRTC_VERT_DISP_END:
1021 sc->vga_crtc.crtc_vert_disp_end = val;
1024 sc->vga_crtc.crtc_offset = val;
1026 case CRTC_UNDERLINE_LOC:
1027 sc->vga_crtc.crtc_underline_loc = val;
1029 case CRTC_START_VERT_BLANK:
1030 sc->vga_crtc.crtc_start_vert_blank = val;
1032 case CRTC_END_VERT_BLANK:
1033 sc->vga_crtc.crtc_end_vert_blank = val;
1035 case CRTC_MODE_CONTROL:
1036 sc->vga_crtc.crtc_mode_ctrl = val;
1038 case CRTC_LINE_COMPARE:
1039 sc->vga_crtc.crtc_line_compare = val;
1042 //printf("XXX VGA CRTC: outb 0x%04x, 0x%02x at index %d\n", port, val, sc->vga_crtc.crtc_index);
1048 if (sc->vga_atc.atc_flipflop == 0) {
1049 if (sc->vga_atc.atc_index & 0x20)
1051 sc->vga_atc.atc_index = val & ATC_IDX_MASK;
1053 switch (sc->vga_atc.atc_index) {
1054 case ATC_PALETTE0 ... ATC_PALETTE15:
1055 sc->vga_atc.atc_palette[sc->vga_atc.atc_index] = val & 0x3f;
1057 case ATC_MODE_CONTROL:
1058 sc->vga_atc.atc_mode = val;
1060 case ATC_OVERSCAN_COLOR:
1061 sc->vga_atc.atc_overscan_color = val;
1063 case ATC_COLOR_PLANE_ENABLE:
1064 sc->vga_atc.atc_color_plane_enb = val;
1066 case ATC_HORIZ_PIXEL_PANNING:
1067 sc->vga_atc.atc_horiz_pixel_panning = val;
1069 case ATC_COLOR_SELECT:
1070 sc->vga_atc.atc_color_select = val;
1071 sc->vga_atc.atc_color_select_45 =
1072 (val & ATC_CS_C45) << 4;
1073 sc->vga_atc.atc_color_select_67 =
1074 ((val & ATC_CS_C67) >> 2) << 6;
1077 //printf("XXX VGA ATC: outb 0x%04x, 0x%02x at index %d\n", port, val, sc->vga_atc.atc_index);
1082 sc->vga_atc.atc_flipflop ^= 1;
1087 sc->vga_seq.seq_index = val & 0x1f;
1090 switch (sc->vga_seq.seq_index) {
1092 sc->vga_seq.seq_reset = val;
1094 case SEQ_CLOCKING_MODE:
1095 sc->vga_seq.seq_clock_mode = val;
1096 sc->vga_seq.seq_cm_dots = (val & SEQ_CM_89) ? 8 : 9;
1099 sc->vga_seq.seq_map_mask = val;
1101 case SEQ_CHAR_MAP_SELECT:
1102 sc->vga_seq.seq_cmap_sel = val;
1104 sc->vga_seq.seq_cmap_pri_off = ((((val & SEQ_CMS_SA) >> SEQ_CMS_SA_SHIFT) * 2) + ((val & SEQ_CMS_SAH) >> SEQ_CMS_SAH_SHIFT)) * 8 * KB;
1105 sc->vga_seq.seq_cmap_sec_off = ((((val & SEQ_CMS_SB) >> SEQ_CMS_SB_SHIFT) * 2) + ((val & SEQ_CMS_SBH) >> SEQ_CMS_SBH_SHIFT)) * 8 * KB;
1107 case SEQ_MEMORY_MODE:
1108 sc->vga_seq.seq_mm = val;
1109 /* Windows queries Chain4 */
1110 //assert((sc->vga_seq.seq_mm & SEQ_MM_C4) == 0);
1113 //printf("XXX VGA SEQ: outb 0x%04x, 0x%02x at index %d\n", port, val, sc->vga_seq.seq_index);
1120 case DAC_IDX_RD_PORT:
1121 sc->vga_dac.dac_rd_index = val;
1122 sc->vga_dac.dac_rd_subindex = 0;
1124 case DAC_IDX_WR_PORT:
1125 sc->vga_dac.dac_wr_index = val;
1126 sc->vga_dac.dac_wr_subindex = 0;
1129 sc->vga_dac.dac_palette[3 * sc->vga_dac.dac_wr_index +
1130 sc->vga_dac.dac_wr_subindex] = val;
1131 sc->vga_dac.dac_wr_subindex++;
1132 if (sc->vga_dac.dac_wr_subindex == 3) {
1133 sc->vga_dac.dac_palette_rgb[sc->vga_dac.dac_wr_index] =
1134 ((((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 0] << 2) |
1135 ((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 0] & 0x1) << 1) |
1136 (sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 0] & 0x1)) << 16) |
1137 (((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 1] << 2) |
1138 ((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 1] & 0x1) << 1) |
1139 (sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 1] & 0x1)) << 8) |
1140 (((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 2] << 2) |
1141 ((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 2] & 0x1) << 1) |
1142 (sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 2] & 0x1)) << 0));
1144 sc->vga_dac.dac_wr_index++;
1145 sc->vga_dac.dac_wr_subindex = 0;
1149 sc->vga_gc.gc_index = val;
1152 switch (sc->vga_gc.gc_index) {
1154 sc->vga_gc.gc_set_reset = val;
1156 case GC_ENABLE_SET_RESET:
1157 sc->vga_gc.gc_enb_set_reset = val;
1159 case GC_COLOR_COMPARE:
1160 sc->vga_gc.gc_color_compare = val;
1162 case GC_DATA_ROTATE:
1163 sc->vga_gc.gc_rotate = val;
1164 sc->vga_gc.gc_op = (val >> 3) & 0x3;
1166 case GC_READ_MAP_SELECT:
1167 sc->vga_gc.gc_read_map_sel = val;
1170 sc->vga_gc.gc_mode = val;
1171 sc->vga_gc.gc_mode_c4 = (val & GC_MODE_C4) != 0;
1172 assert(!sc->vga_gc.gc_mode_c4);
1173 sc->vga_gc.gc_mode_oe = (val & GC_MODE_OE) != 0;
1174 sc->vga_gc.gc_mode_rm = (val >> 3) & 0x1;
1175 sc->vga_gc.gc_mode_wm = val & 0x3;
1178 sc->gc_image->vgamode = 1;
1180 case GC_MISCELLANEOUS:
1181 sc->vga_gc.gc_misc = val;
1182 sc->vga_gc.gc_misc_gm = val & GC_MISC_GM;
1183 sc->vga_gc.gc_misc_mm = (val & GC_MISC_MM) >>
1186 case GC_COLOR_DONT_CARE:
1187 sc->vga_gc.gc_color_dont_care = val;
1190 sc->vga_gc.gc_bit_mask = val;
1193 //printf("XXX VGA GC: outb 0x%04x, 0x%02x at index %d\n", port, val, sc->vga_gc.gc_index);
1198 case GEN_INPUT_STS0_PORT:
1199 /* write to Miscellaneous Output Register */
1202 case GEN_INPUT_STS1_MONO_PORT:
1203 case GEN_INPUT_STS1_COLOR_PORT:
1204 /* write to Feature Control Register */
1209 printf("XXX vga_port_out_handler() unhandled port 0x%x, val 0x%x\n", port, val);
1217 vga_port_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1218 uint32_t *eax, void *arg)
1227 error = vga_port_in_handler(ctx, in, port, 1,
1234 error = vga_port_out_handler(ctx, in, port, 1,
1241 error = vga_port_in_handler(ctx, in, port, 1,
1246 error = vga_port_in_handler(ctx, in, port + 1, 1,
1249 *eax |= (val & 0xff) << 8;
1253 error = vga_port_out_handler(ctx, in, port, 1,
1255 val = (*eax >> 8) & 0xff;
1256 error =vga_port_out_handler(ctx, in, port + 1, 1,
1269 vga_init(int io_only)
1271 struct inout_port iop;
1272 struct vga_softc *sc;
1275 sc = calloc(1, sizeof(struct vga_softc));
1277 bzero(&iop, sizeof(struct inout_port));
1279 for (port = VGA_IOPORT_START; port <= VGA_IOPORT_END; port++) {
1282 iop.flags = IOPORT_F_INOUT;
1283 iop.handler = vga_port_handler;
1286 error = register_inout(&iop);
1290 sc->gc_image = console_get_image();
1292 /* only handle io ports; vga graphics is disabled */
1296 sc->mr.name = "VGA memory";
1297 sc->mr.flags = MEM_F_RW;
1298 sc->mr.base = 640 * KB;
1299 sc->mr.size = 128 * KB;
1300 sc->mr.handler = vga_mem_handler;
1302 error = register_mem_fallback(&sc->mr);
1305 sc->vga_ram = malloc(256 * KB);
1306 memset(sc->vga_ram, 0, 256 * KB);
1309 static uint8_t palette[] = {
1310 0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a,
1311 0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x2a,0x00, 0x2a,0x2a,0x2a,
1312 0x00,0x00,0x15, 0x00,0x00,0x3f, 0x00,0x2a,0x15, 0x00,0x2a,0x3f,
1313 0x2a,0x00,0x15, 0x2a,0x00,0x3f, 0x2a,0x2a,0x15, 0x2a,0x2a,0x3f,
1317 memcpy(sc->vga_dac.dac_palette, palette, 16 * 3 * sizeof (uint8_t));
1318 for (i = 0; i < 16; i++) {
1319 sc->vga_dac.dac_palette_rgb[i] =
1320 ((((sc->vga_dac.dac_palette[3*i + 0] << 2) |
1321 ((sc->vga_dac.dac_palette[3*i + 0] & 0x1) << 1) |
1322 (sc->vga_dac.dac_palette[3*i + 0] & 0x1)) << 16) |
1323 (((sc->vga_dac.dac_palette[3*i + 1] << 2) |
1324 ((sc->vga_dac.dac_palette[3*i + 1] & 0x1) << 1) |
1325 (sc->vga_dac.dac_palette[3*i + 1] & 0x1)) << 8) |
1326 (((sc->vga_dac.dac_palette[3*i + 2] << 2) |
1327 ((sc->vga_dac.dac_palette[3*i + 2] & 0x1) << 1) |
1328 (sc->vga_dac.dac_palette[3*i + 2] & 0x1)) << 0));