2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #define VGA_IOPORT_START 0x3c0
35 #define VGA_IOPORT_END 0x3df
37 /* General registers */
38 #define GEN_INPUT_STS0_PORT 0x3c2
39 #define GEN_FEATURE_CTRL_PORT 0x3ca
40 #define GEN_MISC_OUTPUT_PORT 0x3cc
41 #define GEN_INPUT_STS1_MONO_PORT 0x3ba
42 #define GEN_INPUT_STS1_COLOR_PORT 0x3da
43 #define GEN_IS1_VR 0x08 /* Vertical retrace */
44 #define GEN_IS1_DE 0x01 /* Display enable not */
46 /* Attribute controller registers. */
47 #define ATC_IDX_PORT 0x3c0
48 #define ATC_DATA_PORT 0x3c1
50 #define ATC_IDX_MASK 0x1f
51 #define ATC_PALETTE0 0
52 #define ATC_PALETTE15 15
53 #define ATC_MODE_CONTROL 16
54 #define ATC_MC_IPS 0x80 /* Internal palette size */
55 #define ATC_MC_GA 0x01 /* Graphics/alphanumeric */
56 #define ATC_OVERSCAN_COLOR 17
57 #define ATC_COLOR_PLANE_ENABLE 18
58 #define ATC_HORIZ_PIXEL_PANNING 19
59 #define ATC_COLOR_SELECT 20
60 #define ATC_CS_C67 0x0c /* Color select bits 6+7 */
61 #define ATC_CS_C45 0x03 /* Color select bits 4+5 */
63 /* Sequencer registers. */
64 #define SEQ_IDX_PORT 0x3c4
65 #define SEQ_DATA_PORT 0x3c5
68 #define SEQ_RESET_ASYNC 0x1
69 #define SEQ_RESET_SYNC 0x2
70 #define SEQ_CLOCKING_MODE 1
71 #define SEQ_CM_SO 0x20 /* Screen off */
72 #define SEQ_CM_89 0x01 /* 8/9 dot clock */
73 #define SEQ_MAP_MASK 2
74 #define SEQ_CHAR_MAP_SELECT 3
75 #define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */
76 #define SEQ_CMS_SAH_SHIFT 5
77 #define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */
78 #define SEQ_CMS_SA_SHIFT 2
79 #define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */
80 #define SEQ_CMS_SBH_SHIFT 4
81 #define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */
82 #define SEQ_CMS_SB_SHIFT 0
83 #define SEQ_MEMORY_MODE 4
84 #define SEQ_MM_C4 0x08 /* Chain 4 */
85 #define SEQ_MM_OE 0x04 /* Odd/even */
86 #define SEQ_MM_EM 0x02 /* Extended memory */
88 /* Graphics controller registers. */
89 #define GC_IDX_PORT 0x3ce
90 #define GC_DATA_PORT 0x3cf
92 #define GC_SET_RESET 0
93 #define GC_ENABLE_SET_RESET 1
94 #define GC_COLOR_COMPARE 2
95 #define GC_DATA_ROTATE 3
96 #define GC_READ_MAP_SELECT 4
98 #define GC_MODE_OE 0x10 /* Odd/even */
99 #define GC_MODE_C4 0x04 /* Chain 4 */
101 #define GC_MISCELLANEOUS 6
102 #define GC_MISC_GM 0x01 /* Graphics/alphanumeric */
103 #define GC_MISC_MM 0x0c /* memory map */
104 #define GC_MISC_MM_SHIFT 2
105 #define GC_COLOR_DONT_CARE 7
106 #define GC_BIT_MASK 8
108 /* CRT controller registers. */
109 #define CRTC_IDX_MONO_PORT 0x3b4
110 #define CRTC_DATA_MONO_PORT 0x3b5
111 #define CRTC_IDX_COLOR_PORT 0x3d4
112 #define CRTC_DATA_COLOR_PORT 0x3d5
114 #define CRTC_HORIZ_TOTAL 0
115 #define CRTC_HORIZ_DISP_END 1
116 #define CRTC_START_HORIZ_BLANK 2
117 #define CRTC_END_HORIZ_BLANK 3
118 #define CRTC_START_HORIZ_RETRACE 4
119 #define CRTC_END_HORIZ_RETRACE 5
120 #define CRTC_VERT_TOTAL 6
121 #define CRTC_OVERFLOW 7
122 #define CRTC_OF_VRS9 0x80 /* VRS bit 9 */
123 #define CRTC_OF_VRS9_SHIFT 7
124 #define CRTC_OF_VDE9 0x40 /* VDE bit 9 */
125 #define CRTC_OF_VDE9_SHIFT 6
126 #define CRTC_OF_VRS8 0x04 /* VRS bit 8 */
127 #define CRTC_OF_VRS8_SHIFT 2
128 #define CRTC_OF_VDE8 0x02 /* VDE bit 8 */
129 #define CRTC_OF_VDE8_SHIFT 1
130 #define CRTC_PRESET_ROW_SCAN 8
131 #define CRTC_MAX_SCAN_LINE 9
132 #define CRTC_MSL_MSL 0x1f
133 #define CRTC_CURSOR_START 10
134 #define CRTC_CS_CO 0x20 /* Cursor off */
135 #define CRTC_CS_CS 0x1f /* Cursor start */
136 #define CRTC_CURSOR_END 11
137 #define CRTC_CE_CE 0x1f /* Cursor end */
138 #define CRTC_START_ADDR_HIGH 12
139 #define CRTC_START_ADDR_LOW 13
140 #define CRTC_CURSOR_LOC_HIGH 14
141 #define CRTC_CURSOR_LOC_LOW 15
142 #define CRTC_VERT_RETRACE_START 16
143 #define CRTC_VERT_RETRACE_END 17
144 #define CRTC_VRE_MASK 0xf
145 #define CRTC_VERT_DISP_END 18
146 #define CRTC_OFFSET 19
147 #define CRTC_UNDERLINE_LOC 20
148 #define CRTC_START_VERT_BLANK 21
149 #define CRTC_END_VERT_BLANK 22
150 #define CRTC_MODE_CONTROL 23
151 #define CRTC_MC_TE 0x80 /* Timing enable */
152 #define CRTC_LINE_COMPARE 24
155 #define DAC_MASK 0x3c6
156 #define DAC_IDX_RD_PORT 0x3c7
157 #define DAC_IDX_WR_PORT 0x3c8
158 #define DAC_DATA_PORT 0x3c9
160 void *vga_init(int io_only);