2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
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8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
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16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/types.h>
36 #include <machine/cpufunc.h>
37 #include <machine/vmm.h>
38 #include <machine/specialreg.h>
49 static int cpu_vendor_intel, cpu_vendor_amd, cpu_vendor_hygon;
52 emulate_wrmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t val)
55 if (cpu_vendor_intel) {
57 case 0xd04: /* Sandy Bridge uncore PMCs */
60 case MSR_BIOS_UPDT_TRIG:
67 } else if (cpu_vendor_amd || cpu_vendor_hygon) {
71 * Ignore writes to hardware configuration MSR.
78 return (0); /* Ignore writes */
84 /* Ignore writes to the PerfEvtSel MSRs */
91 /* Ignore writes to the PerfCtr MSRs */
94 case MSR_P_STATE_CONTROL:
95 /* Ignore write to change the P-state */
106 emulate_rdmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t *val)
110 if (cpu_vendor_intel) {
113 case MSR_IA32_PLATFORM_ID:
114 case MSR_PKG_ENERGY_STATUS:
115 case MSR_PP0_ENERGY_STATUS:
116 case MSR_PP1_ENERGY_STATUS:
117 case MSR_DRAM_ENERGY_STATUS:
120 case MSR_RAPL_POWER_UNIT:
122 * Use the default value documented in section
123 * "RAPL Interfaces" in Intel SDM vol3.
127 case MSR_IA32_FEATURE_CONTROL:
129 * Windows guests check this MSR.
130 * Set the lock bit to avoid writes
133 *val = IA32_FEATURE_CONTROL_LOCK;
139 } else if (cpu_vendor_amd || cpu_vendor_hygon) {
146 * Bios and Kernel Developer's Guides for AMD Families
147 * 12H, 14H, 15H and 16H.
149 *val = 0x01000010; /* Reset value */
150 *val |= 1 << 9; /* MONITOR/MWAIT disable */
157 * The reset value is processor family dependent so
168 * PerfEvtSel MSRs are not properly virtualized so just
174 case MSR_K7_PERFCTR0:
175 case MSR_K7_PERFCTR1:
176 case MSR_K7_PERFCTR2:
177 case MSR_K7_PERFCTR3:
179 * PerfCtr MSRs are not properly virtualized so just
188 * Return the reset value defined in the AMD Bios and
189 * Kernel Developer's Guide.
194 case MSR_P_STATE_LIMIT:
195 case MSR_P_STATE_CONTROL:
196 case MSR_P_STATE_STATUS:
197 case MSR_P_STATE_CONFIG(0): /* P0 configuration */
202 * OpenBSD guests test bit 0 of this MSR to detect if the
203 * workaround for erratum 721 is already applied.
204 * https://support.amd.com/TechDocs/41322_10h_Rev_Gd.pdf
228 ((u_int *)&cpu_vendor)[0] = regs[1];
229 ((u_int *)&cpu_vendor)[1] = regs[3];
230 ((u_int *)&cpu_vendor)[2] = regs[2];
231 cpu_vendor[12] = '\0';
234 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
236 } else if (strcmp(cpu_vendor, "HygonGenuine") == 0) {
237 cpu_vendor_hygon = 1;
238 } else if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
239 cpu_vendor_intel = 1;
241 EPRINTLN("Unknown cpu vendor \"%s\"", cpu_vendor);