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27 .Dd September 30, 2017
32 .Nd control utility for the
44 .Fl m Ar msr Ns = Ns Ar value
50 .Fl m Ar msr Ns &= Ns Ar mask
56 .Fl m Ar msr Ns |= Ns Ar mask
68 .Fl i Ar level,level_type
82 utility can be used to read and write arbitrary machine-specific
86 It can also be used to apply CPU firmware updates.
88 The following options are available:
89 .Bl -tag -width indent
91 Directory paths where to look for microcode images.
92 The option can be specified multiple times.
93 The paths are added in order of the options appearance on the command
94 line, default directories are appended after the user-supplied paths.
96 Do not look for the microcode images in the standard directories.
97 Currently standard directory to look for the microcode update files is
98 .Pa /usr/local/share/cpucontrol .
100 Show value of the specified MSR.
101 MSR register number should be given as a hexadecimal number.
102 The high word is printed first, then the low word is printed second.
103 .It Fl m Ar msr Ns = Ns Ar value
106 in the specified MSR register.
109 argument can be prefixed with ~ operator.
110 In this case the inverted value of argument will be stored in the register.
111 .It Fl m Ar msr Ns &= Ns Ar mask
112 Store the result of bitwise AND operation between
114 and the current MSR value in the MSR register.
117 argument can be prefixed with ~ operator.
118 In this case the inverted value of mask will be used.
119 .It Fl m Ar msr Ns |= Ns Ar mask
120 Store the result of bitwise OR operation between
122 and the current MSR value in the MSR register.
125 argument can be prefixed with ~ operator.
126 In this case the inverted value of mask will be used.
129 Level should be given as a hex number.
130 .It Fl i Ar level,level_type
132 Level and level_type should be given as hex numbers.
134 Apply CPU firmware updates.
137 utility will walk through the configured data directories
138 and apply all firmware updates available for this CPU.
140 Increase the verbosity level.
149 .Dq Li "cpucontrol -m 0x10 /dev/cpuctl0"
151 will read the contents of TSC MSR from CPU 0.
153 To set the CPU 0 TSC MSR register value to 0x1 issue
155 .Dq Li "cpucontrol -m 0x10=0x1 /dev/cpuctl0" .
157 The following command will clear the second bit of TSC register:
159 .Dq Li "cpucontrol -m 0x10&=~0x02 /dev/cpuctl0" .
161 The following command will set the forth and second bit of TSC register:
163 .Dq Li "cpucontrol -m 0x10|=0x0a /dev/cpuctl0" .
167 .Dq Li "cpucontrol -i 0x1 /dev/cpuctl1"
169 will retrieve the CPUID level 0x1 from CPU 1.
171 To perform firmware updates on CPU 0 from images located at
172 .Pa /usr/local/share/cpuctl
173 use the following command:
175 .Dq Li "cpucontrol -nd /usr/local/share/cpuctl -u /dev/cpuctl0"
181 utility first appeared in
186 utility and this manual page was written by
187 .An Stanislav Sedov Aq Mt stas@FreeBSD.org .