usr.sbin/cxgbetool/tcbshowt5.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2018 Chelsio Communications, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 /* Auto-generated file.  Avoid direct editing.     */
  33 /* Edits will be lost when file regenerated.       */
  34 #include <stdio.h>
  35 #include "tcb_common.h"
  36
  37 void t5_display_tcb_aux_0 (_TCBVAR *tvp, int aux)
  38 {
  39
  40
  41
  42
  43
  44
  45
  46   PR("STATE:\n");
  47   PR("  %-12s (%-2u), %s, lock_tid %u, rss_fw %u\n",
  48               spr_tcp_state(val("t_state")),
  49               val("t_state"),
  50               spr_ip_version(val("ip_version")),
  51               val("lock_tid"),
  52               val("rss_fw")
  53              );
  54   PR("  l2t_ix 0x%x, smac sel 0x%x, tos 0x%x\n",
  55               val("l2t_ix"),
  56               val("smac_sel"),
  57               val("tos")
  58               );
  59   PR("  maxseg %u, recv_scaleflag %u, recv_tstmp %u, recv_sack %u\n",
  60               val("t_maxseg"),   val("recv_scale"),
  61               val("recv_tstmp"), val("recv_sack"));
  62
  63
  64   PR("TIMERS:\n"); /* **************************************** */
  65   PR("  timer    %u,  dack_timer      %u\n",
  66            val("timer"), val("dack_timer"));
  67   PR("  mod_schd: tx: %u, rx: %u, reason 0x%1x\n",
  68               val("mod_schd_tx"),
  69               val("mod_schd_rx"),
  70               ((val("mod_schd_reason2")<<2) | (val("mod_schd_reason1")<<1) |
  71                val("mod_schd_reason0"))
  72               );
  73
  74
  75   PR("  max_rt   %-2u, rxtshift        %u, keepalive   %u\n",
  76            val("max_rt"),  val("t_rxtshift"),
  77            val("keepalive"));
  78   PR("  timestamp_offset 0x%x,  timestamp 0x%x\n",
  79            val("timestamp_offset"),val("timestamp"));
  80
  81
  82   PR("  t_rtt_ts_recent_age %u  t_rttseq_recent %u\n",
  83            val("t_rtt_ts_recent_age"), val("t_rtseq_recent"));
  84   PR("  t_srtt %u, t_rttvar %u\n",
  85            val("t_srtt"),val("t_rttvar"));
  86
  87
  88
  89
  90
  91
  92   PR("TRANSMIT BUFFER:\n");   /* *************************** */
  93   PR("  snd_una %u, snd_nxt %u, snd_max %u, tx_max %u\n",
  94               val("snd_una"),val("snd_nxt"),
  95               val("snd_max"),val("tx_max"));
  96   PR("  core_fin %u, tx_hdr_offset %u\n",
  97               val("core_fin"), SEQ_SUB(val("tx_max"),val("snd_una"))
  98              );
  99   if (val("recv_scale") && !val("active_open")) {
 100     PR("  rcv_adv    %-5u << %-2u == %u (recv_scaleflag %u rcv_scale %u active open %u)\n",
 101                 val("rcv_adv"), val("rcv_scale"),
 102                 val("rcv_adv") << val("rcv_scale"),
 103                 val("recv_scale"), val("rcv_scale"), val("active_open"));
 104   } else {
 105     PR("  rcv_adv    %-5u (rcv_scale %-2u recv_scaleflag %u active_open %u)\n",
 106                 val("rcv_adv"), val("rcv_scale"),
 107                 val("recv_scale"), val("active_open"));
 108   }
 109
 110   PR("  snd_cwnd   %-5u  snd_ssthresh %u  snd_rec %u\n",
 111               val("snd_cwnd")    , val("snd_ssthresh"), val("snd_rec")
 112              );
 113
 114
 115
 116
 117   PR("  cctrl: sel %s, ecn %u, ece %u, cwr %u, rfr %u\n",
 118               spr_cctrl_sel(val("cctrl_sel0"),val("cctrl_sel1")),
 119               val("cctrl_ecn"), val("cctrl_ece"), val("cctrl_cwr"),
 120               val("cctrl_rfr"));
 121   PR("  t_dupacks %u, dupack_count_odd %u, fast_recovery %u\n",
 122               val("t_dupacks"), val("dupack_count_odd"),val("fast_recovery"));
 123   PR("  core_more    %u, core_urg,       %u  core_push   %u,",
 124               val("core_more"),val("core_urg"),val("core_push"));
 125   PR("  core_flush %u\n",val("core_flush"));
 126   PR("  nagle        %u, ssws_disable    %u, turbo       %u,",
 127               val("nagle"), val("ssws_disabled"), val("turbo"));
 128   PR("  tx_pdu_out %u\n",val("tx_pdu_out"));
 129   PR("  tx_pace_auto %u, tx_pace_fixed   %u, tx_queue    %u",
 130               val("tx_pace_auto"),val("tx_pace_fixed"),val("tx_queue"));
 131
 132
 133   PR("   tx_quiesce %u\n",val("tx_quiesce"));
 134   PR("  tx_channel   %u, tx_channel1     %u, tx_channel0 %u\n",
 135               val("tx_channel"),
 136               (val("tx_channel")>>1)&1,
 137               val("tx_channel")&1
 138               );
 139
 140
 141
 142
 143   PR("  tx_hdr_ptr   0x%-6x   tx_last_ptr 0x%-6x  tx_compact %u\n",
 144               val("tx_hdr_ptr"),val("tx_last_ptr"),val("tx_compact"));
 145
 146
 147
 148
 149   PR("RECEIVE BUFFER:\n");  /* *************************** */
 150   PR("  last_ack_sent %-10u                      rx_compact %u\n",
 151               val("ts_last_ack_sent"),val("rx_compact"));
 152   PR("  rcv_nxt       %-10u  hdr_off %-10u\n",
 153               val("rcv_nxt"), val("rx_hdr_offset"));
 154   PR("  frag0_idx     %-10u  length  %-10u  rx_ptr  0x%-8x\n",
 155               val("rx_frag0_start_idx"),
 156               val("rx_frag0_len"),
 157               val("rx_ptr"));
 158   PR("  frag1_idx     %-10u  length  %-10u  ",
 159               val("rx_frag1_start_idx_offset"),
 160               val("rx_frag1_len"));
 161
 162
 163
 164
 165   if (val("ulp_type")!=4) { /* RDMA has FRAG1 idx && len, but no ptr?  Should I not display frag1 at all? */
 166     PR("frag1_ptr  0x%-8x\n",val("rx_frag1_ptr"));
 167   } else {
 168     PR("\n");
 169   }
 170
 171
 172   if (val("ulp_type") !=6 && val("ulp_type") != 5 && val("ulp_type") !=4) {
 173     PR("  frag2_idx     %-10u  length  %-10u  frag2_ptr  0x%-8x\n",
 174                 val("rx_frag2_start_idx_offset"),
 175                 val("rx_frag2_len"),
 176                 val("rx_frag2_ptr"));
 177     PR("  frag3_idx     %-10u  length  %-10u  frag3_ptr  0x%-8x\n",
 178                 val("rx_frag3_start_idx_offset"),
 179                 val("rx_frag3_len"),
 180                 val("rx_frag3_ptr"));
 181   }
 182
 183
 184
 185
 186
 187
 188   PR("  peer_fin %u,   rx_pdu_out %u, pdu_len %u\n",
 189               val("peer_fin"),val("rx_pdu_out"), val("pdu_len"));
 190
 191
 192
 193
 194   if (val("recv_scale")) {
 195     PR("  rcv_wnd %u >> snd_scale %u == %u, recv_scaleflag = %u\n",
 196                 val("rcv_wnd"), val("snd_scale"),
 197                 val("rcv_wnd") >> val("snd_scale"),
 198                 val("recv_scale"));
 199   } else {
 200     PR("  rcv_wnd %u.  (snd_scale %u, recv_scaleflag = %u)\n",
 201                 val("rcv_wnd"), val("snd_scale"),
 202                 val("recv_scale"));
 203   }
 204
 205
 206
 207
 208  PR("  dack_mss   %u dack       %u,  dack_not_acked: %u\n",
 209               val("dack_mss"),val("dack"),val("dack_not_acked"));
 210   PR("  rcv_coal   %u rcv_co_psh %u rcv_co_last_psh  %u heart %u\n",
 211               val("rcv_coalesce_enable"),
 212               val("rcv_coalesce_push"),
 213               val("rcv_coalesce_last_psh"),
 214               val("rcv_coalesce_heartbeat"));
 215
 216   PR("  rx_channel %u rx_quiesce %u rx_flow_ctrl_dis %u,",
 217               val("rx_channel"), val("rx_quiesce"),
 218               val("rx_flow_control_disable"));
 219   PR("  rx_flow_ctrl_ddp %u\n",
 220               val("rx_flow_control_ddp"));
 221
 222
 223   PR("MISCELANEOUS:\n");  /* *************************** */
 224   PR("  pend_ctl: 0x%1x, unused_flags: 0x%x,  main_slush: 0x%x\n",
 225               ((val("pend_ctl2")<<2) | (val("pend_ctl1")<<1) |
 226                val("pend_ctl0")),
 227               val("unused"),val("main_slush"));
 228   PR("  Migrating %u, ask_mode %u, non_offload %u, rss_info %u\n",
 229               val("migrating"),
 230               val("ask_mode"), val("non_offload"), val("rss_info"));
 231   PR("  ULP: ulp_type %u (%s), ulp_raw %u",
 232               val("ulp_type"), spr_ulp_type(val("ulp_type")),
 233               val("ulp_raw"));
 234
 235
 236   if (aux==1) {
 237     PR(",  ulp_ext %u",val("ulp_ext"));
 238   }
 239   PR("\n");
 240
 241
 242
 243
 244   PR("  RDMA: error   %u, flm_err %u\n",
 245               val("rdma_error"), val("rdma_flm_error"));
 246
 247
 248 }
 249 void t5_display_tcb_aux_1 (_TCBVAR *tvp, int aux)
 250 {
 251
 252
 253
 254   PR("    aux1_slush0: 0x%x aux1_slush1 0x%x\n",
 255               val("aux1_slush0"), val("aux1_slush1"));
 256   PR("    pdu_hdr_len %u\n",val("pdu_hdr_len"));
 257
 258
 259
 260 }
 261 void t5_display_tcb_aux_2 (_TCBVAR *tvp, int aux)
 262 {
 263
 264
 265
 266
 267   PR("    qp_id %u, pd_id %u, stag %u\n",
 268               val("qp_id"), val("pd_id"),val("stag"));
 269   PR("    irs_ulp %u, iss_ulp %u\n",
 270               val("irs_ulp"),val("iss_ulp"));
 271   PR("    tx_pdu_len %u\n",
 272               val("tx_pdu_len"));
 273   PR("    cq_idx_sq %u, cq_idx_rq %u\n",
 274               val("cq_idx_sq"),val("cq_idx_rq"));
 275   PR("    rq_start %u, rq_MSN %u, rq_max_off %u, rq_write_ptr %u\n",
 276               val("rq_start"),val("rq_msn"),val("rq_max_offset"),
 277               val("rq_write_ptr"));
 278   PR("    L_valid %u, rdmap opcode %u\n",
 279               val("ord_l_bit_vld"),val("rdmap_opcode"));
 280   PR("    tx_flush: %u, tx_oos_rxmt %u, tx_oos_txmt %u\n",
 281               val("tx_flush"),val("tx_oos_rxmt"),val("tx_oos_txmt"));
 282
 283
 284
 285
 286 }
 287 void t5_display_tcb_aux_3 (_TCBVAR *tvp, int aux)
 288 {
 289
 290
 291
 292
 293   PR("  aux3_slush: 0x%x, unused: buf0 0x%x, buf1: 0x%x, main: 0x%x\n",
 294               val("aux3_slush"),val("ddp_buf0_unused"),val("ddp_buf1_unused"),
 295               val("ddp_main_unused"));
 296
 297
 298
 299
 300
 301   PR("  DDP: DDPOFF  ActBuf  IndOut  WaitFrag  Rx2Tx  BufInf\n");
 302   PR("         %u       %u       %u        %u        %u      %u\n",
 303               val("ddp_off"),val("ddp_active_buf"),val("ddp_indicate_out"),
 304               val("ddp_wait_frag"),val("ddp_rx2tx"),val("ddp_buf_inf")
 305              );
 306
 307
 308
 309
 310
 311   PR("        Ind  PshfEn PushDis Flush NoInvalidate\n");
 312   PR("   Buf0: %u      %u       %u    %u       %u\n",
 313               val("ddp_buf0_indicate"),
 314               val("ddp_pshf_enable_0"), val("ddp_push_disable_0"),
 315               val("ddp_buf0_flush"),  val("ddp_psh_no_invalidate0")
 316                );
 317   PR("   Buf1: %u      %u       %u    %u       %u\n",
 318               val("ddp_buf1_indicate"),
 319               val("ddp_pshf_enable_1"), val("ddp_push_disable_1"),
 320               val("ddp_buf1_flush"),  val("ddp_psh_no_invalidate1")
 321                );
 322
 323
 324
 325
 326
 327
 328
 329
 330
 331
 332   PR("        Valid  Offset   Length    Tag\n");
 333   PR("   Buf0:  %u    0x%6.6x 0x%6.6x  0x%8.8x",
 334               val("ddp_buf0_valid"),val("rx_ddp_buf0_offset"),
 335               val("rx_ddp_buf0_len"),val("rx_ddp_buf0_tag")
 336
 337
 338                );
 339   if      (0==val("ddp_off") && 1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
 340     PR("   (Active)\n");
 341   } else {
 342     PR(" (Inactive)\n");
 343   }
 344
 345
 346   PR("   Buf1:  %u    0x%6.6x 0x%6.6x  0x%8.8x",
 347               val("ddp_buf1_valid"),val("rx_ddp_buf1_offset"),
 348               val("rx_ddp_buf1_len"),val("rx_ddp_buf1_tag")
 349
 350
 351                );
 352
 353
 354   if      (0==val("ddp_off") && 1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
 355     PR("   (Active)\n");
 356   } else {
 357     PR(" (Inactive)\n");
 358   }
 359
 360
 361
 362
 363
 364
 365   if    (1==val("ddp_off")) {
 366     PR("   DDP is off (which also disables indicate)\n");
 367   } else if (1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
 368     PR("   Data being DDP'ed to buf 0, ");
 369     PR("which has %u - %u = %u bytes of space left\n",
 370                 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
 371                 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
 372                );
 373     if (1==val("ddp_buf1_valid")) {
 374       PR("   And buf1, which is also valid, has %u - %u = %u bytes of space left\n",
 375                   val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
 376                   val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
 377                  );
 378     }
 379   } else if (1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
 380     PR("   Data being DDP'ed to buf 1, ");
 381     PR("which has %u - %u = %u bytes of space left\n",
 382                 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
 383                 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
 384                );
 385     if (1==val("ddp_buf0_valid")) {
 386       PR("   And buf0, which is also valid, has %u - %u = %u bytes of space left\n",
 387                   val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
 388                   val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
 389                  );
 390     }
 391   } else if (0==val("ddp_buf0_valid") && 1==val("ddp_buf1_valid") && 0==val("ddp_active_buf")) {
 392     PR("   !!! Invalid DDP buf 1 valid, but buf 0 active.\n");
 393   } else if (1==val("ddp_buf0_valid") && 0==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
 394     PR("   !!! Invalid DDP buf 0 valid, but buf 1 active.\n");
 395   } else {
 396     PR("   DDP is enabled, but no buffers are active && valid.\n");
 397
 398
 399
 400
 401     if (0==val("ddp_indicate_out")) {
 402       if (0==val("ddp_buf0_indicate") && 0==val("ddp_buf1_indicate")) {
 403         PR("   0 length Indicate buffers ");
 404         if (0==val("rx_hdr_offset")) {
 405           PR("will cause new data to be held in PMRX.\n");
 406         } else {
 407           PR("is causing %u bytes to be held in PMRX\n",
 408                       val("rx_hdr_offset"));
 409         }
 410       } else {
 411         PR("   Data being indicated to host\n");
 412       }
 413     } else if (1==val("ddp_indicate_out")) {
 414       PR("   Indicate is off, which ");
 415       if (0==val("rx_hdr_offset")) {
 416         PR("will cause new data to be held in PMRX.\n");
 417       } else {
 418         PR("is causing %u bytes to be held in PMRX\n",
 419                     val("rx_hdr_offset"));
 420       }
 421     }
 422   }
 423
 424
 425
 426
 427 }