2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Chelsio Communications, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 /* Auto-generated file. Avoid direct editing. */
33 /* Edits will be lost when file regenerated. */
35 #include "tcb_common.h"
37 void t6_display_tcb_aux_0 (_TCBVAR *tvp, int aux)
47 PR(" %-12s (%-2u), %s, lock_tid %u, rss_fw %u\n",
48 spr_tcp_state(val("t_state")),
50 spr_ip_version(val("ip_version")),
54 PR(" l2t_ix 0x%x, smac sel 0x%x, tos 0x%x\n",
59 PR(" maxseg %u, recv_scaleflag %u, recv_tstmp %u, recv_sack %u\n",
60 val("t_maxseg"), val("recv_scale"),
61 val("recv_tstmp"), val("recv_sack"));
64 PR("TIMERS:\n"); /* **************************************** */
65 PR(" timer %u, dack_timer %u\n",
66 val("timer"), val("dack_timer"));
67 PR(" mod_schd: tx: %u, rx: %u, reason 0x%1x\n",
70 ((val("mod_schd_reason2")<<2) | (val("mod_schd_reason1")<<1) |
71 val("mod_schd_reason0"))
75 PR(" max_rt %-2u, rxtshift %u, keepalive %u\n",
76 val("max_rt"), val("t_rxtshift"),
78 PR(" timestamp_offset 0x%x, timestamp 0x%x\n",
79 val("timestamp_offset"),val("timestamp"));
82 PR(" t_rtt_ts_recent_age %u t_rttseq_recent %u\n",
83 val("t_rtt_ts_recent_age"), val("t_rtseq_recent"));
84 PR(" t_srtt %u, t_rttvar %u\n",
85 val("t_srtt"),val("t_rttvar"));
92 PR("TRANSMIT BUFFER:\n"); /* *************************** */
93 PR(" snd_una %u, snd_nxt %u, snd_max %u, tx_max %u\n",
94 val("snd_una"),val("snd_nxt"),
95 val("snd_max"),val("tx_max"));
96 PR(" core_fin %u, tx_hdr_offset %u\n",
97 val("core_fin"), SEQ_SUB(val("tx_max"),val("snd_una"))
99 if (val("recv_scale") && !val("active_open")) {
100 PR(" rcv_adv %-5u << %-2u == %u (recv_scaleflag %u rcv_scale %u active open %u)\n",
101 val("rcv_adv"), val("rcv_scale"),
102 val("rcv_adv") << val("rcv_scale"),
103 val("recv_scale"), val("rcv_scale"), val("active_open"));
105 PR(" rcv_adv %-5u (rcv_scale %-2u recv_scaleflag %u active_open %u)\n",
106 val("rcv_adv"), val("rcv_scale"),
107 val("recv_scale"), val("active_open"));
110 PR(" snd_cwnd %-5u snd_ssthresh %u snd_rec %u\n",
111 val("snd_cwnd") , val("snd_ssthresh"), val("snd_rec")
117 PR(" cctrl: sel %s, ecn %u, ece %u, cwr %u, rfr %u\n",
118 spr_cctrl_sel(val("cctrl_sel0"),val("cctrl_sel1")),
119 val("cctrl_ecn"), val("cctrl_ece"), val("cctrl_cwr"),
121 PR(" t_dupacks %u, dupack_count_odd %u, fast_recovery %u\n",
122 val("t_dupacks"), val("dupack_count_odd"),val("fast_recovery"));
123 PR(" core_more %u, core_urg, %u core_push %u,",
124 val("core_more"),val("core_urg"),val("core_push"));
125 PR(" core_flush %u\n",val("core_flush"));
126 PR(" nagle %u, ssws_disable %u, turbo %u,",
127 val("nagle"), val("ssws_disabled"), val("turbo"));
128 PR(" tx_pdu_out %u\n",val("tx_pdu_out"));
129 PR(" tx_pace_auto %u, tx_pace_fixed %u, tx_queue %u",
130 val("tx_pace_auto"),val("tx_pace_fixed"),val("tx_queue"));
133 PR(" tx_quiesce %u\n",val("tx_quiesce"));
134 PR(" tx_channel %u, tx_channel1 %u, tx_channel0 %u\n",
136 (val("tx_channel")>>1)&1,
143 PR(" tx_hdr_ptr 0x%-6x tx_last_ptr 0x%-6x tx_compact %u\n",
144 val("tx_hdr_ptr"),val("tx_last_ptr"),val("tx_compact"));
149 PR("RECEIVE BUFFER:\n"); /* *************************** */
150 PR(" last_ack_sent %-10u rx_compact %u\n",
151 val("ts_last_ack_sent"),val("rx_compact"));
152 PR(" rcv_nxt %-10u hdr_off %-10u\n",
153 val("rcv_nxt"), val("rx_hdr_offset"));
154 PR(" frag0_idx %-10u length %-10u frag0_ptr 0x%-8x\n",
155 val("rx_frag0_start_idx"),
158 PR(" frag1_idx %-10u length %-10u ",
159 val("rx_frag1_start_idx_offset"),
160 val("rx_frag1_len"));
165 if (val("ulp_type")!=4) { /* RDMA has FRAG1 idx && len, but no ptr? Should I not display frag1 at all? */
166 PR("frag1_ptr 0x%-8x\n",val("rx_frag1_ptr"));
172 if (val("ulp_type") != 9 && val("ulp_type")!=8 && val("ulp_type") !=6 &&
173 val("ulp_type") != 5 && val("ulp_type") !=4) {
174 PR(" frag2_idx %-10u length %-10u frag2_ptr 0x%-8x\n",
175 val("rx_frag2_start_idx_offset"),
177 val("rx_frag2_ptr"));
178 PR(" frag3_idx %-10u length %-10u frag3_ptr 0x%-8x\n",
179 val("rx_frag3_start_idx_offset"),
181 val("rx_frag3_ptr"));
189 PR(" peer_fin %u, rx_pdu_out %u, pdu_len %u\n",
190 val("peer_fin"),val("rx_pdu_out"), val("pdu_len"));
195 if (val("recv_scale")) {
196 PR(" rcv_wnd %u >> snd_scale %u == %u, recv_scaleflag = %u\n",
197 val("rcv_wnd"), val("snd_scale"),
198 val("rcv_wnd") >> val("snd_scale"),
201 PR(" rcv_wnd %u. (snd_scale %u, recv_scaleflag = %u)\n",
202 val("rcv_wnd"), val("snd_scale"),
209 PR(" dack_mss %u dack %u, dack_not_acked: %u\n",
210 val("dack_mss"),val("dack"),val("dack_not_acked"));
211 PR(" rcv_coal %u rcv_co_psh %u rcv_co_last_psh %u heart %u\n",
212 val("rcv_coalesce_enable"),
213 val("rcv_coalesce_push"),
214 val("rcv_coalesce_last_psh"),
215 val("rcv_coalesce_heartbeat"));
217 PR(" rx_channel %u rx_quiesce %u rx_flow_ctrl_dis %u,",
218 val("rx_channel"), val("rx_quiesce"),
219 val("rx_flow_control_disable"));
220 PR(" rx_flow_ctrl_ddp %u\n",
221 val("rx_flow_control_ddp"));
224 PR("MISCELANEOUS:\n"); /* *************************** */
225 PR(" pend_ctl: 0x%1x, core_bypass: 0x%x, main_slush: 0x%x\n",
226 ((val("pend_ctl2")<<2) | (val("pend_ctl1")<<1) |
228 val("core_bypass"),val("main_slush"));
229 PR(" Migrating %u, ask_mode %u, non_offload %u, rss_info %u\n",
231 val("ask_mode"), val("non_offload"), val("rss_info"));
232 PR(" ULP: ulp_type %u (%s), ulp_raw %u",
233 val("ulp_type"), spr_ulp_type(val("ulp_type")),
238 PR(", ulp_ext %u",val("ulp_ext"));
245 PR(" RDMA: error %u, flm_err %u\n",
246 val("rdma_error"), val("rdma_flm_error"));
250 void t6_display_tcb_aux_1 (_TCBVAR *tvp, int aux)
255 PR(" aux1_slush0: 0x%x aux1_slush1 0x%x\n",
256 val("aux1_slush0"), val("aux1_slush1"));
257 PR(" pdu_hdr_len %u\n",val("pdu_hdr_len"));
262 void t6_display_tcb_aux_2 (_TCBVAR *tvp, int aux)
268 PR(" qp_id %u, pd_id %u, stag %u\n",
269 val("qp_id"), val("pd_id"),val("stag"));
270 PR(" irs_ulp %u, iss_ulp %u\n",
271 val("irs_ulp"),val("iss_ulp"));
272 PR(" tx_pdu_len %u\n",
274 PR(" cq_idx_sq %u, cq_idx_rq %u\n",
275 val("cq_idx_sq"),val("cq_idx_rq"));
276 PR(" rq_start %u, rq_MSN %u, rq_max_off %u, rq_write_ptr %u\n",
277 val("rq_start"),val("rq_msn"),val("rq_max_offset"),
278 val("rq_write_ptr"));
279 PR(" L_valid %u, rdmap opcode %u\n",
280 val("ord_l_bit_vld"),val("rdmap_opcode"));
281 PR(" tx_flush: %u, tx_oos_rxmt %u, tx_oos_txmt %u\n",
282 val("tx_flush"),val("tx_oos_rxmt"),val("tx_oos_txmt"));
288 void t6_display_tcb_aux_3 (_TCBVAR *tvp, int aux)
296 PR(" aux3_slush: 0x%x, unused: buf0 0x%x, buf1: 0x%x\n",
297 val("aux3_slush"),val("ddp_buf0_unused"),val("ddp_buf1_unused"));
300 PR(" ind_full: %u, tls_key_mode: %u\n",
301 val("ddp_indicate_fll"),val("tls_key_mode"));
304 PR(" DDP: DDPOFF ActBuf IndOut WaitFrag Rx2Tx BufInf\n");
305 PR(" %u %u %u %u %u %u\n",
306 val("ddp_off"),val("ddp_active_buf"),val("ddp_indicate_out"),
307 val("ddp_wait_frag"),val("ddp_rx2tx"),val("ddp_buf_inf")
311 PR(" Ind PshfEn PushDis Flush NoInvalidate\n");
312 PR(" Buf0: %u %u %u %u %u\n",
313 val("ddp_buf0_indicate"),
314 val("ddp_pshf_enable_0"), val("ddp_push_disable_0"),
315 val("ddp_buf0_flush"), val("ddp_psh_no_invalidate0")
317 PR(" Buf1: %u %u %u %u %u\n",
318 val("ddp_buf1_indicate"),
319 val("ddp_pshf_enable_1"), val("ddp_push_disable_1"),
320 val("ddp_buf1_flush"), val("ddp_psh_no_invalidate1")
332 PR(" Valid Offset Length Tag\n");
333 PR(" Buf0: %u 0x%6.6x 0x%6.6x 0x%8.8x",
334 val("ddp_buf0_valid"),val("rx_ddp_buf0_offset"),
335 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_tag")
339 if (0==val("ddp_off") && 1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
346 PR(" Buf1: %u 0x%6.6x 0x%6.6x 0x%8.8x",
347 val("ddp_buf1_valid"),val("rx_ddp_buf1_offset"),
348 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_tag")
354 if (0==val("ddp_off") && 1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
365 if (1==val("ddp_off")) {
366 PR(" DDP is off (which also disables indicate)\n");
367 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
368 PR(" Data being DDP'ed to buf 0, ");
369 PR("which has %u - %u = %u bytes of space left\n",
370 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
371 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
373 if (1==val("ddp_buf1_valid")) {
374 PR(" And buf1, which is also valid, has %u - %u = %u bytes of space left\n",
375 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
376 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
379 } else if (1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
380 PR(" Data being DDP'ed to buf 1, ");
381 PR("which has %u - %u = %u bytes of space left\n",
382 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
383 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
385 if (1==val("ddp_buf0_valid")) {
386 PR(" And buf0, which is also valid, has %u - %u = %u bytes of space left\n",
387 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
388 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
391 } else if (0==val("ddp_buf0_valid") && 1==val("ddp_buf1_valid") && 0==val("ddp_active_buf")) {
392 PR(" !!! Invalid DDP buf 1 valid, but buf 0 active.\n");
393 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
394 PR(" !!! Invalid DDP buf 0 valid, but buf 1 active.\n");
396 PR(" DDP is enabled, but no buffers are active && valid.\n");
401 if (0==val("ddp_indicate_out")) {
402 if (0==val("ddp_buf0_indicate") && 0==val("ddp_buf1_indicate")) {
403 PR(" 0 length Indicate buffers ");
404 if (0==val("rx_hdr_offset")) {
405 PR("will cause new data to be held in PMRX.\n");
407 PR("is causing %u bytes to be held in PMRX\n",
408 val("rx_hdr_offset"));
411 PR(" Data being indicated to host\n");
413 } else if (1==val("ddp_indicate_out")) {
414 PR(" Indicate is off, which ");
415 if (0==val("rx_hdr_offset")) {
416 PR("will cause new data to be held in PMRX.\n");
418 PR("is causing %u bytes to be held in PMRX\n",
419 val("rx_hdr_offset"));
428 void t6_display_tcb_aux_4 (_TCBVAR *tvp, int aux)
433 PR("TLS: offset: 0x%6.6x, len:0x%6.6x, flags: 0x%4.4x\n",
434 val("rx_tls_buf_offset"),val("rx_tls_buf_len"),
435 val("rx_tls_flags"));
436 PR(" seq: 0x%llx \n",val64("rx_tls_seq"));
437 PR(" tag: 0x%8.8x, key:0x%8.8x\n",
438 val("rx_tls_buf_tag"),val("rx_tls_key_tag"));